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1. 发明授权

US4395646A Logic performing cell for use in array structures 失效
标题翻译：用于阵列结构的逻辑执行单元
公开(公告)号：US4395646A
公开(公告)日：1983-07-26
申请号：US203170
申请日：1980-11-03
申请人： Moises Cases , Wayne R. Kraft , Victor S. Moore , William L. Stahl, Jr. , Nandor G. Thoma
发明人： Moises Cases , Wayne R. Kraft , Victor S. Moore , William L. Stahl, Jr. , Nandor G. Thoma
IPC分类号： H01L27/088 , H01L27/112 , H03K19/0944 , H03K19/177 , H03K19/017 , H03K19/094
CPC分类号： H03K19/1778 , H01L27/0883 , H01L27/112 , H03K19/09445 , H03K19/1772 , H03K19/17728
摘要： A logic performing cell for use in array structures is provided which allows greater density fabrication in integrated circuits and reduces operational delays. The array has a plurality of output lines intercepted by a plurality of orthogonally oriented input lines, with elements in the form of a three terminal device located at each of the intersections of the input and output lines so that logical functions are performed on interrogation signals placed on the input lines and the responses thereto placed on the output lines. The three terminal device transfer gates are connected in groups of series strings which are connected in parallel to a recombination line. These groups of series connected transfer gates comprise a programmed mix of enhancement and depletion devices. Each logic function of each group of transfer gates establishes an output which, when coupled to the recombining output circuit line, provides an overall logic function for the logic performing cell.
摘要翻译：提供了用于阵列结构的逻辑执行单元，其允许在集成电路中进行更大的密度制造并且减少操作延迟。阵列具有由多个正交取向的输入线截取的多个输出线，其中三个终端装置形式的元件位于输入和输出线的每个交叉点处，使得在放置的询问信号上执行逻辑功能在输入线上和对输出线上的响应。三个端子器件传输门以串联串联的方式连接，并联到复合线。这些串联连接的传输门组包括增强和耗尽装置的编程组合。每组传输门的每个逻辑功能建立一个输出，当耦合到重新组合的输出电路线时，该逻辑执行单元提供总逻辑功能。

2. 发明授权

US4488067A Tristate driver circuit with low standby power consumption 失效
标题翻译：三态驱动电路具有低待机功耗
公开(公告)号：US4488067A
公开(公告)日：1984-12-11
申请号：US533392
申请日：1983-09-19
申请人： Wayne R. Kraft , Victor S. Moore , William L. Stahl, Jr. , Nandor G. Thoma
发明人： Wayne R. Kraft , Victor S. Moore , William L. Stahl, Jr. , Nandor G. Thoma
IPC分类号： H03K19/0175 , H03K19/094 , H03K19/20 , H03K19/017
CPC分类号： H03K19/09429
摘要： Improved tristate control circuitry is provided for a driver circuit formed on an integrated circuit chip. A parallel-connected combination of a depletion mode transistor and an enhancement mode transistor is connected in series in the voltage supply path for the driver circuit for controlling whether the driver circuit is in an active mode or a standby mode by controlling the supplying of operating voltage thereto. A further enhancement mode transistor provides a shunting action between the driver circuit side of the parallel-connected transistors and circuit ground to further aid in the control of the driver circuit operating mode.
摘要翻译：为在集成电路芯片上形成的驱动电路提供改进的三态控制电路。耗尽型晶体管和增强型晶体管的并联组合串联连接在用于驱动电路的电压供给路径中，用于通过控制提供工作电压来控制驱动电路是处于活动模式还是待机模式到此。另外的增强模式晶体管在并联晶体管的驱动器电路侧和电路接地之间提供分流动作，以进一步有助于控制驱动器电路工作模式。

3. 发明授权

US4531068A Bus line precharging tristate driver circuit 失效
标题翻译：总线预充电三态驱动电路
公开(公告)号：US4531068A
公开(公告)日：1985-07-23
申请号：US533393
申请日：1983-09-19
申请人： Wayne R. Kraft , Victor S. Moore , William L. Stahl, Jr. , Nandor G. Thoma
发明人： Wayne R. Kraft , Victor S. Moore , William L. Stahl, Jr. , Nandor G. Thoma
IPC分类号： H03K19/0175 , H03K5/02 , H03K19/094 , H03K19/20 , H03K19/003
CPC分类号： H03K5/023 , H03K19/09425 , H03K19/09429
摘要： A tristate driver circuit is provided on an integrated circuit chip for driving a bus line or signal line located off of the chip. This circuit very rapidly charges the bus line or signal line to positive voltage level each time and just before it switches to its tristate or high impedance output condition. This eliminates the need for a pull-up resistor or pull-up transistor to be connected to the off-chip bus line or signal line.
摘要翻译：在用于驱动位于芯片外的总线或信号线的集成电路芯片上提供三态驱动器电路。该电路非常快速地将总线或信号线充电至正电压电平，并且恰好在其切换到其三态或高阻抗输出条件之前。这样就不需要连接到片外总线或信号线的上拉电阻或上拉晶体管。

4. 发明授权

US4484268A Apparatus and method for decoding an operation code using a plurality of multiplexed programmable logic arrays 失效
标题翻译：使用多个可复用可编程逻辑阵列对操作码进行解码的装置和方法
公开(公告)号：US4484268A
公开(公告)日：1984-11-20
申请号：US350661
申请日：1982-02-22
申请人： Nandor G. Thoma , Victor S. Moore , Wayne R. Kraft
发明人： Nandor G. Thoma , Victor S. Moore , Wayne R. Kraft
IPC分类号： G06F9/22 , G06F9/26 , G06F9/30 , H03K19/177 , G06F9/00
CPC分类号： G06F9/267
摘要： A plurality of programmable logic arrays (PLA's) operate in parallel, each to decode an operation code (OP code). A portion of the OP code is decoded to select one of the PLA's, and the decoded OP code from the selected PLA is gated through a multiplexer to provide the control code corresponding to the OP code.
摘要翻译：多个可编程逻辑阵列（PLA）并行操作，每个解码操作码（OP代码）。对OP代码的一部分进行解码以选择PLA中的一个，并且通过多路复用器选择来自所选择的PLA的解码的OP代码以提供对应于OP代码的控制代码。

5. 发明授权

US4947369A Microword generation mechanism utilizing a separate branch decision programmable logic array 失效
标题翻译：微剑生成机制利用单独的分支决策可编程逻辑阵列
公开(公告)号：US4947369A
公开(公告)日：1990-08-07
申请号：US416881
申请日：1989-10-04
申请人： Nandor G. Thoma , Victor S. Moore , Wayne R. Kraft
发明人： Nandor G. Thoma , Victor S. Moore , Wayne R. Kraft
IPC分类号： G06F9/26 , G06F9/42
CPC分类号： G06F9/264
摘要： A microword generation mechanism is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed digital data processor. This microword generation mechanism includes programmable logic array means responsive to the processor instructions for producing the appropriate microword sequences. The microword generation mechanism also includes condition indicator circuitry for supplying indicator signals indicating whether the results of arithmetic and logic operations in the processor meet certain types of conditions. The microword generation mechanism further includes a condition testing programmable logic array responsive to the condition field of a conditional branch type processor instruction for testing the appropriate indicator signal or signals and causing a branch type microword sequence to be produced if the specified condition is met.
摘要翻译：提供了一种微词生成机制，用于产生用于控制微程序数字数据处理器中的处理器指令的执行的微词序列。该微词生成机制包括响应于处理器指令以产生适当的微词序列的可编程逻辑阵列装置。微字生成机构还包括用于提供指示信号的条件指示器电路，其指示处理器中的算术和逻辑运算的结果是否符合某些类型的条件。微字生成机构还包括响应于条件分支型处理器指令的条件字段的条件测试可编程逻辑阵列，用于测试适当的指示符信号或者如果满足指定条件则产生分支型微字序列。

6. 发明授权

US4354228A Flexible processor on a single semiconductor substrate using a plurality of arrays 失效
标题翻译：使用多个阵列的单个半导体衬底上的柔性处理器
公开(公告)号：US4354228A
公开(公告)日：1982-10-12
申请号：US105711
申请日：1979-12-20
申请人： Victor S. Moore , Wayne R. Kraft , Joseph C. Rhodes, Jr. , William L. Stahl, Jr.
发明人： Victor S. Moore , Wayne R. Kraft , Joseph C. Rhodes, Jr. , William L. Stahl, Jr.
IPC分类号： G06F7/00 , G06F9/22 , G06F15/78
CPC分类号： G06F9/223
摘要： A processor is provided that is fabricated on a single semiconductor substrate. The processor includes an AND array for receiving program instructions from input sources external of the processor and for generating product signals. An OR array is provided and interconnected to the AND array for receiving the product signals and for generating a plurality of control signals. A register array receives ones of the plurality of control signals and transfers data between the processor and data sources external of the processor. An arithmetic and logic unit array is also provided on the semiconductor substrate and interconnected to the register array and the OR array for executing operations on data received from the register array in accordance with ones of the plurality of control signals to generate output data. A control register is further provided and is interconnected to the OR array and the AND array for receiving ones of the plurality of control signals for controlling execution of the program instructions within the AND array.
摘要翻译：提供了制造在单个半导体衬底上的处理器。处理器包括用于从处理器外部的输入源接收程序指令并用于产生乘积信号的AND阵列。提供OR阵列并将其互连到AND阵列，用于接收产品信号并产生多个控制信号。寄存器阵列接收多个控制信号中的一个并且在处理器和处理器外部的数据源之间传送数据。还在半导体衬底上提供了一个算术和逻辑单元阵列，并将其与寄存器阵列和OR阵列互连，以根据多个控制信号中的一个从寄存器阵列接收的数据执行操作，以产生输出数据。进一步提供控制寄存器，并且与OR阵列和AND阵列互连，用于接收多个控制信号中的一个，以控制AND阵列内的程序指令的执行。

7. 发明授权

US4594661A Microword control system utilizing multiplexed programmable logic arrays 失效
标题翻译：微控制系统利用多路复用可编程逻辑阵列
公开(公告)号：US4594661A
公开(公告)日：1986-06-10
申请号：US350660
申请日：1982-02-22
申请人： Victor S. Moore , Gerard A. Veneski , Tony E. Parker , Joseph C. Rhodes, Jr. , Wayne R. Kraft , William L. Stahl, Jr.
发明人： Victor S. Moore , Gerard A. Veneski , Tony E. Parker , Joseph C. Rhodes, Jr. , Wayne R. Kraft , William L. Stahl, Jr.
IPC分类号： G06F9/22 , G06F9/28
CPC分类号： G06F9/223 , G06F9/28
摘要： A microword control system is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed digital data processor. This microword control system includes a plurality of programmable logic array mechanisms responsive to the processor instruction to be executed for individually producing different ones of the microwords needed to execute such instruction. This microword control system also includes microword-responsive control circuitry for controlling the operation of the data processor. This microword control system further includes multiplexing circuitry for supplying microwords from different ones of the programmable logic array mechanisms to the control circuitry during different time intervals.
摘要翻译：提供了一种微词控制系统，用于产生用于控制微程序数字数据处理器中处理器指令执行的微词序列。该微词控制系统包括多个可编程逻辑阵列机构，其响应于要执行的处理器指令来单独产生执行该指令所需的不同的微剑。该微词控制系统还包括用于控制数据处理器的操作的微字响应控制电路。该微词控制系统还包括用于在不同的时间间隔期间将不同的可编程逻辑阵列机构的微词提供给控制电路的多路复用电路。

8. 发明授权

US4608649A Differential cascode voltage switch (DCVS) master slice for high efficiency/custom density physical design 失效
标题翻译：差分共源共栅电压开关（DCVS）主片用于高效率/定制密度物理设计
公开(公告)号：US4608649A
公开(公告)日：1986-08-26
申请号：US508451
申请日：1983-06-27
申请人： James W. Davis , Victor S. Moore , Nandor G. Thoma
发明人： James W. Davis , Victor S. Moore , Nandor G. Thoma
IPC分类号： G06F17/50 , H01L27/118 , H03K19/173 , H03K19/094
CPC分类号： H01L27/11803 , G06F17/5068 , H03K19/1738
摘要： A topological physical circuit design is utilized for the support of a Differential Cascode Voltage Switch circuit/logic technology in an Automated Placement-Wiring environment. This physical entity takes the form of a "brickwall" set of transistors in a Master Slice image which may be stored and later personalized.
摘要翻译：拓扑物理电路设计用于在自动放置布线环境中支持差分串联电压开关电路/逻辑技术。该物理实体采用可以存储和稍后个性化的主切片图像中的“砖墙”一组晶体管的形式。

9. 发明授权

US4509114A Microword control mechanism utilizing a programmable logic array and a sequence counter 失效
标题翻译：微控制机制利用可编程逻辑阵列和序列计数器
公开(公告)号：US4509114A
公开(公告)日：1985-04-02
申请号：US350662
申请日：1982-02-22
申请人： Joel C. Leininger , Victor S. Moore , William L. Stahl, Jr.
发明人： Joel C. Leininger , Victor S. Moore , William L. Stahl, Jr.
IPC分类号： G06F9/22 , G06F9/26
CPC分类号： G06F9/262
摘要： A microword control mechanism is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed data processor. This microword control mechanism includes circuitry (15, 20) responsive to a processor instruction to be executed for providing an instruction dependent signal uniquely representative of such instruction. This microword control mechanism also includes sequence counter circuitry (18) for supplying a sequence of number signals. This microword control mechanism further includes a programmable logic array (17) responsive to the instruction dependent signal and to the sequence of number signals for producing a sequence of microwords needed to execute the processor instruction.
摘要翻译：提供了一种微词控制机制，用于产生用于控制微程序数据处理器中处理器指令执行的微词序列。该微词控制机制包括响应于要执行的处理器指令以提供唯一表示这种指令的指令相关信号的电路（15,20）。该微字控制机构还包括用于提供一系列数字信号的序列计数器电路（18）。该微字控制机构还包括响应于指令相关信号和数字信号序列的可编程逻辑阵列（17），用于产生执行处理器指令所需的一系列微字。

10. 发明授权

US4931989A Microword generation mechanism utilizing a separate programmable logic array for first microwords 失效
标题翻译：微剑生成机制利用单独的可编程逻辑阵列为第一个微词
公开(公告)号：US4931989A
公开(公告)日：1990-06-05
申请号：US38556
申请日：1987-04-15
申请人： Joseph C. Rhodes, Jr. , Victor S. Moore , Wayne R. Kraft , John W. Barrs
发明人： Joseph C. Rhodes, Jr. , Victor S. Moore , Wayne R. Kraft , John W. Barrs
IPC分类号： G06F9/28 , H04N5/225
CPC分类号： G06F9/28 , H04N5/2253
摘要： A microword generation mechanism is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed digital data processor. This microword generation mechanism includes a first programmable logic array mechanism responsive to the processor instruction to be executed for providing the first microword needed in the execution of such instruction. This microword generation mechanism also includes a second programmable logic array mechanism responsive to the processor instruction to be executed for providing the second microword needed in the execution of such instruction. This microword generation mechanism further includes at least one additional programmable logic array mechanism responsive to the processor instruction to be executed for providing the remainder of the microwords needed to execute such instruction.
摘要翻译：提供了一种微词生成机制，用于产生用于控制微程序数字数据处理器中的处理器指令的执行的微词序列。该微字生成机构包括响应于要执行的处理器指令以提供执行这样的指令所需的第一微字的第一可编程逻辑阵列机构。该微字生成机构还包括响应于要执行的处理器指令以提供执行这样的指令所需的第二微字的第二可编程逻辑阵列机制。该微字生成机构进一步包括至少一个额外的可编程逻辑阵列机构，其响应于要执行的处理器指令，以提供执行这样的指令所需的其余的微核。

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