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1. 发明授权

US4583193A Integrated circuit mechanism for coupling multiple programmable logic arrays to a common bus 失效
标题翻译：用于将多个可编程逻辑阵列耦合到公共总线的集成电路机制
公开(公告)号：US4583193A
公开(公告)日：1986-04-15
申请号：US350681
申请日：1982-02-22
申请人： Wayne R. Kraft , Moises Cases , William L. Stahl, Jr. , Nandor G. Thoma , Virgil D. Wyatt
发明人： Wayne R. Kraft , Moises Cases , William L. Stahl, Jr. , Nandor G. Thoma , Virgil D. Wyatt
IPC分类号： H01L21/822 , G06F9/22 , G06F9/26 , G06F9/28 , H01L21/82 , H01L27/04 , H03K19/173 , H03K19/177 , G06F13/38
CPC分类号： G06F9/28 , G06F9/223 , G06F9/267
摘要： An integrated circuit mechanism is provided for coupling the separate sets of output lines from a plurality of programmable logic arrays to the same set of bus lines of plural-line signal transfer bus. This coupling mechanism includes precharge circuitry for precharging each of the bus lines during a first time interval. This coupling mechanism also includes a separate strobe signal line for each programmable logic array and circuitry for activating one of the strobe signal lines during a second time interval for selecting a particular programmable logic array. This coupling mechanism further includes a separate output buffer for each programmable logic array. Each such output buffer includes a plurality of buffer stages for individually coupling the different ones of the programmable logic array output lines to their respective bus lines. The buffer stages for each programmable logic array are responsive to the strobe signal for its programmable logic array for discharging during the second time interval those bus lines for which its programmable logic array output lines are at a particular binary value.
摘要翻译：提供了一种集成电路机制，用于将分离的输出线组从多个可编程逻辑阵列耦合到多行信号传输总线的同一组总线。该耦合机构包括用于在第一时间间隔期间预充电每个总线的预充电电路。该耦合机构还包括用于每个可编程逻辑阵列的单独选通信号线和用于在用于选择特定可编程逻辑阵列的第二时间间隔期间激活选通信号线之一的电路。该耦合机构还包括用于每个可编程逻辑阵列的单独的输出缓冲器。每个这样的输出缓冲器包括用于将不同的可编程逻辑阵列输出线分别耦合到它们各自的总线的多个缓冲级。每个可编程逻辑阵列的缓冲级响应于其可编程逻辑阵列的选通信号，用于在第二时间间隔期间对其可编程逻辑阵列输出线处于特定二进制值的总线进行放电。

2. 发明授权

US4567561A Large scale integration data processor signal transfer mechanism 失效
标题翻译：大规模集成数据处理器信号传递机制
公开(公告)号：US4567561A
公开(公告)日：1986-01-28
申请号：US334185
申请日：1981-12-24
申请人： Virgil D. Wyatt , Wayne R. Kraft , Nandor G. Thoma
发明人： Virgil D. Wyatt , Wayne R. Kraft , Nandor G. Thoma
IPC分类号： G06F7/00 , G06F9/30 , G06F13/40 , G06F15/78 , G06F9/00
CPC分类号： G06F13/4077 , G06F15/7864 , Y02B60/1225 , Y02B60/1228 , Y02B60/1235
摘要： A digital data signal transfer mechanism is provided for use in large scale integration digital data processor circuitry formed on an integrated circuit chip. The signal transfer mechanism includes a plural-bit data bus formed on the integrated circuit chip for transferring plural-bit binary data signals between different locations on the chip. The signal transfer mechanism also includes plural-bit signal source circuitry and plural-bit signal destination circuitry formed on the integrated circuit chip and coupled to the plural-bit data bus for respectively supplying plural-bit data signals to and receiving plural-bit data signals from the bus. The signal transfer mechanism further includes processor control circuitry coupled to the signal source and signal destination circuitry for enabling the signal source circuitry to put a plural-bit data signal onto the data bus during a first processor control cycle and for enabling the signal destination circuitry to take in this plural-bit data signal from the bus during a second and different processor control cycle. The inherent capacitance of the plural-bit data bus serves to store the plural-bit data signal during the first and second and any intervening processor control cycles.
摘要翻译：提供数字数据信号传送机制，用于形成在集成电路芯片上的大规模集成数字数据处理器电路。信号传送机构包括形成在集成电路芯片上用于在芯片上的不同位置之间传送多位二进制数据信号的多位数据总线。信号传送机构还包括形成在集成电路芯片上并耦合到多位数据总线的多位信号源电路和多位信号目的地电路，用于分别向多位数据信号提供多位数据信号并接收多位数据信号从公共汽车。信号传送机构还包括耦合到信号源和信号目的地电路的处理器控制电路，用于使信号源电路在第一处理器控制周期期间将多位数据信号放入数据总线上，并使信号目的地电路能够在第二和不同的处理器控制周期期间从总线接收该多位数据信号。多位数据总线的固有电容用于在第一和第二和任何中间处理器控制周期期间存储多位数据信号。

3. 发明授权

US4156925A Overlapped and interleaved control store with address modifiers 失效
标题翻译：具有地址修改器的重叠和交织控制存储
公开(公告)号：US4156925A
公开(公告)日：1979-05-29
申请号：US681955
申请日：1976-04-30
申请人： William E. Tutt , Virgil D. Wyatt
发明人： William E. Tutt , Virgil D. Wyatt
IPC分类号： G06F9/22 , G06F9/26 , G06F9/28 , G06F12/06 , G06F15/16 , G06F15/177 , G06F13/00 , G06F9/10 , G06F9/16 , G06F9/20
CPC分类号： G06F9/262 , G06F9/261 , G06F9/28
摘要： This invention relates to controls for a control store made of plural modules which operate in an overlapped continuous manner, wherein the modules are cycled in a fixed sequence.This invention particularly relates to a novel next address generation and handling means for a control store using time interleaved modules.
摘要翻译：本发明涉及一种以重叠的连续方式工作的由多个模块组成的控制存储器的控制，其中模块以固定的顺序循环。

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