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1. 发明授权

US10141086B2 Cable for high speed data communications 有权
公开(公告)号：US10141086B2
公开(公告)日：2018-11-27
申请号：US12628245
申请日：2009-12-01
申请人： Moises Cases , Vinh B. Lu , Bhyrav M. Mutnury
发明人： Moises Cases , Vinh B. Lu , Bhyrav M. Mutnury
IPC分类号： H01B7/00 , H01B11/20 , H01B11/10 , H01P3/06
摘要： A cable for high speed data communications is provided. The cable includes a first inner conductor enclosed by a first dielectric layer and a second inner conductor enclosed by a second dielectric layer. The first inner conductor is substantially parallel to the second inner conductor and to a longitudinal axis. The cable includes a conductive shield wrapped around the first and second inner conductors, with an overlap of the conductive shield along and about the longitudinal axis. The overlap is aligned with a low current plane. The low current plane is substantially parallel to the first and second inner conductors, substantially equidistant from the first and second inner conductors, and substantially orthogonal to a plane including the first and second inner conductors.

2. 发明授权

US08830690B2 Minimizing plating stub reflections in a chip package using capacitance 有权
标题翻译：使用电容最小化芯片封装中的电镀短截线反射
公开(公告)号：US08830690B2
公开(公告)日：2014-09-09
申请号：US12237444
申请日：2008-09-25
申请人： Bhyrav M Mutnury , Moises Cases , Nanju Na , Tae Hong Kim
发明人： Bhyrav M Mutnury , Moises Cases , Nanju Na , Tae Hong Kim
IPC分类号： H05K1/18 , H05K1/02 , H05K1/16 , H05K3/24
CPC分类号： H01L21/4853 , C25D5/02 , H01L24/73 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2924/14 , H01L2924/15311 , H05K1/0231 , H05K1/162 , H05K3/242 , H05K2203/049 , H01L2924/00012 , H01L2924/00
摘要： Embodiments of the present invention are directed to shifting the resonant frequency in a high-frequency chip package away from an operational frequency by connecting a capacitance between an open-ended plating stub and ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A first outer layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A capacitor is used to capacitively couple the plating stub to a ground layer.
摘要翻译：本发明的实施例涉及通过连接开放式电镀短截线和接地之间的电容来将高频芯片封装中的谐振频率从工作频率移开。一个实施例提供了用于将芯片与印刷电路板接口的多层基板。第一外层提供了芯片安装位置。信号互连与芯片安装位置间隔开，并且信号迹线从芯片安装位置附近延伸到信号互连。安装在芯片安装位置的芯片可以通过引线键合连接到信号迹线。电镀短截线从信号互连延伸到衬底的周围。电容器用于将电镀端子电容耦合到接地层。

3. 发明授权

US08453081B2 Electrical design space exploration 失效
标题翻译：电气设计空间探索
公开(公告)号：US08453081B2
公开(公告)日：2013-05-28
申请号：US12784150
申请日：2010-05-20
申请人： Moises Cases , Jinwoo Choi , Bhyrav M. Mutnury , Caleb J. Wesley
发明人： Moises Cases , Jinwoo Choi , Bhyrav M. Mutnury , Caleb J. Wesley
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , G06F2217/08
摘要： A method for electrical design space exploration includes receiving a template for an electrical design. Design component parameters associated with at least one component in the electrical design are also received. Weighted factors are assigned to design complexity parameters of the electrical design. The parameters of the complexity can include at least one of following: whether the electrical design is known, a number of the design component parameters, a level of interaction among the design component parameters, a time constraint and a memory restriction of a simulation, and whether a statistical analysis or a worst case approach is used to analyze an output of the simulation. A simulation approach for design space exploration of the electrical design is selected based on the weighted factors for the parameters of the complexity of the electrical design. The simulation is performed based on the selected simulation approach.
摘要翻译：电气设计空间探索的方法包括接收电气设计的模板。还接收与电气设计中的至少一个组件相关联的设计组件参数。加权因子分配给电气设计的设计复杂性参数。复杂性的参数可以包括以下至少一个：电气设计是否已知，多个设计组件参数，设计组件参数之间的交互级别，时间约束和模拟的存储器限制，以及是否使用统计分析或最坏情况的方法来分析模拟的输出。基于电气设计复杂度参数的加权因子，选择电气设计空间探索的仿真方法。基于选择的模拟方法进行模拟。

4. 发明授权

US08402406B2 Controlling plating stub reflections in a chip package 失效
标题翻译：控制芯片封装中的电镀短截线反射
公开(公告)号：US08402406B2
公开(公告)日：2013-03-19
申请号：US12979745
申请日：2010-12-28
申请人： Moises Cases , Bhyrav M. Mutnury , Nanju Na , Terence Rodrigues
发明人： Moises Cases , Bhyrav M. Mutnury , Nanju Na , Terence Rodrigues
IPC分类号： G06F17/50 , G06F9/455 , H01L23/02 , H01L21/00 , H01R9/00
CPC分类号： G06F17/5068 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： Methods, apparatuses, and computer program products are disclosed for controlling plating stub reflections in a chip package. In one embodiment, a resonance optimizer determines performance characteristics of a bond wire that connects a chip to a substrate of a semiconductor chip mount. In this embodiment, the resonance optimizer selects, based on the performance characteristics of the bond wire, a line width for an open-ended plating stub that extends from a signal interconnect of the substrate to a periphery of the substrate, The resonance optimizer also generates a design of signal traces for the substrate, where the signal traces include the open-ended plating stub with the selected line width.
摘要翻译：公开了用于控制芯片封装中的电镀短截线反射的方法，装置和计算机程序产品。在一个实施例中，谐振优化器确定将芯片连接到半导体芯片基座的衬底的接合线的性能特性。在该实施例中，谐振优化器基于接合线的性能特性，选择从衬底的信号互连延伸到衬底的周边的开放式电镀短截线的线宽度。谐振优化器还产生用于衬底的信号迹线的设计，其中信号迹线包括具有所选线宽的开口电镀短截线。

5. 发明授权

US08319113B2 Printed circuit board with reduced dielectric loss 有权
标题翻译：具有降低介电损耗的印刷电路板
公开(公告)号：US08319113B2
公开(公告)日：2012-11-27
申请号：US12797244
申请日：2010-06-09
申请人： Moises Cases , Bradley D. Herrman , Bhyrav M. Mutnury , Nam H. Pham , Terence Rodrigues
发明人： Moises Cases , Bradley D. Herrman , Bhyrav M. Mutnury , Nam H. Pham , Terence Rodrigues
IPC分类号： H05K1/00 , H05K3/00
CPC分类号： H05K1/024 , H05K3/4602 , H05K3/4697 , Y10T29/49124 , Y10T29/49155
摘要： A printed circuit board (‘PCB’) with reduced dielectric loss, including conductive traces disposed upon layers of dielectric material, the layers of dielectric material including core layers and prepreg layers, one or more of the layers of dielectric material including pockets of air that reduce an overall relative dielectric constant of the PCB.
摘要翻译：一种具有降低的介质损耗的印刷电路板（PCB），包括设置在介电材料层上的导电迹线，所述介电材料层包括芯层和预浸料层，介电材料层中的一个或多个包括空气袋， PCB的总相对介电常数。

6. 发明申请

US20120167033A1 Controlling Plating Stub Reflections In A Chip Package 失效
标题翻译：控制芯片封装中的电镀短截线反射
公开(公告)号：US20120167033A1
公开(公告)日：2012-06-28
申请号：US12979745
申请日：2010-12-28
申请人： Moises Cases , Bhyrav M. Mutnury , Nanju Na , Terence Rodrigues
发明人： Moises Cases , Bhyrav M. Mutnury , Nanju Na , Terence Rodrigues
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： Methods, apparatuses, and computer program products are disclosed for controlling plating stub reflections in a chip package. Embodiments include determining, by a resonance optimizer, performance characteristics of a bond wire, the bond wire connecting a chip to a substrate of a semiconductor chip mount; based on the performance characteristics of the bond wire, selecting, by the resonance optimizer, a line width for an open-ended plating stub, the open-ended plating stub extending from a signal interconnect of the substrate to a periphery of the substrate; and generating, by the resonance optimizer, a design of signal traces for the substrate, the signal traces including the open-ended plating stub with the selected line width.
摘要翻译：公开了用于控制芯片封装中的电镀短截线反射的方法，装置和计算机程序产品。实施例包括通过谐振优化器确定接合线的性能特征，将芯片连接到半导体芯片基座的衬底的接合线; 基于所述接合线的性能特性，通过所述共振优化器选择所述开口电镀短截线的线宽，所述开口电镀短截线从所述基板的信号互连延伸到所述基板的周围; 并且通过所述谐振优化器产生用于所述衬底的信号迹线的设计，所述信号迹线包括具有所选线宽度的开放式电镀短截线。

7. 发明授权

US08106666B2 Testing an electrical component 有权
标题翻译：测试电气部件
公开(公告)号：US08106666B2
公开(公告)日：2012-01-31
申请号：US12402806
申请日：2009-03-12
申请人： Rubina F. Ahmed , Moises Cases , Bradley D. Herrman , Bhyrav M. Mutnury , Pravin Patel , Peter R. Seidel
发明人： Rubina F. Ahmed , Moises Cases , Bradley D. Herrman , Bhyrav M. Mutnury , Pravin Patel , Peter R. Seidel
IPC分类号： G01R31/02
CPC分类号： G01R31/2806 , G01R15/183
摘要： Testing an electrical component, the component including a printed circuit board (‘PCB’) with a number of traces, the traces organized in pairs with each trace of a pair carrying current in opposite directions and separated from one another by a substrate layer of the PCB, where testing of the electrical component includes: dynamically and iteratively until a present impedance for a pair of traces of the component is greater than a predetermined threshold impedance: increasing, by an impedance varying device at the behest of a testing device, magnetic field strength of a magnetic field applied to the pair of traces by the impedance varying device, including increasing the present impedance of the pair of traces; measuring, by the testing device, one or more operating parameters; and recording, by the testing device, the measurements of the operating parameters.
摘要翻译：测试电气部件，该部件包括具有多个迹线的印刷电路板（“PCB”），该迹线与成对的每个迹线成对地沿着相反的方向承载电流，并且彼此分离由基底层 PCB，其中电气部件的测试包括：动态地和迭代地，直到组件的一对迹线的当前阻抗大于预定阈值阻抗：通过测试装置的阻抗改变装置增加磁场通过阻抗变化装置施加到该对迹线的磁场的强度，包括增加该对迹线的当前阻抗; 由所述测试装置测量一个或多个操作参数; 并由测试装置记录操作参数的测量值。

8. 发明申请

US20110267906A1 Measuring SDRAM Control Signal Timing 有权
标题翻译：测量SDRAM控制信号时序
公开(公告)号：US20110267906A1
公开(公告)日：2011-11-03
申请号：US12768998
申请日：2010-04-28
申请人： Moises Cases , Vinh B. Lu , Bhyrav M. Mutnury , James J. Parsonese , Nam H. Pham
发明人： Moises Cases , Vinh B. Lu , Bhyrav M. Mutnury , James J. Parsonese , Nam H. Pham
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/56008 , G11C7/1072 , G11C29/023 , G11C29/028 , G11C29/56012 , G11C2029/5602 , G11C2029/5606
摘要： Measuring control signal timing for synchronous dynamic random access memory (‘SDRAM’), including combining into a trigger signal for an oscilloscope display control signals of an SDRAM under test, the control signals derived only from a single type of memory operations; and driving, continually during both READ and WRITE operations to and from the SDRAM under test, the oscilloscope display with a memory bus data signal (‘DQ’) and a memory bus clock signal (‘DQS’) from the SDRAM under test.
摘要翻译：测量同步动态随机存取存储器（“SDRAM”）的控制信号定时，包括组合成示波器的触发信号，显示被测SDRAM的控制信号，仅从单一类型存储器操作导出的控制信号; 并且在读取和写入操作的SDRAM期间不断地驱动，示波器显示器具有来自被测SDRAM的存储器总线数据信号（'DQ'）和存储器总线时钟信号（'DQS'）。

9. 发明申请

US20110061898A1 REDUCING CROSS-TALK IN HIGH SPEED CERAMIC PACKAGES USING SELECTIVELY-WIDENED MESH 审中-公开
标题翻译：使用选择性更宽的MESH降低高速陶瓷包装中的交叉点
公开(公告)号：US20110061898A1
公开(公告)日：2011-03-17
申请号：US12560133
申请日：2009-09-15
申请人： Bhyrav Mutnury , Jinwoo Choi , Moises Cases , Nanju Na
发明人： Bhyrav Mutnury , Jinwoo Choi , Moises Cases , Nanju Na
IPC分类号： H05K1/00 , G06F17/50 , H05K3/00
CPC分类号： H05K1/0224 , G06F17/5036 , G06F17/5081 , G06F2217/82 , H05K3/4629 , H05K2201/09681 , H05K2201/09727 , H05K2201/09972 , Y10T29/49155
摘要： One embodiment of the invention provides a multi-layered ceramic package. The ceramic package includes a signal layer having a plurality of signal lines and a mesh reference layer parallel to the signal layer. The mesh reference layer includes a plurality of intersecting reference lines of varying reference-line width in the plane of the mesh layer. The mesh reference lines may be widened in locations of probable signal cross-talk. Other embodiments of the invention include software for optimizing a ceramic package design by selectively widening mesh lines in regions of probable cross-talk, and systems for designing and manufacturing such a ceramic package.
摘要翻译：本发明的一个实施例提供一种多层陶瓷封装。陶瓷封装包括具有多个信号线的信号层和与信号层平行的网格参考层。网格参考层包括在网格层的平面中改变参考线宽度的多个相交参考线。网格参考线可能在可能的信号串扰的位置加宽。本发明的其它实施例包括通过在可能的串扰区域中选择性地加宽网格线来优化陶瓷封装设计的软件，以及用于设计和制造这种陶瓷封装的系统。

10. 发明授权

US07868651B1 Off-die termination of memory module signal lines 有权
标题翻译：内存模块信号线的裸片端接
公开(公告)号：US07868651B1
公开(公告)日：2011-01-11
申请号：US12632858
申请日：2009-12-08
申请人： Moises Cases , Bhyrav M. Mutnury , Nam H. Pham
发明人： Moises Cases , Bhyrav M. Mutnury , Nam H. Pham
IPC分类号： H03K17/16
CPC分类号： G06F13/4086
摘要： Off-die termination of memory module signal lines in a computer memory subsystem. The computer memory subsystem includes a memory controller and a DIMM socket installed on a PCB. The memory controller is electrically coupled to the DIMM socket via a memory module signal line. Off-die termination includes detecting, by a termination controller installed on the PCB, no presence of a DIMM in the DIMM socket and, responsive to the detection, activating, by the termination controller, an off-die termination component on the PCB to terminate the memory module signal line.
摘要翻译：计算机存储器子系统中存储器模块信号线的裸片端接。计算机存储器子系统包括安装在PCB上的存储器控制器和DIMM插槽。存储器控制器通过存储器模块信号线电耦合到DIMM插槽。离线端接包括通过安装在PCB上的终端控制器来检测DIMM插槽中是否存在DIMM，并且通过终端控制器响应于检测激活PCB上的脱模终端部件以终止内存模块信号线。

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