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1. 发明授权

US06754126B2 Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US06754126B2
公开(公告)日：2004-06-22
申请号：US10106597
申请日：2002-03-27
申请人： Shusaku Yamaguchi , Toshiya Uchida , Yoshimasa Yagishita , Yoshihide Bando , Masahiro Yada , Masaki Okuda , Hiroyuki Kobayashi , Kota Hara , Shinya Fujioka , Waichiro Fujieda
发明人： Shusaku Yamaguchi , Toshiya Uchida , Yoshimasa Yagishita , Yoshihide Bando , Masahiro Yada , Masaki Okuda , Hiroyuki Kobayashi , Kota Hara , Shinya Fujioka , Waichiro Fujieda
IPC分类号： G11C700
CPC分类号： G11C7/1006 , G11C8/12 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/40618 , G11C11/4087 , G11C2211/4061 , G11C2211/4062
摘要： A plurality of first memory blocks and a second memory block for reproducing data of the first memory blocks are formed. When a read command and a refresh command conflict with each other, a read control circuit accesses the first memory block according to the refresh command and reproduces read data by using the second memory block. When a write command and the refresh command conflict with each other, a write control circuit operates the memory block according to an order of command reception. Therefore, it is possible to perform refresh operation without being recognized by users. Namely, a user-friendly semiconductor memory can be provided.
摘要翻译：形成多个第一存储块和用于再现第一存储块的数据的第二存储块。当读命令和刷新命令彼此冲突时，读控制电路根据刷新命令访问第一存储块，并通过使用第二存储块再现读数据。当写命令和刷新命令彼此冲突时，写控制电路根据命令接收的顺序操作存储块。因此，可以在不被用户识别的情况下进行刷新操作。即，可以提供用户友好的半导体存储器。

2. 发明授权

US06529439B2 Semiconductor memory device 有权
公开(公告)号：US06529439B2
公开(公告)日：2003-03-04
申请号：US09789514
申请日：2001-02-22
申请人： Toshiya Uchida , Kota Hara , Shinya Fujioka
发明人： Toshiya Uchida , Kota Hara , Shinya Fujioka
IPC分类号： G11C800
CPC分类号： G11C8/08 , G11C5/06
摘要： A semiconductor memory device includes isolation circuits disconnecting cell arrays from sense amplifiers, and isolation signal generating circuits generating isolation signals that control the isolation circuits. The isolation signal generating circuits are hierarchically divided into main isolation signal generating circuits and sub isolation signal generating circuits. The sub isolation signal generating circuits generate sub isolation signals having a first potential on a high-potential side. The main isolation signal generating circuits generate main isolation signals having a second potential on the high-potential side, the second potential being lower than the first potential.

3. 发明授权

US06614712B2 Semiconductor memory device 有权
公开(公告)号：US06614712B2
公开(公告)日：2003-09-02
申请号：US10329669
申请日：2002-12-27
申请人： Toshiya Uchida , Kota Hara , Shinya Fujioka
发明人： Toshiya Uchida , Kota Hara , Shinya Fujioka
IPC分类号： G11C800
CPC分类号： G11C8/08 , G11C5/06
摘要： A semiconductor memory device includes isolation circuits disconnecting cell arrays from sense amplifiers, and isolation signal generating circuits generating isolation signals that control the isolation circuits. The isolation signal generating circuits are hierarchically divided into main isolation signal generating circuits and sub isolation signal generating circuits. The sub isolation signal generating circuits generate sub isolation signals having a first potential on a high-potential side. The main isolation signal generating circuits generate main isolation signals having a second potential on the high-potential side, the second potential being lower than the first potential.

4. 发明授权

US06731553B2 Memory circuit having compressed testing function 有权
标题翻译：存储电路具有压缩测试功能
公开(公告)号：US06731553B2
公开(公告)日：2004-05-04
申请号：US10270196
申请日：2002-10-15
申请人： Shinya Fujioka , Waichiro Fujieda , Kota Hara
发明人： Shinya Fujioka , Waichiro Fujieda , Kota Hara
IPC分类号： G11C700
CPC分类号： G11C29/40
摘要： A multi-bit output configuration memory circuit comprises: a memory core having a normal cell array and a redundant cell array, which have a plurality of memory cells; N output terminals which respectively output N-bit output read out from the memory core; an output circuit provided between the output terminals and the memory core, which detects whether each L-bit output of the N-bit output (N=L×M) read out from said memory core matches or not and outputs a compressed output which becomes the output data in the event of a match while becomes a third state in the event of a non-match, to a first output terminal of the N output terminals. Responding to each of a plurality of test commands or the test control signals of the external terminals, the compressed output of the M groups of L-bit output is outputted in time shared.
摘要翻译：多比特输出配置存储器电路包括：具有正常单元阵列的存储器核心和具有多个存储单元的冗余单元阵列; N个输出端子，分别输出从存储器芯读出的N位输出; 输出电路，设置在输出端子和存储器核心之间，其检测从所述存储器芯片读出的N位输出（N = L×M）的每个L位输出是否匹配，并输出成为输出的压缩输出在匹配的情况下的数据在不匹配的情况下变为第三状态时，输出到N个输出端的第一输出端。响应多个测试命令或外部终端的测试控制信号中的每一个，M个组的L位输出的压缩输出以时间共享的形式被输出。

5. 发明授权

US06621750B2 Semiconductor memory 有权
公开(公告)号：US06621750B2
公开(公告)日：2003-09-16
申请号：US10155029
申请日：2002-05-28
申请人： Yoshiaki Okuyama , Shinya Fujioka , Kota Hara , Katsuhiro Mori
发明人： Yoshiaki Okuyama , Shinya Fujioka , Kota Hara , Katsuhiro Mori
IPC分类号： G11C700
CPC分类号： G11C29/808 , G11C29/812 , G11C29/848
摘要： A redundancy memory circuit stores a defect address indicating a defective memory cell row. A redundancy control circuit disables the defective memory cell row corresponding to the defect address stored in the redundancy memory circuit and enables a redundancy memory cell row in the memory block containing the defective memory cell row. Moreover, in the other memory blocks, the redundancy control circuit disables memory cell rows corresponding to the defective memory cell row and enables redundancy memory cell rows instead of these memory cell rows. Consequently, not only the memory block having the defective memory cell row but one of the memory cell rows in the other memory blocks is always also relieved. Thus, the redundancy memory circuit can be shared among all the memory blocks with a reduction in the number of redundancy memory circuits. As a result, the semiconductor memory can be reduced in chip size.

6. 发明授权

US07032142B2 Memory circuit having parity cell array 失效
公开(公告)号：US07032142B2
公开(公告)日：2006-04-18
申请号：US10271533
申请日：2002-10-17
申请人： Shinya Fujioka , Waichiro Fujieda , Kota Hara , Toru Koga , Katsuhiro Mori
发明人： Shinya Fujioka , Waichiro Fujieda , Kota Hara , Toru Koga , Katsuhiro Mori
IPC分类号： G11C29/00 , G11C7/00 , G06F11/00
CPC分类号： G11C29/42 , G06F11/106 , G11C11/401 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C2211/4062
摘要： A memory circuit has: a real cell array; a parity generating circuit for generating a parity bit from data of the real cell array; a parity cell array; a refresh control circuit, which sequentially refreshes the real cell array, and when an internal refresh request and a read request coincide, prioritizes a refresh operation; a data recovery section, which, in accordance with the parity bit read out from the parity cell array, recovers data read out from the real cell array; and an output circuit for outputting data from the real cell array. Further, the memory circuit has a test control circuit, which, at a first test mode, prohibits a refresh operation for the real cell array to output data read out from the real cell array, and, at a second test mode, controls the output circuit so as to output data read out from the parity cell array.

7. 发明授权

US06185149B2 Semiconductor integrated circuit memory 有权
标题翻译：半导体集成电路存储器
公开(公告)号：US06185149B2
公开(公告)日：2001-02-06
申请号：US09340147
申请日：1999-06-28
申请人： Shinya Fujioka , Masao Taguchi , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Yasurou Matsuzaki , Toshiya Uchida
发明人： Shinya Fujioka , Masao Taguchi , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Yasurou Matsuzaki , Toshiya Uchida
IPC分类号： G11C800
CPC分类号： G11C7/1018 , G11C7/1072
摘要： A semiconductor memory includes memory cell blocks, a burst-length information generating circuit which generates burst-length information based on a burst length, and a block enable circuit which receives the burst-length information. The block enable circuit selectively enables one of the memory cell blocks when the burst length is equal to or shorter than a predetermined burst length and selectively enables a plurality of memory cell blocks based on the burst length when the burst length is longer than the predetermined burst length. Data are read from the above-mentioned one or plurality of memory cell blocks.
摘要翻译：半导体存储器包括存储单元块，基于突发长度生成突发长度信息的突发长度信息产生电路，以及接收脉冲串长度信息的块使能电路。当突发长度等于或小于预定突发长度时，块使能电路选择性地启用存储单元块中的一个，并且当突发长度长于预定突发时，基于脉冲串长度选择性地启用多个存储单元块长度。从上述一个或多个存储单元块读取数据。

8. 发明授权

US06353561B1 Semiconductor integrated circuit and method for controlling the same 有权
标题翻译：半导体集成电路及其控制方法
公开(公告)号：US06353561B1
公开(公告)日：2002-03-05
申请号：US09397845
申请日：1999-09-17
申请人： Akihiro Funyu , Shinya Fujioka , Yasuharu Sato , Toshiya Uchida
发明人： Akihiro Funyu , Shinya Fujioka , Yasuharu Sato , Toshiya Uchida
IPC分类号： G11C700
CPC分类号： G11C7/109 , G11C7/1006 , G11C7/1072 , G11C7/1078 , G11C11/4093
摘要： A semiconductor memory device, such as a synchronous DRAM, receives external commands and an external clock signal via input buffers. The device generates internal clock signals having a slower frequency than the external clock signal and uses the internal clock signals to acquire the external command. This allows more than one external command to be acquired for each cycle of the external clock. The acquired external commands are provided to command decoders for decoding. A mask circuit is connected to the decoder circuits and inhibits the decoding circuits, except for a first one of the decoding circuits, from decoding the external commands for a predetermined time period, when the first decoder circuit is decoding the external commands.
摘要翻译：诸如同步DRAM的半导体存储器件经由输入缓冲器接收外部命令和外部时钟信号。该器件产生的频率低于外部时钟信号的内部时钟信号，并使用内部时钟信号来获取外部命令。这允许在外部时钟的每个周期获取多于一个外部命令。获取的外部命令被提供给命令解码器进行解码。当第一解码器电路解码外部命令时，掩码电路连接到解码器电路，并且禁止解码电路以外的第一解码电路在预定时间段内解码外部命令。

9. 发明授权

US07903487B2 Semiconductor memory device, and method of controlling the same 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US07903487B2
公开(公告)日：2011-03-08
申请号：US12201922
申请日：2008-08-29
申请人： Shinya Fujioka , Tomohiro Kawakubo , Koichi Nishimura , Kotoku Sato
发明人： Shinya Fujioka , Tomohiro Kawakubo , Koichi Nishimura , Kotoku Sato
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3268 , G06F1/3275 , G11C5/14 , G11C5/145 , G11C5/147 , G11C11/406 , G11C11/40615 , G11C14/00 , G11C2207/2227 , G11C2211/4067 , H02M3/07 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.
摘要翻译：内部电压发生器激活时，产生内部电压供给内部电路。操作内部电压发生器消耗预定量的功率。响应来自外部的控制信号，入口电路使内部电压发生器失活。内部电压发生器未激活时，不产生内部电压，从而降低功耗。因此，通过来自外部的控制信号，芯片可以容易地进入低功耗模式。内部电压发生器的例子是用于产生与存储器单元连接的字线的升压电压的升压器，用于产生衬底电压的衬底电压发生器或用于产生要连接的位线的预充电电压的预充电电压发生器记忆细胞。

10. 发明授权

US07869296B2 Semiconductor memory device, and method of controlling the same 有权
公开(公告)号：US07869296B2
公开(公告)日：2011-01-11
申请号：US11515852
申请日：2006-09-06
申请人： Shinya Fujioka , Tomohiro Kawakubo , Koichi Nishimura , Kotoku Sato
发明人： Shinya Fujioka , Tomohiro Kawakubo , Koichi Nishimura , Kotoku Sato
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3268 , G06F1/3275 , G11C5/14 , G11C5/145 , G11C5/147 , G11C11/406 , G11C11/40615 , G11C14/00 , G11C2207/2227 , G11C2211/4067 , H02M3/07 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

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