专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07791131B2 Semiconductor device and a method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07791131B2
公开(公告)日：2010-09-07
申请号：US11645577
申请日：2006-12-27
申请人： Tomoyuki Miyake , Masatoshi Morikawa , Yutaka Hoshino , Makoto Hatori
发明人： Tomoyuki Miyake , Masatoshi Morikawa , Yutaka Hoshino , Makoto Hatori
IPC分类号： H01L29/76 , H01L29/94 , H01L31/62 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66659 , H01L21/823425 , H01L23/3677 , H01L23/66 , H01L24/45 , H01L24/48 , H01L27/0629 , H01L27/088 , H01L29/0847 , H01L29/0878 , H01L29/4175 , H01L29/41758 , H01L29/7835 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2924/01079 , H01L2924/1305 , H01L2924/13091 , H01L2924/19041 , H01L2924/19105 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： To reduce the size and improve the power added efficiency of an RF power module having an amplifier element composed of a silicon power MOSFET, the on resistance and feedback capacitance, which were conventionally in a trade-off relationship, are reduced simultaneously by forming the structure of an offset drain region existing between a gate electrode and an n+ type drain region of the power MOSFET into a double offset one. More specifically, this is accomplished by adjusting the impurity concentration of an n− type offset drain region, which is closest to the gate electrode, to be relatively low and adjusting the impurity concentration of an n type offset drain region, which is distant from the gate electrode, to be relatively high.
摘要翻译：为了减小尺寸并提高具有由硅功率MOSFET组成的放大器元件的RF功率模块的功率附加效率，传统上处于折衷关系的导通电阻和反馈电容通过形成结构存在于功率MOSFET的栅极电极和n +型漏极区域之间的偏移漏极区域，成为双偏移漏极区域。更具体地说，这是通过将最接近栅电极的n型偏移漏极区域的杂质浓度调整为相对较低而调整n型偏移漏极区域的杂质浓度来实现的，该杂质浓度远离栅电极，要比较高。

2. 发明授权

US07491992B2 Image sensor cells 失效
标题翻译：图像传感器单元
公开(公告)号：US07491992B2
公开(公告)日：2009-02-17
申请号：US11619024
申请日：2007-01-02
申请人： James W. Adkisson , John J. Ellis-Monaghan , Mark D. Jaffe , Richard J. Rassel , Jeffrey P. Gambino
发明人： James W. Adkisson , John J. Ellis-Monaghan , Mark D. Jaffe , Richard J. Rassel , Jeffrey P. Gambino
IPC分类号： H01L31/62 , H01L31/113
CPC分类号： H01L27/14609 , H01L27/1463 , H01L27/14641 , H01L27/14643 , H01L31/035281
摘要： A structure (and method for forming the same) for an image sensor cell. The method includes providing a semiconductor substrate. Then, a charge collection well is formed in the semiconductor substrate, the charge collection well comprising dopants of a first doping polarity. Next, a surface pinning layer is formed in the charge collection well, the surface pinning layer comprising dopants of a second doping polarity opposite to the first doping polarity. Then, an electrically conductive push electrode is formed in direct physical contact with the surface pinning layer but not in direct physical contact with the charge collection well. Then, a transfer transistor is formed on the semiconductor substrate. The transfer transistor includes first and second source/drain regions and a channel region. The first and second source/drain regions comprise dopants of the first doping polarity. The first source/drain region is in direct physical contact with the charge collection well.
摘要翻译：用于图像传感器单元的结构（及其形成方法）。该方法包括提供半导体衬底。然后，在半导体衬底中形成电荷收集阱，电荷收集阱包含第一掺杂极性的掺杂剂。接下来，在电荷收集阱中形成表面钉扎层，表面钉扎层包括与第一掺杂极性相反的第二掺杂极性的掺杂剂。然后，导电的推动电极形成为与表面钉扎层直接物理接触，但不与电荷收集阱直接物理接触。然后，在半导体衬底上形成传输晶体管。传输晶体管包括第一和第二源极/漏极区域和沟道区域。第一和第二源/漏区包括第一掺杂极性的掺杂剂。第一源极/漏极区域与电荷收集阱直接物理接触。

3. 发明授权

US07446357B2 Split trunk pixel layout 有权
标题翻译：拆分中继线像素布局
公开(公告)号：US07446357B2
公开(公告)日：2008-11-04
申请号：US11126307
申请日：2005-05-11
申请人： Jeffrey A. McKee
发明人： Jeffrey A. McKee
IPC分类号： H01L31/62 , H01L31/113
CPC分类号： H01L27/146
摘要： A pixel array architecture having multiple pixel cells arranged in a split trunk pixel layout and sharing common pixel cell components. The array architecture increases the fill factor, and in turn, the quantum efficiency of the pixel cells. The common pixel cell components may be shared by a number of pixels in the array, and may include several components that are associated with the storage and readout of a signal from the pixel cells.
摘要翻译：一种像素阵列架构，其具有以分裂干线像素布局布置并且共享公共像素单元组件的多个像素单元。阵列架构增加了填充因子，反过来增加了像素单元的量子效率。公共像素单元分量可以由阵列中的多个像素共享，并且可以包括与来自像素单元的信号的存储和读出相关联的若干组件。

4. 发明授权

US07244638B2 Semiconductor memory device and method of production 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07244638B2
公开(公告)日：2007-07-17
申请号：US11241820
申请日：2005-09-30
申请人： Dirk Caspary , Stefano Parascandola
发明人： Dirk Caspary , Stefano Parascandola
IPC分类号： H01L21/82 , H01L31/62
CPC分类号： H01L27/10 , H01L27/105 , H01L27/11568 , H01L2924/0002 , H01L2924/00
摘要： Final sections of the word lines are arranged in a staggered fashion to fan out and have larger lateral extensions than the word lines. Interspaces are filled with a dielectric material, and a mask is applied that partially covers the final sections and leaves contact areas in regions adjacent to the final sections and to the interspaces open. This mask is used to remove the dielectric material between the word line stacks. A second word line layer is applied and planarized to form second word lines between the first word lines, which have contact areas arranged in a staggered fashion to fan out like the final sections of the first word lines.
摘要翻译：字线的最后部分以交错的方式布置成扇形，并且具有比字线更大的横向延伸。间隙填充有电介质材料，并且施加部分覆盖最终部分并且在与最终部分相邻的区域中留下接触区域并且打开间隙的掩模。该掩模用于去除字线堆叠之间的介电材料。第二字线层被施加和平坦化以在第一字线之间形成第二字线，第一字线具有以交错方式布置的接触区域，以与第一字线的最后部分一样扇出。

5. 发明授权

US07157760B2 Magnetic memory device and method of manufacturing magnetic memory device 有权
标题翻译：磁存储器件及其制造方法
公开(公告)号：US07157760B2
公开(公告)日：2007-01-02
申请号：US10950399
申请日：2004-09-28
申请人： Akifumi Kamijima
发明人： Akifumi Kamijima
IPC分类号： H01L29/76 , H01L29/94 , H01L31/62 , H01L31/113 , H01L31/119
CPC分类号： G11C11/16 , H01L27/224
摘要： The present invention provides a magnetic memory device capable of stably writing information by efficiently using a magnetic field generated by current flowing in a conductor, which can be manufactured more easily, and a method of manufacturing the magnetic memory device. The method includes: a stacked body forming step of forming a pair of stacked bodies S20a and S20b on a substrate 31; a lower yoke forming step of forming a lower yoke 4B so as to cover at least the pair of stacked bodies S20a and S20b; and a write line forming step of simultaneously forming a pair of first parts 6F and write bit lines 5a and 5b so as to be disposed adjacent to each other in a first level L1 via an insulating film 7A as a first insulating film on the lower yoke 4B. Thus, the manufacturing process can be more simplified.
摘要翻译：本发明提供一种能够通过有效地利用可以制造得更容易制造的导体中流过的电流而产生的磁场来稳定地写信息的磁存储装置，以及制造该磁存储装置的方法。该方法包括：在基板31上形成一对堆叠体S20a和S2b的层叠体形成步骤; 下轭形成步骤，形成下轭铁B以至少覆盖所述一对堆叠体S20a和S220b; 以及写入线形成步骤，同时形成一对第一部分6F和写位线5a和5b，以便经由作为第一绝缘体的绝缘膜7A在第一电平L 1中彼此相邻设置因此，可以更加简化制造工艺。

6. 发明授权

US07129542B2 High voltage semiconductor device having high breakdown voltage and method of fabricating the same 有权
公开(公告)号：US07129542B2
公开(公告)日：2006-10-31
申请号：US10714607
申请日：2003-11-18
申请人： Chan-ho Park
发明人： Chan-ho Park
IPC分类号： H01L31/62 , H01L31/119
CPC分类号： H01L29/66295 , H01L29/0661 , H01L29/732
摘要： A high voltage semiconductor device, including: a high concentration collector area of a first conductive type; a low concentration collector area of a first conductive type formed on the high concentration collector area; a base area of a second conductive type formed on the low concentration collector area and having a trench perforating the low concentration collector area in a vertical direction at the edge of the trench; a high concentration emitter area of a first conductive type formed on a predetermined upper surface of the base area; and an emitter electrode, a base electrode, and a collector electrode isolated from one another and connected to the emitter area, the base area, and the collector area, respectively. High breakdown voltage can be obtained with a narrow junction termination area due to the trench.

7. 发明授权

US07115924B1 Pixel with asymmetric transfer gate channel doping 有权
标题翻译：具有不对称传输栅极通道掺杂的像素
公开(公告)号：US07115924B1
公开(公告)日：2006-10-03
申请号：US11144304
申请日：2005-06-03
申请人： Fredrick P. LaMaster , John H. Stanback , Chintamani P. Palsule , Thomas E. Dungan
发明人： Fredrick P. LaMaster , John H. Stanback , Chintamani P. Palsule , Thomas E. Dungan
IPC分类号： H01L31/62 , H01L21/00
CPC分类号： H01L27/14643 , H01L27/14601 , H01L29/66659 , H01L31/035281
摘要： A pixel including a substrate of a first conductivity type, a photodetector of a second conductivity type that is opposite the first conductivity type and configured to convert incident light to a charge, a floating diffusion of the second conductivity, and a transfer region between the photodetector and floating diffusion. A gate is formed above the transfer region and partially overlaps the photodetector and is configured to transfer charge from the photodetector to the floating diffusion. A pinning layer of the first conductivity type extends at least across the photodetector from the gate. A channel region of the first conductivity type extends generally from a midpoint of the gate at least across the photodiode and is formed by an implant of a dopant of the first conductivity and having a concentration such that a dopant concentration of the transfer region is greater proximate to the photodetector than proximate to the floating diffusion.
摘要翻译：包括第一导电类型的衬底的像素，与第一导电类型相反并被配置为将入射光转换成电荷的第二导电类型的光电检测器，第二导电率的浮动扩散以及光电检测器和浮动扩散。栅极形成在传输区域的上方，并且部分地与光电检测器重叠，并且被配置为将电荷从光电检测器转移到浮动扩散。第一导电类型的钉扎层至少跨过光电检测器从栅极延伸。第一导电类型的沟道区域至少跨越光电二极管从栅极的中点大致延伸并且由第一导电性的掺杂剂的注入形成，并且具有使得转移区域的掺杂剂浓度更大的浓度到光电探测器，而不是靠近浮动扩散。

8. 发明授权

US06891238B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06891238B2
公开(公告)日：2005-05-10
申请号：US10109893
申请日：2002-04-01
申请人： Yuichiro Mitani , Hideki Satake
发明人： Yuichiro Mitani , Hideki Satake
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/30 , H01L21/318 , H01L27/115 , H01L29/51 , H01L29/78 , H01L29/788 , H01L29/792 , H01L29/76 , H01L29/94 , H01L31/113 , H01L31/119 , H01L31/62
CPC分类号： H01L21/28185 , H01L21/28176 , H01L21/28202 , H01L21/28211 , H01L21/3003 , H01L29/518
摘要： A semiconductor device including a silicon substrate, a gate insulator film formed on the silicon substrate and including silicon, deuterium, and at least one of oxygen and nitrogen, and a gate electrode formed on the gate insulator film wherein a deuterium concentration in a vicinity of an interface of the gate insulator film with the gate electrode is at least 1×107 cm−3, and a deuterium concentration in a vicinity of an interface of the gate insulator film with the silicon substrate is higher than the deuterium concentration in the vicinity of the interface of the gate insulation film with the gate electrode.
摘要翻译：一种半导体器件，包括硅衬底，形成在硅衬底上的包括硅，氘和至少一个氧和氮的栅极绝缘膜，以及形成在栅极绝缘膜上的栅电极，其中氘浓度在栅极绝缘体膜与栅电极的界面为至少1×10 -7 cm -3，并且在栅极绝缘体膜的界面附近的氘浓度与硅基板比栅电极的栅极绝缘膜的界面附近的氘浓度高。

9. 发明授权

US06849906B2 Standard-cell type semiconductor integrated circuit device with a mixed arrangement of standard cells differing in height 失效
标题翻译：具有高度不同的标准电池的混合布置的标准电池型半导体集成电路器件
公开(公告)号：US06849906B2
公开(公告)日：2005-02-01
申请号：US10365415
申请日：2003-02-12
申请人： Muneaki Maeno , Toshiki Morimoto
发明人： Muneaki Maeno , Toshiki Morimoto
IPC分类号： H01L21/822 , H01L21/82 , H01L27/04 , H01L27/06 , H01L27/118 , H01L29/76 , H01L29/94 , H01L31/113 , H01L31/119 , H01L31/62
CPC分类号： H01L27/11807
摘要： A first cell block in which a plurality of standard cells with a large cell height are arranged and a second cell block in which a plurality of standard cells with a small cell height are arranged. In the second cell block, transistors are formed whose shape and characteristics are practically the same as those of the transistors provided in the standard cells with the large cell height arranged in the first cell block.
摘要翻译：布置有多个具有大单元高度的标准单元的第一单元块和布置有小单元高度的多个标准单元的第二单元块。在第二单元块中，形成晶体管，其晶体管的形状和特性与设置在第一单元块中的具有大单元高度的标准单元中提供的晶体管的形状和特性实际上相同。

10. 发明授权

US5563435A Insulated gate type semiconductor device having built-in protection circuit 失效
标题翻译：具有内置保护电路的绝缘栅型半导体器件
公开(公告)号：US5563435A
公开(公告)日：1996-10-08
申请号：US405835
申请日：1995-03-17
申请人： Yasuhiko Kohno , Yoshitaka Sugawara
发明人： Yasuhiko Kohno , Yoshitaka Sugawara
IPC分类号： H01L29/78 , H01L27/02 , H01L27/04 , H01L27/06 , H01L27/088 , H01L29/10 , H01L29/739 , H01L29/749 , H02M7/537 , H01L29/76 , H01L29/94 , H01L31/113 , H01L31/62
CPC分类号： H01L29/1095 , H01L27/0248 , H01L27/0251 , H01L29/7395
摘要： A semiconductor substrate is partitioned into a main IGBT region and a protection circuit region by a p-type well portion which is formed therebetween in contact with an emitter electrode and which acts as a cut-off region. Both a detection IGBT and protection circuit elements are formed within the protection circuit region. Since excessive carriers flowing from the main IGBT into the protection circuit region can efficiently be extracted through the p-type well portion, a highly reliable and high precision protection circuit built-in insulated gate semiconductor device is realized that can precisely detect any overcurrent, and operate without causing malfunction in the protection circuit and time delay.
摘要翻译：半导体基板被形成在与发射极电极接触并作为截止区域的p型阱部分的主IGBT区域和保护电路区域中。检测IGBT和保护电路元件都在保护电路区域内形成。由于从主IGBT流入保护电路区域的过量载流子能够通过p型阱部分有效地提取，因此实现了可靠性高的精密保护电路，内置绝缘栅极半导体器件，能够精确地检测任何过电流，操作而不会在保护电路中造成故障并延时。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式