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1. 发明授权

US07176089B2 Vertical dual gate field effect transistor 失效
标题翻译：垂直双栅场效应晶体管
公开(公告)号：US07176089B2
公开(公告)日：2007-02-13
申请号：US10853177
申请日：2004-05-26
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , James M. Leas , William H-L Ma , Paul A. Rabidoux
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , James M. Leas , William H-L Ma , Paul A. Rabidoux
IPC分类号： H01L21/336
CPC分类号： H01L29/78642 , H01L21/2255 , H01L21/76897 , H01L21/823487 , H01L27/088 , H01L29/66666 , H01L29/7827 , H01L29/7831
摘要： A method of manufacturing provides a vertical transistor particularly suitable for high density integration and which includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.
摘要翻译：一种制造方法提供特别适用于高密度积分的垂直晶体管，其包括通过在沟槽中蚀刻或外延生长而形成的半导体柱的相对侧上的潜在独立栅极结构。栅极结构被绝缘材料包围，绝缘材料可选择性地蚀刻到围绕晶体管的隔离材料。通过选择性地蚀刻对绝缘材料有选择性的隔离材料，对柱的下端（例如，晶体管漏极）进行接触。柱的上端由盖和可选择性蚀刻材料的侧壁覆盖，使得栅极和源极连接开口也可以通过具有良好配准公差的选择性蚀刻制成。在平行于芯片表面的方向上的柱的尺寸由隔离区域和选择性蚀刻之间的距离限定，并且柱的高度由牺牲层的厚度限定。

2. 发明授权

US06815737B2 Method for selective trimming of gate structures and apparatus formed thereby 失效
公开(公告)号：US06815737B2
公开(公告)日：2004-11-09
申请号：US10799819
申请日：2004-03-12
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
IPC分类号： H01L2710
CPC分类号： H01L21/76897 , H01L21/76888 , H01L21/76895
摘要： A method for forming a trimmed gate in a transistor comprises the steps of forming a polysilicon gate conductor on a semiconductor substrate and trimming the polysilicon portion by a film growth method chosen from among selective surface oxidation and selective surface nitridation. The trimming step may selectively compensate n-channel and p-channel devices. Also, the trimming film may optionally be removed by a method chosen from among anisotropic and isotropic etching. Further, gate conductor spacers may be formed by anisotropic etching of the grown film. The resulting transistor may comprise a trimmed polysilicon portion of a gate conductor, wherein the trimming occurred by a film growth method chosen from among selective surface oxidation and selective surface nitridation.

3. 发明授权

US06277543B1 Method for forming features using frequency doubling hybrid resist and device formed thereby 失效
标题翻译：使用倍频混合抗蚀剂形成特征的方法和由此形成的器件
公开(公告)号：US06277543B1
公开(公告)日：2001-08-21
申请号：US09369412
申请日：1999-08-05
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
IPC分类号： G03C500
CPC分类号： G03F7/70466 , G03F7/038 , G03F7/2022 , H01L21/0274
摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art by providing a method to form unlinked features using hybrid resist. The method uses a trim process in order to trim the linking features from the “loops” formed by the hybrid resist. This allows the method to form a plurality of unlinked features rather than the loops. In order to trim the ends, a relatively larger trim area is formed adjacent the narrow feature line, either by a second exposure step or by utilizing a grey scale reticle. The broader or wider open area allows features to be formed in the narrow feature lines and being trimmed from the relatively large areas, thereby resulting in district features rather than loops.
摘要翻译：本发明的优选实施例通过提供使用混合抗蚀剂形成不连接特征的方法来克服现有技术的局限性。该方法使用修剪工艺来修剪由混合抗蚀剂形成的“环”的连接特征。这允许该方法形成多个未链接的特征而不是循环。为了修剪端部，通过第二曝光步骤或通过利用灰度光罩，形成与窄特征线相邻的相对较大的修整区域。更宽或更宽的开放区域允许在窄特征线中形成特征并且从相对较大的区域修剪特征，从而导致区域特征而不是环。

4. 发明授权

US6114725A Structure for folded architecture pillar memory cell 失效
标题翻译：折叠式立柱式记忆体的新型结构
公开(公告)号：US6114725A
公开(公告)日：2000-09-05
申请号：US93928
申请日：1998-06-09
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Howard L. Kalter , Jack A. Mandelman , Paul A. Rabidoux , Jeffrey J. Welser
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Howard L. Kalter , Jack A. Mandelman , Paul A. Rabidoux , Jeffrey J. Welser
IPC分类号： H01L21/8242 , H01L21/8247 , H01L27/108 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792 , H01L29/76 , H01L29/94 , H01L31/113 , H01L31/119 , H01L31/62
CPC分类号： H01L27/11556 , H01L27/10808 , H01L27/10823 , H01L27/10841 , H01L27/10897 , H01L27/115
摘要： A densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has rows of wordlines and columns of bitlines. The array has vertical pillars, each having two wordlines, one active and the other passing for each cell. Two wordlines are formed per pillar on opposite pillar sidewalls which are along the row direction. The threshold voltage of the pillar device is raised on the side of the pillar touching the passing wordline, thereby permanently shutting off the pillar device during the cell operation and isolating the pillar from the voltage variations on the passing wordline. The isolated wordlines allow individual cells to be addressed and written via direct tunneling, in both volatile and non-volatile memory cell configurations. For Gbit DRAM application, stack or trench capacitors may be formed on the pillars, or in trenches surrounding the pillars, respectively.
摘要翻译：公开了一种具有支柱的紧密堆叠的垂直半导体器件阵列及其制造方法。该阵列具有字线和位线列。阵列具有垂直柱，每个具有两个字线，一个有效，另一个通过每个单元格。在沿着行方向的相对的支柱侧壁上的每个柱形成两个字线。支柱装置的阈值电压在柱体侧面升高，接触通过字线，从而在电池工作期间永久地关闭支柱装置，并将支柱与通过字线上的电压变化隔离。孤立的字线允许在易失性和非易失性存储单元配置中通过直接隧道寻址和写入各个单元。对于Gbit DRAM应用，可以在支柱上或在柱子周围的沟槽中分别形成堆叠或沟槽电容器。

5. 发明授权

US6100172A Method for forming a horizontal surface spacer and devices formed thereby 失效
标题翻译：用于形成水平表面间隔物的方法和由此形成的装置
公开(公告)号：US6100172A
公开(公告)日：2000-08-08
申请号：US182173
申请日：1998-10-29
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
IPC分类号： H01L21/033 , H01L21/308 , H01L21/336 , H01L21/768 , H01L21/822 , H01L29/78 , H01L21/22 , H01L21/425 , H01L21/8234
CPC分类号： H01L29/66613 , H01L21/0337 , H01L21/3086 , H01L21/76895 , H01L21/822 , H01L29/7835
摘要： The present invention provides a method for forming self-aligned spacers on the horizontal surfaces while removing spacer material from the vertical surfaces. The preferred method uses a resist that can be made insoluble to developer by the use of an implant. By conformally depositing the resist over a substrate having both vertical and horizontal surfaces, implanting the resist, and developing the resist, the resist is removed from the vertical surfaces while remaining on the horizontal surfaces. Thus, a self-aligned spacer is formed on the horizontal surfaces while the spacer material is removed from the vertical surfaces. This horizontal-surface spacer can then be used in further fabrication. The preferred method can be used in many different processes where there is exists a need to differentially process the vertical and horizontal surfaces of a substrate.
摘要翻译：本发明提供一种用于在水平表面上形成自对准间隔物的方法，同时从垂直表面移除间隔物材料。优选的方法使用可以通过使用植入物使其不溶于显影剂的抗蚀剂。通过在具有垂直和水平表面的基底上保形地沉积抗蚀剂，植入抗蚀剂并显影抗蚀剂，在保持在水平表面上的同时将抗蚀剂从垂直表面上除去。因此，当从垂直表面移除间隔物材料时，在水平表面上形成自对准间隔物。然后可以将该水平表面间隔件用于进一步制造。优选的方法可以用于许多不同的工艺，其中存在需要对衬底的垂直和水平表面进行差异化处理。

6. 发明授权

US06531724B1 Borderless gate structures 有权
标题翻译：无边界门结构
公开(公告)号：US06531724B1
公开(公告)日：2003-03-11
申请号：US09686740
申请日：2000-10-10
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
IPC分类号： H01L29772
CPC分类号： H01L21/76897 , H01L21/76888 , H01L21/76895
摘要： A method for forming a gate conductor cap in a transistor comprises the steps of: a) forming a polysilicon gate conductor; b) doping the polysilicon gate; c) doping diffusion areas; and d) capping the gate conductor by a nitridation method chosen from among selective nitride deposition and selective surface nitridation. The resulting transistor may comprise a capped gate conductor and borderless diffusion contacts, wherein the capping occurred by a nitridation method chosen from among selective nitride deposition and selective surface nitridation and wherein a portion of the gate conductor is masked during the nitridation method to leave open a contact area for a local interconnect or a gate contact.
摘要翻译：一种用于在晶体管中形成栅极导体帽的方法，包括以下步骤：a）形成多晶硅栅极导体; b）掺杂多晶硅栅极; c）掺杂扩散区域; 以及d）通过从选择性氮化物沉积和选择性表面氮化中选择的氮化方法来封盖栅极导体。所得到的晶体管可以包括封盖栅极导体和无边界扩散接触，其中通过选择性氮化物沉积和选择性表面氮化中选择的氮化方法发生封盖，并且其中在氮化方法期间掩模一部分栅极导体以留下开口接触区域用于局部互连或门接触。

7. 发明授权

US06440801B1 Structure for folded architecture pillar memory cell 有权
标题翻译：折叠式立柱式记忆体结构
公开(公告)号：US06440801B1
公开(公告)日：2002-08-27
申请号：US09604901
申请日：2000-06-28
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Howard L. Kalter , Jack A. Mandelman , Paul A. Rabidoux , Jeffrey J. Welser
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Howard L. Kalter , Jack A. Mandelman , Paul A. Rabidoux , Jeffrey J. Welser
IPC分类号： H01L21336
CPC分类号： H01L27/11556 , H01L27/10808 , H01L27/10823 , H01L27/10841 , H01L27/10897 , H01L27/115
摘要： A densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has rows of wordlines and columns of bitlines. The array has vertical pillars, each having two wordlines, one active and the other passing for each, cell. Two wordlines are formed per pillar on opposite pillar sidewalls which are along the row direction. The threshold voltage of the pillar device is raised on the side of the pillar touching the passing wordline, thereby permanently shutting off the pillar device during the cell operation and isolating the pillar from the voltage variations on the passing wordline. The isolated wordlines allow individual cells to be addressed and written via direct tunneling, in both volatile and non-volatile memory cell configurations. For Gbit DRAM application, stack or trench capacitors may be formed on the pillars, or in trenches surrounding the pillars, respectively.
摘要翻译：公开了一种具有支柱的紧密堆叠的垂直半导体器件阵列及其制造方法。该阵列具有字线和位线列。阵列具有垂直柱，每个具有两个字线，一个有效，另一个通过每个单元格。在沿着行方向的相对的支柱侧壁上的每个柱形成两个字线。支柱装置的阈值电压在柱体侧面升高，接触通过字线，从而在电池工作期间永久地关闭支柱装置，并将支柱与通过字线上的电压变化隔离。孤立的字线允许在易失性和非易失性存储单元配置中通过直接隧道寻址和写入各个单元。对于Gbit DRAM应用，可以在支柱上或在柱子周围的沟槽中分别形成堆叠或沟槽电容器。

8. 发明授权

US06221704B1 Process for fabricating short channel field effect transistor with a highly conductive gate 失效
公开(公告)号：US06221704B1
公开(公告)日：2001-04-24
申请号：US09089650
申请日：1998-06-03
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , James S. Nakos , Paul A. Rabidoux
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , James S. Nakos , Paul A. Rabidoux
IPC分类号： H01L2144
CPC分类号： H01L21/76897 , H01L21/28123 , H01L21/823842 , H01L29/66575
摘要： Semiconductor devices are fabricated by providing a substrate; forming isolation regions in the substrate; forming a first insulating layer on the isolation regions and the substrate; forming a conductive-forming layer on the first insulating layer; forming a second insulating layer on the conductive layer; forming a resist layer on the second insulating layer; forming an opening through the resist down to the second insulating layer located vertically between the isolation region; removing the second insulating layer beneath the opening down to the conductive-forming layer; depositing a conductive material through the opening over the conductive layer; planarizing the second insulating layer and the conductive material; removing the second insulating layer, the conductive-forming layer and the first insulating layer except beneath the conductive material; and forming source/drain regions in the substrate; or by providing a substrate; forming isolation regions in the substrate; forming a first insulating layer on the isolation regions and the substrate; forming a first conductive-forming layer on the first insulating layer; forming a second conductive layer on the first conductive-forming layer; forming a second insulating layer on the second conductive layer; forming a resist layer on the second insulating layer; forming an opening through the resist down to the second insulating layer located vertically between the isolation region; removing the second insulating layer beneath the opening down to the second conductive layer; depositing a third insulating material through the opening over the conductive layer; planarizing the second insulating layer and the third insulating material; removing the second insulating layer, the first conductive-forming layer and second conductive layer and the first insulating layer except beneath the third insulating material; and forming source/drain regions in the substrate.

9. 发明授权

US5945707A DRAM cell with grooved transfer device 失效
标题翻译：具有槽式转移装置的DRAM单元
公开(公告)号：US5945707A
公开(公告)日：1999-08-31
申请号：US56903
申请日：1998-04-07
申请人： Gary B. Bronner , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Jack A. Mandelman , Paul A. Rabidoux
发明人： Gary B. Bronner , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Jack A. Mandelman , Paul A. Rabidoux
IPC分类号： H01L21/8242 , H01L29/72
CPC分类号： H01L27/10876 , H01L27/10861 , H01L27/10891
摘要： A memory cell having a grooved gate formed in a sub-lithographic groove, and methods of making thereof are disclosed. The groove extends the channel length to include the groove sidewalls and width of the groove. Sidewall sections of the channel located along the gate sidewalls have a larger length than the bottom channel section length located along the gate bottom width. Thus, the memory device is primarily controlled by the sidewall channel sections, instead of the bottom channel section. The groove may be a stepped groove formed by a two step etch to further increase the channel length and may be formed centered along the gate conductor width.
摘要翻译：公开了一种在副光刻槽中形成有槽栅的存储单元及其制造方法。凹槽延伸通道长度以包括凹槽侧壁和凹槽的宽度。沿着栅极侧壁的通道的侧壁部分具有比沿着栅极底部宽度定位的底部通道部分长度更大的长度。因此，存储器件主要由侧壁通道部分而不是底部通道部分控制。沟槽可以是通过两步蚀刻形成的阶梯槽，以进一步增加沟道长度，并且可以沿着栅极导体宽度形成为中心。

10. 发明授权

US06759315B1 Method for selective trimming of gate structures and apparatus formed thereby 失效
标题翻译：选择性修整栅极结构的方法及由此形成的装置
公开(公告)号：US06759315B1
公开(公告)日：2004-07-06
申请号：US09224759
申请日：1999-01-04
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
IPC分类号： H01L218238
CPC分类号： H01L21/76897 , H01L21/76888 , H01L21/76895
摘要： A method for forming a trimmed gate in a transistor comprises the steps of forming a polysilicon gate conductor on a semiconductor substrate and trimming the polysilicon portion by a film growth method chosen from among selective surface oxidation and selective surface nitridation. The trimming step may selectively compensate n-channel and p-channel devices. Also, the trimming film may optionally be removed by a method chosen from among anisotropic and isotropic etching. Further, gate conductor spacers may be formed by anisotropic etching of the grown film. The resulting transistor may comprise a trimmed polysilicon portion of a gate conductor, wherein the trimming occurred by a film growth method chosen from among selective surface oxidation and selective surface nitridation.
摘要翻译：在晶体管中形成修整栅极的方法包括以下步骤：在半导体衬底上形成多晶硅栅极导体，并通过从选择性表面氧化和选择性表面氮化中选择的膜生长方法来修整多晶硅部分。修整步骤可以选择性地补偿n沟道和p沟道器件。此外，修整膜可以任选地通过从各向异性和各向同性蚀刻中选择的方法去除。此外，可以通过生长膜的各向异性蚀刻形成栅极导体间隔物。所得到的晶体管可以包括栅极导体的经修剪的多晶硅部分，其中通过从选择性表面氧化和选择性表面氮化中选择的膜生长方法进行修整。

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