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1. 发明申请

US20090125865A1 SYSTEM AND METHOD FOR MAKING PHOTOMASKS 有权
标题翻译：制作光子的系统和方法
公开(公告)号：US20090125865A1
公开(公告)日：2009-05-14
申请号：US11940270
申请日：2007-11-14
申请人： Thomas J. Aton , Carl A. Vickery , Frank Scott Johnson , James Walter Blatchford , Benjamen Michael Rathsack , Benjamin McKee
发明人： Thomas J. Aton , Carl A. Vickery , Frank Scott Johnson , James Walter Blatchford , Benjamen Michael Rathsack , Benjamin McKee
IPC分类号： G06F17/50 , H05K1/00
CPC分类号： G03F1/36
摘要： The present disclosure is directed a method for preparing photomask patterns. The method comprises receiving drawn pattern data for a design database. The drawn pattern data describes first device features and second device features, the second device features being associated with design specifications for providing a desired connectivity of the first device features to the second device features. At least a first plurality of the first device features have drawn patterns that will not result in sufficient coverage to effect the desired connectivity. Photomask patterns are formed for the first device features, wherein the photomask patterns for the first plurality of the first device features will result in the desired coverage. Integrated circuit devices formed using the principles of the present disclosure are also taught.
摘要翻译：本公开涉及一种制备光掩模图案的方法。该方法包括接收用于设计数据库的绘制图案数据。所绘制的图案数据描述了第一设备特征和第二设备特征，第二设备特征与用于向第二设备特征提供第一设备特征的期望连接性的设计规范相关联。至少第一多个第一设备特征具有不会导致足够的覆盖以实现期望的连接性的图形。为第一器件特征形成光掩模图案，其中用于第一多个第一器件特征的光掩模图案将导致期望的覆盖。还教导了使用本公开的原理形成的集成电路器件。

2. 发明授权

US07930656B2 System and method for making photomasks 有权
标题翻译：制作光掩模的系统和方法
公开(公告)号：US07930656B2
公开(公告)日：2011-04-19
申请号：US11940270
申请日：2007-11-14
申请人： Thomas J. Aton , Carl A. Vickery , Frank Scott Johnson , James Walter Blatchford , Benjamen Michael Rathsack , Benjamin McKee
发明人： Thomas J. Aton , Carl A. Vickery , Frank Scott Johnson , James Walter Blatchford , Benjamen Michael Rathsack , Benjamin McKee
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： The present disclosure is directed a method for preparing photomask patterns. The method comprises receiving drawn pattern data for a design database. The drawn pattern data describes first device features and second device features, the second device features being associated with design specifications for providing a desired connectivity of the first device features to the second device features. At least a first plurality of the first device features have drawn patterns that will not result in sufficient coverage to effect the desired connectivity. Photomask patterns are formed for the first device features, wherein the photomask patterns for the first plurality of the first device features will result in the desired coverage. Integrated circuit devices formed using the principles of the present disclosure are also taught.
摘要翻译：本公开涉及一种制备光掩模图案的方法。该方法包括接收用于设计数据库的绘制图案数据。所绘制的图案数据描述了第一设备特征和第二设备特征，第二设备特征与用于向第二设备特征提供第一设备特征的期望连接性的设计规范相关联。至少第一多个第一设备特征具有不会导致足够的覆盖以实现期望的连接性的图形。为第一器件特征形成光掩模图案，其中用于第一多个第一器件特征的光掩模图案将导致期望的覆盖。还教导了使用本公开的原理形成的集成电路器件。

3. 发明授权

US07960287B2 Methods for fabricating FinFET structures having different channel lengths 有权
标题翻译：制造具有不同沟道长度的FinFET结构的方法
公开(公告)号：US07960287B2
公开(公告)日：2011-06-14
申请号：US12891365
申请日：2010-09-27
申请人： Frank Scott Johnson , Richard T. Schultz
发明人： Frank Scott Johnson , Richard T. Schultz
IPC分类号： H01L21/311
CPC分类号： H01L21/823431 , H01L29/66795 , H01L29/66818
摘要： Methods for fabricating FinFET structures having gate structures of different gate widths are provided. The methods include the formation of sidewall spacers of different thicknesses to define gate structures of the FinFET structures with different gate widths. The width of a sidewall spacer is defined by the height of the structure about which the sidewall spacer is formed, the thickness of the sidewall spacer material layer from which the spacer is formed, and the etch parameters used to etch the sidewall spacer material layer. By forming structures of varying height, forming the sidewall spacer material layer of varying thickness, or a combination of these, sidewall spacers of varying width can be fabricated and subsequently used as an etch mask so that gate structures of varying widths can be formed simultaneously.
摘要翻译：提供了制造具有不同栅极宽度的栅极结构的FinFET结构的方法。这些方法包括形成不同厚度的侧壁间隔物，以限定具有不同栅极宽度的FinFET结构的栅极结构。侧壁间隔物的宽度由形成侧壁间隔物的结构的高度，形成间隔物的侧壁间隔材料层的厚度和用于蚀刻侧壁间隔物材料层的蚀刻参数限定。通过形成不同高度的结构，形成不同厚度的侧壁间隔物材料层或这些的组合，可以制造不同宽度的侧壁间隔物，并随后用作蚀刻掩模，从而可以同时形成不同宽度的栅极结构。

4. 发明申请

US20090286375A1 METHOD OF FORMING SIDEWALL SPACERS TO REDUCE FORMATION OF RECESSES IN THE SUBSTRATE AND INCREASE DOPANT RETENTION IN A SEMICONDUCTOR DEVICE 有权
标题翻译：形成侧壁间隔的方法，以减少在基底中形成的凹陷并增加半导体器件中的氘保持
公开(公告)号：US20090286375A1
公开(公告)日：2009-11-19
申请号：US12122885
申请日：2008-05-19
申请人： Mahalingam Nandakumar , Said Ghneim , Frank Scott Johnson
发明人： Mahalingam Nandakumar , Said Ghneim , Frank Scott Johnson
IPC分类号： H01L21/336
CPC分类号： H01L21/28247 , H01L29/6656
摘要： A method of forming sidewall spacers for a gate in a semiconductor device includes re-oxidizing/annealing silicon of the substrate and silicon of the gate after formation of the gate. The substrate is re-oxidized by performing an anneal in an inert atmosphere or ambient. The substrate may be re-oxidized/annealing after depositing an oxide layer covering the substrate and gate. Additionally, the substrate may be re-oxidized/annealing after forming the gate without depositing the oxide layer.
摘要翻译：在半导体器件中形成用于栅极的侧壁间隔物的方法包括：在栅极形成之后，再次氧化/退火衬底的硅和栅极的硅。通过在惰性气氛或环境中进行退火，使基板再次氧化。在沉积覆盖衬底和栅极的氧化物层之后，衬底可以被再氧化/退火。此外，可以在形成栅极之后再次氧化/退火衬底，而不沉积氧化物层。

5. 发明授权

US08729609B2 Integrated circuits including multi-gate transistors locally interconnected by continuous fin structure and methods for the fabrication thereof 有权
标题翻译：集成电路包括通过连续鳍结构局部互连的多栅极晶体及其制造方法
公开(公告)号：US08729609B2
公开(公告)日：2014-05-20
申请号：US12711022
申请日：2010-02-23
申请人： Frank Scott Johnson , Andreas Knorr
发明人： Frank Scott Johnson , Andreas Knorr
IPC分类号： H01L29/66
CPC分类号： H01L27/1207 , H01L21/76895 , H01L21/823431 , H01L21/823821 , H01L21/845 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of an integrated circuit are provided. In one embodiment, the integrated circuit includes a substrate and a plurality of locally interconnected multi-gate transistors. The plurality of locally interconnected multi-gate transistors includes a continuous fin structure formed on the substrate and first and second multi-gate transistors formed on the substrate and including first and second fin segments of the continuous fin structure, respectively. The continuous fin structure electrically interconnects the first and second multi-gate transistors.
摘要翻译：提供集成电路的实施例。在一个实施例中，集成电路包括衬底和多个局部互连的多栅极晶体管。多个本地互连的多栅极晶体管包括形成在衬底上的连续鳍结构，以及形成在衬底上的第一和第二多栅极晶体管，并且分别包括连续鳍结构的第一鳍片段和第二鳍片段。连续翅片结构使第一和第二多栅极晶体管电连接。

6. 发明申请

US20130309838A1 METHODS FOR FABRICATING FINFET INTEGRATED CIRCUITS ON BULK SEMICONDUCTOR SUBSTRATES 有权
标题翻译：在半导体衬底上制造FINFET集成电路的方法
公开(公告)号：US20130309838A1
公开(公告)日：2013-11-21
申请号：US13474443
申请日：2012-05-17
申请人： Andy C. Wei , Francis C. Tambwe , Frank Scott Johnson
发明人： Andy C. Wei , Francis C. Tambwe , Frank Scott Johnson
IPC分类号： H01L21/762
CPC分类号： H01L21/76229 , H01L21/3086 , H01L21/823821 , H01L29/6681
摘要： Methods are provided for fabricating FinFET integrated circuits on bulk semiconductor substrates. In accordance with one embodiment a patterned hard mask that defines locations of a regular array of a plurality of fins is formed overlying a semiconductor substrate. Portions of the patterned hard mask are removed using a cut mask to form a modified hard mask. The substrate is etched using the modified hard mask as an etch mask to form a plurality of fins extending upwardly from the substrate and separated by trenches. Selected ones of the plurality of fins are at least partially removed to form isolation regions and an insulating material is deposited to fill the trenches and to cover the at least partially removed selected ones of the plurality of fins.
摘要翻译：提供了用于在体半导体衬底上制造FinFET集成电路的方法。根据一个实施例，形成覆盖半导体衬底的限定多个翅片的规则阵列的位置的图案化硬掩模。使用切割掩模去除图案化硬掩模的部分以形成修改的硬掩模。使用改进的硬掩模作为蚀刻掩模蚀刻衬底，以形成从衬底向上延伸并由沟槽分离的多个鳍。至少部分地去除多个翅片中的选定的翅片以形成隔离区域，并且沉积绝缘材料以填充沟槽并且覆盖多个翅片中的至少部分移除的选定翼片。

7. 发明授权

US08039326B2 Methods for fabricating bulk FinFET devices having deep trench isolation 有权
标题翻译：用于制造具有深沟槽隔离的体积FinFET器件的方法
公开(公告)号：US08039326B2
公开(公告)日：2011-10-18
申请号：US12544931
申请日：2009-08-20
申请人： Andreas Knorr , Frank Scott Johnson
发明人： Andreas Knorr , Frank Scott Johnson
IPC分类号： H01L21/00 , H01L21/84 , H01L21/8234 , H01L21/336
CPC分类号： H01L21/76232 , H01L29/66795 , H01L29/7851
摘要： Methods are provided for fabricating Bulk FinFET devices having deep trench isolation. One or more deep isolation trenches are formed in a bulk silicon wafer. Mandrel-forming material is deposited overlying the bulk silicon wafer and dielectric pad layer thereon and simultaneously into the trench(es) as filler material. Mandrels are formed, overetching thereof creating a recess at the trench upper end. A conformal sidewall spacer material from which sidewall spacers are fabricated is deposited overlying the mandrels and into the recess forming a spacer overlying the filler material in the trench(es). Mandrels are removed using the spacer as an etch stop. Fin structures are formed from the bulk silicon wafer using the sidewall spacers as an etch mask. The mandrel-forming material is amorphous and/or polycrystalline silicon.
摘要翻译：提供了用于制造具有深沟槽隔离的块状FinFET器件的方法。在体硅晶片中形成一个或多个深隔离沟槽。在其上的沉积硅晶片和介质垫层上沉积形成心轴的材料，同时沉积到作为填充材料的沟槽中。形成心轴，其过蚀刻在沟槽上端形成凹部。制造侧壁间隔件的共形侧壁间隔材料沉积在芯轴上并且形成凹槽，形成覆盖沟槽中的填充材料的间隔物。使用间隔物去除心轴作为蚀刻停止。使用侧壁间隔物作为蚀刻掩模，从体硅晶片形成翅片结构。心轴形成材料是非晶和/或多晶硅。

8. 发明授权

US07785970B2 Method of forming source and drain regions utilizing dual capping layers and split thermal processes 有权
标题翻译：使用双重封盖层和分裂热处理形成源区和漏区的方法
公开(公告)号：US07785970B2
公开(公告)日：2010-08-31
申请号：US11841269
申请日：2007-08-20
申请人： Frank Scott Johnson , Shaofeng Yu
发明人： Frank Scott Johnson , Shaofeng Yu
IPC分类号： H01L21/8238
CPC分类号： H01L29/7847 , H01L21/324 , H01L21/823807 , H01L21/823814 , H01L29/6659 , H01L29/7833
摘要： Source and drain regions are formed in a first-type semiconductor device. Then, a high tensile stress capping layer is formed over the source and drain regions. A thermal process is then performed to re-crystallize the source and drain regions and to introduce tensile strain into the source and drain regions of the first-type semiconductor device. Afterwards, source and drain regions are formed in a second-type semiconductor device. Then, a high compressive stress capping layer is formed over the source and drain regions of the second-type semiconductor device. A thermal process is performed to re-crystallize the source and drain regions and to introduce compressive strain into the source and drain regions of the second-type semiconductor device.
摘要翻译：源区和漏区形成在第一类半导体器件中。然后，在源极和漏极区域上形成高拉伸应力覆盖层。然后进行热处理以使源极和漏极区域再结晶，并将拉伸应变引入第一类型半导体器件的源极和漏极区域。之后，源区和漏区形成在第二类半导体器件中。然后，在第二类型半导体器件的源极和漏极区域上形成高压缩应力覆盖层。执行热处理以使源区和漏区重新结晶，并将压缩应变引入第二类半导体器件的源区和漏区。

9. 发明授权

US08192641B2 Methods for fabricating non-planar electronic devices having sidewall spacers formed adjacent selected surfaces 有权
标题翻译：制造具有邻近选定表面的侧壁间隔物的非平面电子器件的方法
公开(公告)号：US08192641B2
公开(公告)日：2012-06-05
申请号：US12508421
申请日：2009-07-23
申请人： Frank Scott Johnson
发明人： Frank Scott Johnson
IPC分类号： B44C1/22 , C03C15/00 , C03C25/68 , C23F1/00
CPC分类号： H01L21/3086 , H01L21/31116 , H01L21/32139 , H01L21/845 , H01L29/66795 , H01L29/785
摘要： Methods are provided for fabricating an electronic device having at least one sidewall spacer formed adjacent a selected surface. In one embodiment, the method includes the step of depositing spacer material adjacent first and second raised structures formed on the substrate and extending along substantially perpendicular axes. The method further includes the step of selectively removing spacer material laterally adjacent one of the first raised structure and the second raised structure. During the step of selectively removing, the electronic device is bombarded with ions from a first predetermined direction forming a first predetermined grazing angle with the substrate such that the spacer material adjacent a first sidewall of the first raised structure is substantially exposed to the ion bombardment while the spacer material adjacent opposing sidewalls of the second raised structure is substantially shielded therefrom.
摘要翻译：提供了用于制造具有邻近选定表面形成的至少一个侧壁间隔物的电子器件的方法。在一个实施例中，该方法包括以下步骤：将邻近第一和第二凸起结构的间隔材料沉积在基底上并且沿着基本垂直的轴线延伸。该方法还包括以下步骤：在第一凸起结构和第二凸起结构之一上横向相邻地选择性地去除间隔物。在选择性去除的步骤期间，电子器件被从第一预定方向的离子轰击，与基底形成第一预定的掠角，使得邻近第一凸起结构的第一侧壁的间隔物基本上暴露于离子轰击，而与第二凸起结构的相对侧壁相邻的间隔物基本上被屏蔽。

10. 发明申请

US20110266622A1 SEMICONDUCTOR DEVICE WITH STRESSED FIN SECTIONS 有权
标题翻译：半导体器件与强化部分
公开(公告)号：US20110266622A1
公开(公告)日：2011-11-03
申请号：US13180300
申请日：2011-07-11
申请人： Scott Luning , Frank Scott Johnson
发明人： Scott Luning , Frank Scott Johnson
IPC分类号： H01L29/786
CPC分类号： H01L29/7842 , H01L29/66795 , H01L29/785
摘要： A method of fabricating a semiconductor device is provided. The method forms a fin arrangement on a semiconductor substrate, the fin arrangement comprising one or more semiconductor fin structures. The method continues by forming a gate arrangement overlying the fin arrangement, where the gate arrangement includes one or more adjacent gate structures. The method proceeds by forming an outer spacer around sidewalls of each gate structure. The fin arrangement is then selectively etched, using the gate structure and the outer spacer(s) as an etch mask, resulting in one or more semiconductor fin sections underlying the gate structure(s). The method continues by forming a stress/strain inducing material adjacent sidewalls of the one or more semiconductor fin sections.
摘要翻译：提供一种制造半导体器件的方法。所述方法在半导体衬底上形成翅片布置，所述翅片布置包括一个或多个半导体翅片结构。该方法通过形成覆盖鳍片布置的栅极布置继续，其中栅极布置包括一个或多个相邻栅极结构。该方法通过在每个栅极结构的侧壁周围形成外部间隔来进行。然后使用栅极结构和外部间隔物作为蚀刻掩模来选择性地蚀刻鳍片布置，从而导致栅极结构下面的一个或多个半导体鳍片部分。该方法通过在一个或多个半导体鳍片部分的侧壁附近形成应力/应变诱导材料来继续。

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