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1. 发明申请

US20090053865A1 METHOD AND APPARATUS FOR DE-INTERLACING VIDEO DATA 有权
标题翻译：用于去互联视频数据的方法和装置
公开(公告)号：US20090053865A1
公开(公告)日：2009-02-26
申请号：US11841269
申请日：2007-08-20
申请人： Frank Scott Johnson , Shaofeng Yu
发明人： Frank Scott Johnson , Shaofeng Yu
IPC分类号： H01L21/8238
CPC分类号： H01L29/7847 , H01L21/324 , H01L21/823807 , H01L21/823814 , H01L29/6659 , H01L29/7833
摘要： Source and drain regions are formed in a first-type semiconductor device. Then, a high tensile stress capping layer is formed over the source and drain regions. A thermal process is then performed to re-crystallize the source and drain regions and to introduce tensile strain into the source and drain regions of the first-type semiconductor device. Afterwards, source and drain regions are formed in a second-type semiconductor device. Then, a high compressive stress capping layer is formed over the source and drain regions of the second-type semiconductor device. A thermal process is performed to re-crystallize the source and drain regions and to introduce compressive strain into the source and drain regions of the second-type semiconductor device.
摘要翻译：源区和漏区形成在第一类半导体器件中。然后，在源极和漏极区域上形成高拉伸应力覆盖层。然后进行热处理以使源极和漏极区域再结晶，并将拉伸应变引入第一类型半导体器件的源极和漏极区域。之后，源区和漏区形成在第二类半导体器件中。然后，在第二类型半导体器件的源极和漏极区域上形成高压缩应力覆盖层。执行热处理以使源区和漏区重新结晶，并将压缩应变引入第二类半导体器件的源区和漏区。

2. 发明授权

US07785970B2 Method of forming source and drain regions utilizing dual capping layers and split thermal processes 有权
标题翻译：使用双重封盖层和分裂热处理形成源区和漏区的方法
公开(公告)号：US07785970B2
公开(公告)日：2010-08-31
申请号：US11841269
申请日：2007-08-20
申请人： Frank Scott Johnson , Shaofeng Yu
发明人： Frank Scott Johnson , Shaofeng Yu
IPC分类号： H01L21/8238
CPC分类号： H01L29/7847 , H01L21/324 , H01L21/823807 , H01L21/823814 , H01L29/6659 , H01L29/7833
摘要： Source and drain regions are formed in a first-type semiconductor device. Then, a high tensile stress capping layer is formed over the source and drain regions. A thermal process is then performed to re-crystallize the source and drain regions and to introduce tensile strain into the source and drain regions of the first-type semiconductor device. Afterwards, source and drain regions are formed in a second-type semiconductor device. Then, a high compressive stress capping layer is formed over the source and drain regions of the second-type semiconductor device. A thermal process is performed to re-crystallize the source and drain regions and to introduce compressive strain into the source and drain regions of the second-type semiconductor device.
摘要翻译：源区和漏区形成在第一类半导体器件中。然后，在源极和漏极区域上形成高拉伸应力覆盖层。然后进行热处理以使源极和漏极区域再结晶，并将拉伸应变引入第一类型半导体器件的源极和漏极区域。之后，源区和漏区形成在第二类半导体器件中。然后，在第二类型半导体器件的源极和漏极区域上形成高压缩应力覆盖层。执行热处理以使源区和漏区重新结晶，并将压缩应变引入第二类半导体器件的源区和漏区。

3. 发明授权

US08467233B2 Asymmetric static random access memory cell with dual stress liner 有权
标题翻译：具有双重应力衬垫的非对称静态随机存取存储单元
公开(公告)号：US08467233B2
公开(公告)日：2013-06-18
申请号：US13154225
申请日：2011-06-06
申请人： Shaofeng Yu , Wah Kit Loh
发明人： Shaofeng Yu , Wah Kit Loh
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , H01L21/823807 , H01L27/0207 , H01L27/1104 , H01L29/7843
摘要： A solid-state memory in which each memory cell is constructed of complementary metal-oxide-semiconductor (CMOS) inverters implemented with dual stress liner (DSL) technology. Asymmetry is incorporated into each memory cell by constructing one of the inverter transistors or the pass-gate transistor using the stress liner with opposite stress characteristics from its opposing counterpart. For example, both of the p-channel load transistors and one of the n-channel driver transistors in each memory cell may be constructed with a compressive nitride liner layer while the other driver transistor is constructed with a tensile nitride liner layer. In another implementation, one of the n-channel pass-gate transistors is constructed with a compressive nitride liner layer while the other pass-gate transistor is constructed with a tensile nitride liner layer. Improved cell stability due to the resulting asymmetric behavior is implemented in a cost-free manner.
摘要翻译：一种固态存储器，其中每个存储单元由用双重应力衬垫（DSL）技术实现的互补金属氧化物半导体（CMOS）反相器构成。通过使用具有相反应力特性的应力衬垫从其相对的对应物构造逆变器晶体管或通过栅极晶体管中的一个，将不对称结合到每个存储单元中。例如，p沟道负载晶体管和每个存储单元中的n沟道驱动晶体管中的一个可以由压缩氮化物衬垫层构成，而另一个驱动晶体管由氮化物衬垫层构成。在另一实现中，n沟道栅极晶体管中的一个由压缩氮化物衬垫层构成，而另一个栅极晶体管由拉伸氮化物衬垫层构成。由于产生的不对称行为而改善的细胞稳定性以无成本的方式实现。

4. 发明授权

US08372703B2 Gate dielectric first replacement gate processes and integrated circuits therefrom 有权
标题翻译：栅介质第一替代栅极工艺及其集成电路
公开(公告)号：US08372703B2
公开(公告)日：2013-02-12
申请号：US12908140
申请日：2010-10-20
申请人： Brian K. Kirkpatrick , Freidoon Mehrad , Shaofeng Yu
发明人： Brian K. Kirkpatrick , Freidoon Mehrad , Shaofeng Yu
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L29/513 , H01L29/66545 , H01L29/66553 , H01L29/6656
摘要： A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes the steps of providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the PMOS regions and NMOS regions. An original gate electrode layer is formed on the gate dielectric layer. A gate masking layer is applied on the gate electrode layer. Etching is used to pattern the original gate electrode layer to simultaneously form original gate electrodes for the PMOS devices and NMOS devices. Source and drain regions are formed for the PMOS devices and NMOS devices. The original gate electrodes are removed for at least one of the PMOS devices and NMOS devices to form trenches using an etch process, such as a hydroxide-based solution, wherein at least a portion and generally substantially all of the gate dielectric layer is preserved. A metal comprising replacement gates is formed in the trenches, and fabrication of the IC is completed.
摘要翻译：一种用于制造CMOS集成电路（IC）及其IC的方法包括提供具有半导体表面的衬底的步骤，其中半导体表面具有用于PMOS器件的PMOS区域和用于NMOS器件的NMOS区域。栅极电介质层形成在PMOS区域和NMOS区域上。在栅极电介质层上形成原始栅电极层。栅极掩模层被施加在栅极电极层上。蚀刻用于对原始栅极电极层进行图案化以同时形成用于PMOS器件和NMOS器件的原始栅电极。为PMOS器件和NMOS器件形成源极和漏极区域。为了至少一个PMOS器件和NMOS器件去除原始栅电极，以使用诸如基于氢氧化物的溶液的蚀刻工艺形成沟槽，其中保留了栅极电介质层的至少一部分和基本上全部的栅极电介质层。在沟槽中形成包括置换栅极的金属，并且完成IC的制造。

5. 发明授权

US07943456B2 Selective wet etch process for CMOS ICs having embedded strain inducing regions and integrated circuits therefrom 有权
标题翻译：具有嵌入式应变诱导区域和集成电路的CMOS IC的选择性湿蚀刻工艺
公开(公告)号：US07943456B2
公开(公告)日：2011-05-17
申请号：US12347173
申请日：2008-12-31
申请人： Shaofeng Yu , Freidoon Mehrad , Brian K. Kirkpatrick
发明人： Shaofeng Yu , Freidoon Mehrad , Brian K. Kirkpatrick
IPC分类号： H01L21/8238 , H01L29/80
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes providing a substrate having a semiconductor surface including PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate stack including a gate electrode layer is formed on a gate dielectric layer in or on both the PMOS regions and the NMOS regions. An n-type doping is used to create n-type wet etch sensitized regions on opposing sides of the gate stack in both the PMOS and said NMOS regions. Wet etching removes the n-type wet etch sensitized regions in (i) at least a portion of said PMOS regions to form a plurality of PMOS source/drain recesses or (ii) in at least a portion of said NMOS regions to form a plurality of NMOS source/drain recesses, or (i) and (ii). At least one of a compressive strain inducing epitaxial layer is formed in the plurality of PMOS source/drain recesses and a tensile strain inducing epitaxial layer is formed in the plurality of NMOS source/drain recesses. The fabrication of the IC is then completed.
摘要翻译：一种用于制造CMOS集成电路（IC）和其IC的方法包括提供具有包括用于PMOS器件的PMOS区域和NMOS器件的NMOS区域的半导体表面的衬底。包括栅极电极层的栅极堆叠形成在PMOS区域和NMOS区域中的栅极电介质层中或栅极电介质层上。使用n型掺杂来在PMOS和NMOS区域中的栅极堆叠的相对侧上产生n型湿法蚀刻增感区域。湿式蚀刻去除在（i）所述PMOS区域的至少一部分中的n型湿法蚀刻增感区域以形成多个PMOS源极/漏极凹槽，或（ii）在所述NMOS区域的至少一部分中形成多个的NMOS源/漏极凹槽，或（i）和（ii）。至少一个压应变诱导外延层形成在多个PMOS源极/漏极凹槽中，并且在多个NMOS源极/漏极凹槽中形成拉伸应变诱发外延层。然后完成IC的制造。

6. 发明授权

US07855111B2 Border region defect reduction in hybrid orientation technology (HOT) direct silicon bonded (DSB) substrates 有权
标题翻译：混合取向技术（HOT）直接硅键合（DSB）衬底的边界区域缺陷减少
公开(公告)号：US07855111B2
公开(公告)日：2010-12-21
申请号：US12538048
申请日：2009-08-07
申请人： Haowen Bu , Shaofeng Yu , Angelo Pinto , Ajith Varghese
发明人： Haowen Bu , Shaofeng Yu , Angelo Pinto , Ajith Varghese
IPC分类号： H01L21/8238 , H01L27/118
CPC分类号： H01L21/26506 , H01L21/187 , H01L21/324 , H01L21/76264 , H01L21/823807 , H01L21/823892 , H01L29/045 , H01L29/665
摘要： Hybrid orientation technology (HOT) substrates for CMOS ICs include (100)-oriented silicon regions for NMOS and (110) regions for PMOS for optimizing carrier mobilities in the respective MOS transistors. Boundary regions between (100) and (110) regions must be sufficiently narrow to support high gate densities and SRAM cells. This invention provides a method of forming a HOT substrate containing regions with two different silicon crystal lattice orientations, with boundary morphology less than 40 nanometers wide. Starting with a direct silicon bonded (DSB) wafer of a (100) substrate wafer and a (110) DBS layer, NMOS regions in the DSB layer are amorphized by a double implant and recrystallized on a (100) orientation by solid phase epitaxy (SPE). Crystal defects during anneal are prevented by a low temperature oxide layer on the top surface of the wafer. An integrated circuit formed with the inventive method is also disclosed.
摘要翻译：用于CMOS IC的混合取向技术（HOT）衬底包括用于NMOS的（100）取向硅区域和用于优化各个MOS晶体管中的载流子迁移率的用于PMOS的（110）区域。（100）和（110）区域之间的边界区域必须足够窄以支持高栅极密度和SRAM单元。本发明提供一种形成含有两个不同硅晶格取向的区域的HOT衬底的方法，边界形貌小于40纳米宽。从（100）衬底晶片和（110）DBS层的直接硅键合（DSB）晶片开始，DSB层中的NMOS区域被双注入物非晶化，并通过固相外延（100）取向（100）取向重结晶 SPE）。退火期间的晶体缺陷通过晶片顶表面上的低温氧化物层来防止。还公开了用本发明方法形成的集成电路。

7. 发明申请

US20100164008A1 METHOD FOR INTEGRATION OF REPLACEMENT GATE IN CMOS FLOW 有权
标题翻译：用于在CMOS流中整合替换门的方法
公开(公告)号：US20100164008A1
公开(公告)日：2010-07-01
申请号：US12647074
申请日：2009-12-24
申请人： Freidoon Mehrad , James J. Chambers , Shaofeng Yu
发明人： Freidoon Mehrad , James J. Chambers , Shaofeng Yu
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823842 , H01L29/66545 , H01L29/6659
摘要： Semiconductor devices and fabrication methods are provided, in which metal transistor replacement gates are provided for CMOS transistors. The process provides dual or differentiated work function capability (e.g., for PMOS and NMOS transistors) in CMOS processes.
摘要翻译：提供半导体器件和制造方法，其中为CMOS晶体管提供金属晶体管替代栅极。该过程在CMOS工艺中提供双重或差分工作功能能力（例如，用于PMOS和NMOS晶体管）。

8. 发明授权

US07642610B2 Transistor gate electrode having conductor material layer 有权
标题翻译：具有导体材料层的晶体管栅电极
公开(公告)号：US07642610B2
公开(公告)日：2010-01-05
申请号：US11715703
申请日：2007-03-08
申请人： Anand Murthy , Boyan Boyanov , Suman Datta , Brian S. Doyle , Been-Yih Jin , Shaofeng Yu , Robert Chau
发明人： Anand Murthy , Boyan Boyanov , Suman Datta , Brian S. Doyle , Been-Yih Jin , Shaofeng Yu , Robert Chau
IPC分类号： H01L21/00
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/823857 , H01L29/66636 , H01L29/7842 , H01L29/7848
摘要： Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.
摘要翻译：本发明的各种实施例涉及在衬底上具有硅锗材料的晶体管沟道的PMOS器件，介电常数大于沟道上的二氧化硅的介电常数的栅极电介质，具有功函数的栅电极导体材料在栅极电介质上的硅的价态能带边缘和导体能带边缘之间的范围，以及栅电极导体材料上的栅电极半导体材料。

9. 发明申请

US20090315076A1 TRANSISTOR GATE ELECTRODE HAVING CONDUCTOR MATERIAL LAYER 有权
标题翻译：具有导体材料层的晶体管栅极电极
公开(公告)号：US20090315076A1
公开(公告)日：2009-12-24
申请号：US12553033
申请日：2009-09-02
申请人： Anand Murthy , Boyan Boyanov , Suman Datta , Brian S. Doyle , Been-Yih Jin , Shaofeng Yu , Robert Chau
发明人： Anand Murthy , Boyan Boyanov , Suman Datta , Brian S. Doyle , Been-Yih Jin , Shaofeng Yu , Robert Chau
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/823857 , H01L29/66636 , H01L29/7842 , H01L29/7848
摘要： Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.
摘要翻译：本发明的各种实施例涉及在衬底上具有硅锗材料的晶体管沟道的PMOS器件，介电常数大于沟道上的二氧化硅的介电常数的栅极电介质，具有功函数的栅电极导体材料在栅极电介质上的硅的价态能带边缘和导体能带边缘之间的范围，以及栅电极导体材料上的栅电极半导体材料。

10. 发明授权

US07585738B2 Method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device 有权
标题翻译：用独立的栅极和源极/漏极掺杂形成完全硅化半导体器件的方法及相关器件
公开(公告)号：US07585738B2
公开(公告)日：2009-09-08
申请号：US11741540
申请日：2007-04-27
申请人： Shaofeng Yu , Freidoon Mehrad , Jiong-Ping Lu
发明人： Shaofeng Yu , Freidoon Mehrad , Jiong-Ping Lu
IPC分类号： H01L21/336 , H01L21/44
CPC分类号： H01L21/28097 , H01L29/66507 , H01L29/66545
摘要： A method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a substrate (the gate stack comprising a polysilicon layer and a blocking layer), and performing an ion implantation into an active region of the substrate adjacent to the gate stack (the blocking layer substantially blocks the ion implantation from the polysilicon layer).
摘要翻译：一种形成具有独立栅极和源极/漏极掺杂及相关器件的完全硅化半导体器件的方法。示例性实施例中的至少一些是包括在衬底上形成栅极堆叠的方法（包括多晶硅层和阻挡层的栅极堆叠），以及执行离子注入到与栅极堆叠相邻的衬底的有源区域中阻挡层基本上阻挡从多晶硅层的离子注入）。

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