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1. 发明申请

US20070042535A1 INTEGRATED CIRCUIT CONTAINING POLYSILICON GATE TRANSISTORS AND FULLY SILICIDIZED METAL GATE TRANSISTORS 有权
标题翻译：包含多晶硅栅极晶体管和完全硅化金属栅极晶体管的集成电路
公开(公告)号：US20070042535A1
公开(公告)日：2007-02-22
申请号：US11553839
申请日：2006-10-27
申请人： Shaofeng Yu , Benjamin McKee
发明人： Shaofeng Yu , Benjamin McKee
IPC分类号： H01L21/8232 , H01L21/335
CPC分类号： H01L21/28518 , H01L21/28052 , H01L21/28097 , H01L21/823835 , H01L21/823842 , H01L21/823878 , H01L29/4933 , H01L29/4975 , H01L29/665 , H01L29/66545
摘要： A method for manufacturing an integrated circuit 10 having transistors 20, 30 of two threshold voltages where protected transistor stacks 270 have a gate protection layer 220 that are formed with the use of a single additional mask step. Also, an integrated circuit 10 having at least one polysilicon gate transistor 20 and at least one FUSI metal gate transistor 30.
摘要翻译：一种用于制造具有两个阈值电压的晶体管20,30的集成电路10的方法，其中受保护的晶体管堆叠270具有使用单个附加掩模步骤形成的栅极保护层220。而且，具有至少一个多晶硅栅极晶体管20和至少一个FUSI金属栅极晶体管30的集成电路10。

2. 发明申请

US20060270140A1 Methods for Transistor Formation Using Selective Gate Implantation 有权
标题翻译：使用选择性栅植入的晶体管形成方法
公开(公告)号：US20060270140A1
公开(公告)日：2006-11-30
申请号：US11462541
申请日：2006-08-04
申请人： F. Scott Johnson , Tad Grider , Benjamin McKee
发明人： F. Scott Johnson , Tad Grider , Benjamin McKee
IPC分类号： H01L21/8238
CPC分类号： H01L21/28035 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted in to the exposed gate structure.
摘要翻译：公开了用于半导体器件制造的方法，其中将掺杂剂选择性地注入到晶体管栅极结构中以抵消或补偿在随后的制造处理期间的掺杂剂耗尽。图案化的注入掩模形成在半导体器件上，其暴露栅极结构的至少一部分并且覆盖器件的剩余上表面。此后，将掺杂剂选择性地植入到暴露的栅极结构中。

3. 发明申请

US20090125865A1 SYSTEM AND METHOD FOR MAKING PHOTOMASKS 有权
标题翻译：制作光子的系统和方法
公开(公告)号：US20090125865A1
公开(公告)日：2009-05-14
申请号：US11940270
申请日：2007-11-14
申请人： Thomas J. Aton , Carl A. Vickery , Frank Scott Johnson , James Walter Blatchford , Benjamen Michael Rathsack , Benjamin McKee
发明人： Thomas J. Aton , Carl A. Vickery , Frank Scott Johnson , James Walter Blatchford , Benjamen Michael Rathsack , Benjamin McKee
IPC分类号： G06F17/50 , H05K1/00
CPC分类号： G03F1/36
摘要： The present disclosure is directed a method for preparing photomask patterns. The method comprises receiving drawn pattern data for a design database. The drawn pattern data describes first device features and second device features, the second device features being associated with design specifications for providing a desired connectivity of the first device features to the second device features. At least a first plurality of the first device features have drawn patterns that will not result in sufficient coverage to effect the desired connectivity. Photomask patterns are formed for the first device features, wherein the photomask patterns for the first plurality of the first device features will result in the desired coverage. Integrated circuit devices formed using the principles of the present disclosure are also taught.
摘要翻译：本公开涉及一种制备光掩模图案的方法。该方法包括接收用于设计数据库的绘制图案数据。所绘制的图案数据描述了第一设备特征和第二设备特征，第二设备特征与用于向第二设备特征提供第一设备特征的期望连接性的设计规范相关联。至少第一多个第一设备特征具有不会导致足够的覆盖以实现期望的连接性的图形。为第一器件特征形成光掩模图案，其中用于第一多个第一器件特征的光掩模图案将导致期望的覆盖。还教导了使用本公开的原理形成的集成电路器件。

4. 发明授权

US07930656B2 System and method for making photomasks 有权
标题翻译：制作光掩模的系统和方法
公开(公告)号：US07930656B2
公开(公告)日：2011-04-19
申请号：US11940270
申请日：2007-11-14
申请人： Thomas J. Aton , Carl A. Vickery , Frank Scott Johnson , James Walter Blatchford , Benjamen Michael Rathsack , Benjamin McKee
发明人： Thomas J. Aton , Carl A. Vickery , Frank Scott Johnson , James Walter Blatchford , Benjamen Michael Rathsack , Benjamin McKee
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： The present disclosure is directed a method for preparing photomask patterns. The method comprises receiving drawn pattern data for a design database. The drawn pattern data describes first device features and second device features, the second device features being associated with design specifications for providing a desired connectivity of the first device features to the second device features. At least a first plurality of the first device features have drawn patterns that will not result in sufficient coverage to effect the desired connectivity. Photomask patterns are formed for the first device features, wherein the photomask patterns for the first plurality of the first device features will result in the desired coverage. Integrated circuit devices formed using the principles of the present disclosure are also taught.
摘要翻译：本公开涉及一种制备光掩模图案的方法。该方法包括接收用于设计数据库的绘制图案数据。所绘制的图案数据描述了第一设备特征和第二设备特征，第二设备特征与用于向第二设备特征提供第一设备特征的期望连接性的设计规范相关联。至少第一多个第一设备特征具有不会导致足够的覆盖以实现期望的连接性的图形。为第一器件特征形成光掩模图案，其中用于第一多个第一器件特征的光掩模图案将导致期望的覆盖。还教导了使用本公开的原理形成的集成电路器件。

5. 发明申请

US20060270139A1 Methods for Transistor Formation Using Selective Gate Implantation 审中-公开
标题翻译：使用选择性栅植入的晶体管形成方法
公开(公告)号：US20060270139A1
公开(公告)日：2006-11-30
申请号：US11462528
申请日：2006-08-04
申请人： F. Scott Johnson , Tad Grider , Benjamin McKee
发明人： F. Scott Johnson , Tad Grider , Benjamin McKee
IPC分类号： H01L21/8238
CPC分类号： H01L21/26513 , H01L21/28035 , H01L21/324 , H01L29/4916 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted into the exposed gate structure.
摘要翻译：公开了用于半导体器件制造的方法，其中将掺杂剂选择性地注入到晶体管栅极结构中以抵消或补偿在随后的制造处理期间的掺杂剂耗尽。图案化的注入掩模形成在半导体器件上，其暴露栅极结构的至少一部分并且覆盖器件的剩余上表面。此后，将掺杂剂选择性地注入到暴露的栅极结构中。

6. 发明申请

US20060199324A1 Integrated circuit containing polysilicon gate transistors and fully silicidized metal gate transistors 有权
公开(公告)号：US20060199324A1
公开(公告)日：2006-09-07
申请号：US11074177
申请日：2005-03-07
申请人： Shaofeng Yu , Benjamin McKee
发明人： Shaofeng Yu , Benjamin McKee
IPC分类号： H01L21/8238 , H01L21/4763 , H01L21/8234
CPC分类号： H01L21/28518 , H01L21/28052 , H01L21/28097 , H01L21/823835 , H01L21/823842 , H01L21/823878 , H01L29/4933 , H01L29/4975 , H01L29/665 , H01L29/66545
摘要： A method for manufacturing an integrated circuit 10 having transistors 20, 30 of two threshold voltages where protected transistor stacks 270 have a gate protection layer 220 that are formed with the use of a single additional mask step. Also, an integrated circuit 10 having at least one polysilicon gate transistor 20 and at least one FUSI metal gate transistor 30.

7. 发明授权

US11612501B2 Hip and knee joint stem explant system and methods of using the same 有权
公开(公告)号：US11612501B2
公开(公告)日：2023-03-28
申请号：US16657581
申请日：2019-10-18
申请人： John E. Pendleton , Daniel H. Hursh , Mary Katlyn Pitz , Benjamin McKee Stronach
发明人： John E. Pendleton , Daniel H. Hursh , Mary Katlyn Pitz , Benjamin McKee Stronach
IPC分类号： A61F2/46
摘要： Systems, instruments, tools and methods for facilitating the removal of a knee or hip implants and other bone implants.

8. 发明申请

US20070052034A1 INTEGRATED CIRCUIT CONTAINING POLYSILICON GATE TRANSISTORS AND FULLY SILICIDIZED METAL GATE TRANSISTORS 审中-公开
公开(公告)号：US20070052034A1
公开(公告)日：2007-03-08
申请号：US11553858
申请日：2006-10-27
申请人： Shaofeng Yu , Benjamin McKee
发明人： Shaofeng Yu , Benjamin McKee
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L21/28518 , H01L21/28052 , H01L21/28097 , H01L21/823835 , H01L21/823842 , H01L21/823878 , H01L29/4933 , H01L29/4975 , H01L29/665 , H01L29/66545
摘要： A method for manufacturing an integrated circuit 10 having transistors 20, 30 of two threshold voltages where protected transistor stacks 270 have a gate protection layer 220 that are formed with the use of a single additional mask step. Also, an integrated circuit 10 having at least one polysilicon gate transistor 20 and at least one FUSI metal gate transistor 30.

9. 发明申请

US20050064673A1 High capacitive density stacked decoupling capacitor structure 有权
标题翻译：高电容密度堆叠去耦电容器结构
公开(公告)号：US20050064673A1
公开(公告)日：2005-03-24
申请号：US10670037
申请日：2003-09-24
申请人： Edmund Burke , Benjamin McKee , Frank Johnson
发明人： Edmund Burke , Benjamin McKee , Frank Johnson
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L27/08 , H01L21/20
CPC分类号： H01L28/40 , H01L27/0805
摘要： A capacitive structure (10). The capacitive structure comprises a semiconductor base region (30) having an upper surface, a well (12) formed within the semiconductor base region and adjacent the upper surface, a first dielectric layer (38) adjacent at least a portion of the upper surface, and a polysilicon layer (16) adjacent the first dielectric layer. The well, the first dielectric layer, and the first polysilicon layer form a first capacitor and are aligned along a planar dimension. The capacitive structure further comprises a first conductive layer (201) positioned with at least a portion overlying at least a portion of the polysilicon layer, a second dielectric layer (202) adjacent the first conductive layer, and a second conductive layer (203) adjacent the second dielectric layer. The first conductive layer, the second dielectric layer, and the second conductive layer form a second capacitor and are aligned along the planar dimension.
摘要翻译：电容结构（10）。电容结构包括具有上表面的半导体基区（30），形成在半导体基区内且邻近上表面的阱（12），邻近上表面的至少一部分的第一介电层（38）和与第一介电层相邻的多晶硅层（16）。阱，第一电介质层和第一多晶硅层形成第一电容器并且沿着平面尺寸对准。所述电容结构还包括第一导电层（201），其位于至少覆盖所述多晶硅层的至少一部分的部分，邻近所述第一导电层的第二介电层（202）和与所述多晶硅层相邻的第二导电层（203）第二电介质层。第一导电层，第二介电层和第二导电层形成第二电容器并且沿平面尺寸排列。

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