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1. 发明授权

US08030144B2 Semiconductor device with stressed fin sections, and related fabrication methods 有权
标题翻译：具有应力鳍片的半导体器件及相关制造方法
公开(公告)号：US08030144B2
公开(公告)日：2011-10-04
申请号：US12576987
申请日：2009-10-09
申请人： Scott Luning , Frank Scott Johnson
发明人： Scott Luning , Frank Scott Johnson
IPC分类号： H01L21/00 , H01L21/84 , H01L21/338 , H01L21/336 , H01L21/3205
CPC分类号： H01L29/7842 , H01L29/66795 , H01L29/785
摘要： A method of fabricating a semiconductor device is provided. The method forms a fin arrangement on a semiconductor substrate, the fin arrangement comprising one or more semiconductor fin structures. The method continues by forming a gate arrangement overlying the fin arrangement, where the gate arrangement includes one or more adjacent gate structures. The method proceeds by forming an outer spacer around sidewalls of each gate structure. The fin arrangement is then selectively etched, using the gate structure and the outer spacer(s) as an etch mask, resulting in one or more semiconductor fin sections underlying the gate structure(s). The method continues by forming a stress/strain inducing material adjacent sidewalls of the one or more semiconductor fin sections.
摘要翻译：提供一种制造半导体器件的方法。所述方法在半导体衬底上形成翅片布置，所述翅片布置包括一个或多个半导体翅片结构。该方法通过形成覆盖鳍片布置的栅极布置继续，其中栅极布置包括一个或多个相邻栅极结构。该方法通过在每个栅极结构的侧壁周围形成外部间隔来进行。然后使用栅极结构和外部间隔物作为蚀刻掩模来选择性地蚀刻鳍片布置，从而导致栅极结构下面的一个或多个半导体鳍片部分。该方法通过在一个或多个半导体鳍片部分的侧壁附近形成应力/应变诱导材料来继续。

2. 发明授权

US08912603B2 Semiconductor device with stressed fin sections 有权
标题翻译：具有应力鳍片的半导体器件
公开(公告)号：US08912603B2
公开(公告)日：2014-12-16
申请号：US13180300
申请日：2011-07-11
申请人： Scott Luning , Frank Scott Johnson
发明人： Scott Luning , Frank Scott Johnson
IPC分类号： H01L29/786 , H01L29/66 , H01L29/78
CPC分类号： H01L29/7842 , H01L29/66795 , H01L29/785
摘要： A method of fabricating a semiconductor device is provided. The method forms a fin arrangement on a semiconductor substrate, the fin arrangement comprising one or more semiconductor fin structures. The method continues by forming a gate arrangement overlying the fin arrangement, where the gate arrangement includes one or more adjacent gate structures. The method proceeds by forming an outer spacer around sidewalls of each gate structure. The fin arrangement is then selectively etched, using the gate structure and the outer spacer(s) as an etch mask, resulting in one or more semiconductor fin sections underlying the gate structure(s). The method continues by forming a stress/strain inducing material adjacent sidewalls of the one or more semiconductor fin sections.
摘要翻译：提供一种制造半导体器件的方法。所述方法在半导体衬底上形成翅片布置，所述翅片布置包括一个或多个半导体翅片结构。该方法通过形成覆盖鳍片布置的栅极布置继续，其中栅极布置包括一个或多个相邻栅极结构。该方法通过在每个栅极结构的侧壁周围形成外部间隔来进行。然后使用栅极结构和外部间隔物作为蚀刻掩模来选择性地蚀刻鳍片布置，从而导致栅极结构下面的一个或多个半导体鳍片部分。该方法通过在一个或多个半导体鳍片部分的侧壁附近形成应力/应变诱导材料来继续。

3. 发明授权

US08039349B2 Methods for fabricating non-planar semiconductor devices having stress memory 有权
标题翻译：用于制造具有应力记忆的非平面半导体器件的方法
公开(公告)号：US08039349B2
公开(公告)日：2011-10-18
申请号：US12512814
申请日：2009-07-30
申请人： Michael J. Hargrove , Frank Scott Johnson , Scott Luning
发明人： Michael J. Hargrove , Frank Scott Johnson , Scott Luning
IPC分类号： H01L21/8234
CPC分类号： H01L21/26586 , H01L29/66795 , H01L29/66803 , H01L29/7847 , H01L29/785
摘要： Embodiments of a method are provided for fabricating a non-planar semiconductor device including a substrate having a plurality of raised crystalline structures formed thereon. In one embodiment, the method includes the steps of amorphorizing a portion of each raised crystalline structure included within the plurality of raised crystalline structures, forming a sacrificial strain layer over the plurality of raised crystalline structures to apply stress to the amorphized portion of each raised crystalline structure, annealing the non-planar semiconductor device to recrystallize the amorphized portion of each raised crystalline structure in a stress-memorized state, and removing the sacrificial strain layer.
摘要翻译：提供了一种用于制造包括其上形成有多个凸起的晶体结构的基板的非平面半导体器件的方法的实施例。在一个实施方案中，该方法包括以下步骤：将包含在多个凸起的晶体结构内的每个凸起的晶体结构的一部分非晶化，在多个凸起的晶体结构上形成牺牲应变层，以将应力施加到每个凸起晶体的非晶化部分结构，退火所述非平面半导体器件以使应力存储状态下的每个凸起晶体结构的非晶化部分重结晶，以及去除所述牺牲应变层。

4. 发明授权

US07977174B2 FinFET structures with stress-inducing source/drain-forming spacers and methods for fabricating the same 有权
标题翻译：具有应力诱导源极/漏极形成间隔物的FinFET结构及其制造方法
公开(公告)号：US07977174B2
公开(公告)日：2011-07-12
申请号：US12480269
申请日：2009-06-08
申请人： Scott Luning , Frank Scott Johnson , Michael J. Hargrove
发明人： Scott Luning , Frank Scott Johnson , Michael J. Hargrove
IPC分类号： H01L21/00
CPC分类号： H01L29/7843 , H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： Methods for fabricating FinFET structures with stress-inducing source/drain-forming spacers and FinFET structures having such spacers are provided herein. In one embodiment, a method for fabricating a FinFET structure comprises fabricating a plurality of parallel fins overlying a semiconductor substrate. Each of the fins has sidewalls. A gate structure is fabricated overlying a portion of each of the fins. The gate structure has sidewalls and overlies channels within the fins. Stress-inducing sidewall spacers are formed about the sidewalls of the fins and the sidewalls of the gate structure. The stress-inducing sidewall spacers induce a stress within the channels. First conductivity-determining ions are implanted into the fins using the stress-inducing sidewall spacers and the gate structure as an implantation mask to form source and drain regions within the fins.
摘要翻译：本文提供了制造具有应力诱导源极/漏极形成间隔物的FinFET结构和具有这种间隔物的FinFET结构的方法。在一个实施例中，制造FinFET结构的方法包括制造覆盖半导体衬底的多个平行散热片。每个翅片都有侧壁。制造覆盖每个翅片的一部分的栅极结构。栅极结构在翅片内具有侧壁并覆盖通道。应力诱导侧壁间隔件围绕翅片的侧壁和门结构的侧壁形成。应力诱导侧壁间隔物在通道内引起应力。使用应力诱导侧壁间隔物和栅极结构作为注入掩模将第一导电率确定离子注入到鳍中，以在翅片内形成源区和漏区。

5. 发明申请

US20110266622A1 SEMICONDUCTOR DEVICE WITH STRESSED FIN SECTIONS 有权
标题翻译：半导体器件与强化部分
公开(公告)号：US20110266622A1
公开(公告)日：2011-11-03
申请号：US13180300
申请日：2011-07-11
申请人： Scott Luning , Frank Scott Johnson
发明人： Scott Luning , Frank Scott Johnson
IPC分类号： H01L29/786
CPC分类号： H01L29/7842 , H01L29/66795 , H01L29/785
摘要： A method of fabricating a semiconductor device is provided. The method forms a fin arrangement on a semiconductor substrate, the fin arrangement comprising one or more semiconductor fin structures. The method continues by forming a gate arrangement overlying the fin arrangement, where the gate arrangement includes one or more adjacent gate structures. The method proceeds by forming an outer spacer around sidewalls of each gate structure. The fin arrangement is then selectively etched, using the gate structure and the outer spacer(s) as an etch mask, resulting in one or more semiconductor fin sections underlying the gate structure(s). The method continues by forming a stress/strain inducing material adjacent sidewalls of the one or more semiconductor fin sections.
摘要翻译：提供一种制造半导体器件的方法。所述方法在半导体衬底上形成翅片布置，所述翅片布置包括一个或多个半导体翅片结构。该方法通过形成覆盖鳍片布置的栅极布置继续，其中栅极布置包括一个或多个相邻栅极结构。该方法通过在每个栅极结构的侧壁周围形成外部间隔来进行。然后使用栅极结构和外部间隔物作为蚀刻掩模来选择性地蚀刻鳍片布置，从而导致栅极结构下面的一个或多个半导体鳍片部分。该方法通过在一个或多个半导体鳍片部分的侧壁附近形成应力/应变诱导材料来继续。

6. 发明授权

US08193592B2 MOSFET with asymmetrical extension implant 有权
标题翻译：具有不对称延伸植入物的MOSFET
公开(公告)号：US08193592B2
公开(公告)日：2012-06-05
申请号：US12904662
申请日：2010-10-14
申请人： Frank Bin Yang , Andrew M. Waite , Scott Luning
发明人： Frank Bin Yang , Andrew M. Waite , Scott Luning
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/26586 , H01L29/66659 , H01L29/7834 , H01L2924/0002 , Y10S438/931 , H01L2924/00
摘要： A method for fabricating a MOSFET (e.g., a PMOS FET) includes providing a semiconductor substrate having surface characterized by a (110) surface orientation or (110) sidewall surfaces, forming a gate structure on the surface, and forming a source extension and a drain extension in the semiconductor substrate asymmetrically positioned with respect to the gate structure. An ion implantation process is performed at a non-zero tilt angle. At least one spacer and the gate electrode mask a portion of the surface during the ion implantation process such that the source extension and drain extension are asymmetrically positioned with respect to the gate structure by an asymmetry measure.
摘要翻译：一种用于制造MOSFET（例如，PMOS FET）的方法包括提供具有由（110）表面取向或（110）侧壁表面表征的表面的半导体衬底，在表面上形成栅极结构，并形成源延伸和半导体衬底中的漏极延伸部相对于栅极结构非对称地定位。以非零倾角进行离子注入工艺。在离子注入过程期间，至少一个间隔物和栅电极掩盖表面的一部分，使得源极延伸和漏极延伸通过不对称度量相对于栅极结构不对称地定位。

7. 发明授权

US08148214B2 Stressed field effect transistor and methods for its fabrication 有权
标题翻译：强调场效应晶体管及其制造方法
公开(公告)号：US08148214B2
公开(公告)日：2012-04-03
申请号：US12360961
申请日：2009-01-28
申请人： Andrew M. Waite , Scott Luning
发明人： Andrew M. Waite , Scott Luning
IPC分类号： H01L21/00
CPC分类号： H01L29/6656 , H01L21/823807 , H01L21/823814 , H01L29/6653 , H01L29/66636 , H01L29/7848
摘要： A stressed field effect transistor and methods for its fabrication are provided. The field effect transistor comprises a silicon substrate with a gate insulator overlying the silicon substrate. A gate electrode overlies the gate insulator and defines a channel region in the silicon substrate underlying the gate electrode. A first silicon germanium region having a first thickness is embedded in the silicon substrate and contacts the channel region. A second silicon germanium region having a second thickness greater than the first thickness and spaced apart from the channel region is also embedded in the silicon substrate.
摘要翻译：提供了一种应力场效应晶体管及其制造方法。场效应晶体管包括具有覆盖硅衬底的栅极绝缘体的硅衬底。栅电极覆盖栅极绝缘体，并且在栅电极下面的硅衬底中限定沟道区。具有第一厚度的第一硅锗区域嵌入在硅衬底中并与沟道区域接触。具有大于第一厚度并且与沟道区间隔开的第二厚度的第二硅锗区域也嵌入在硅衬底中。

8. 发明申请

US20110062498A1 EMBEDDED SILICON GERMANIUM SOURCE DRAIN STRUCTURE WITH REDUCED SILICIDE ENCROACHMENT AND CONTACT RESISTANCE AND ENHANCED CHANNEL MOBILITY 有权
标题翻译：嵌入式硅锗锗排水结构，具有降低的硅胶密封性和接触电阻和增强的通道移动性
公开(公告)号：US20110062498A1
公开(公告)日：2011-03-17
申请号：US12561685
申请日：2009-09-17
申请人： Frank (Bin) Yang , Johan W. Weijtmans , Scott Luning
发明人： Frank (Bin) Yang , Johan W. Weijtmans , Scott Luning
IPC分类号： H01L29/772 , H01L21/335
CPC分类号： H01L29/665 , H01L29/165 , H01L29/6656 , H01L29/66575 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： Semiconductor devices with embedded silicon germanium source/drain regions are formed with enhanced channel mobility, reduced contact resistance, and reduced silicide encroachment. Embodiments include embedded silicon germanium source/drain regions with a first portion having a relatively high germanium concentration, e.g., about 25 to about 35 at. %, an overlying second portion having a first layer with a relatively low germanium concentration, e.g., about 10 to about 20 at. %, and a second layer having a germanium concentration greater than that of the first layer. Embodiments include forming additional layers on the second layer, each odd numbered layer having relatively low germanium concentration, at. % germanium, and each even numbered layer having a relatively high germanium concentration. Embodiments include forming the first region at a thickness of about 400 Å to 28 about 800 Å, and the first and second layers at a thickness of about 30 Å to about 70 Å.
摘要翻译：具有嵌入式硅锗源极/漏极区域的半导体器件形成具有增强的沟道迁移率，降低的接触电阻和减少的硅化物侵蚀。实施例包括具有较高锗浓度的第一部分的嵌入式硅锗源/漏区，例如约25至约35at。％，上覆的第二部分具有具有相对低的锗浓度的第一层，例如约10至约20at。％，第二层的锗浓度大于第一层的浓度。实施例包括在第二层上形成附加层，每个奇数层具有较低的锗浓度。％锗，并且每个偶数层具有较高的锗浓度。实施例包括形成厚度为约400至28约800的第一区域，第一和第二层的厚度为约至大约为70埃。

9. 发明授权

US07893493B2 Stacking fault reduction in epitaxially grown silicon 有权
标题翻译：堆积外延生长硅中的断层减少
公开(公告)号：US07893493B2
公开(公告)日：2011-02-22
申请号：US11456326
申请日：2006-07-10
申请人： Yun-Yu Wang , Linda Black , Judson R. Holt , Woo-Hyeong Lee , Scott Luning , Christopher D. Sheraw
发明人： Yun-Yu Wang , Linda Black , Judson R. Holt , Woo-Hyeong Lee , Scott Luning , Christopher D. Sheraw
IPC分类号： H01L27/12 , H01L21/302 , H01L21/461
CPC分类号： H01L21/02639 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/02609 , H01L21/84
摘要： An intermediate hybrid surface orientation structure may include a silicon-on-insulator (SOI) substrate adhered to a bulk silicon substrate, the silicon of the SOI substrate having a different surface orientation than that of the bulk silicon substrate, and a reachthrough region extending through the SOI substrate to the bulk silicon substrate, the reachthrough region including a silicon nitride liner over a silicon oxide liner and a silicon epitaxially grown from the bulk silicon substrate, the epitaxially grown silicon extending into an undercut into the silicon oxide liner under the silicon nitride liner, wherein the epitaxially grown silicon is substantially stacking fault free.
摘要翻译：中间混合表面取向结构可以包括粘附到体硅衬底上的绝缘体上硅（SOI）衬底，SOI衬底的硅具有与体硅衬底不同的表面取向，并且穿透区域延伸穿过 SOI衬底到体硅衬底，穿透区域包括在氧化硅衬底上的氮化硅衬垫和从体硅衬底外延生长的硅，外延生长的硅延伸到底切到氮化硅之下的氧化硅衬底中衬垫，其中外延生长的硅基本上是无层错的。

10. 发明授权

US07674720B2 Stacking fault reduction in epitaxially grown silicon 失效
标题翻译：堆积外延生长硅中的断层减少
公开(公告)号：US07674720B2
公开(公告)日：2010-03-09
申请号：US12131214
申请日：2008-06-02
申请人： Yun-Yu Wang , Linda Black , Judson R. Holt , Woo-Hyeong Lee , Scott Luning , Christopher D. Sheraw
发明人： Yun-Yu Wang , Linda Black , Judson R. Holt , Woo-Hyeong Lee , Scott Luning , Christopher D. Sheraw
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/02639 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/02609 , H01L21/84
摘要： Methods are disclosed for providing stacking fault reduced epitaxially grown silicon for use in hybrid surface orientation structures. In one embodiment, a method includes depositing a silicon nitride liner over a silicon oxide liner in an opening, etching to remove the silicon oxide liner and silicon nitride liner on a lower surface of the opening, undercutting the silicon nitride liner adjacent to the lower surface, and epitaxially growing silicon in the opening. The silicon is substantially reduced of stacking faults because of the negative slope created by the undercut.
摘要翻译：公开了用于提供用于混合表面取向结构的堆叠故障减少的外延生长的硅的方法。在一个实施例中，一种方法包括在开口中的氧化硅衬垫上沉积氮化硅衬垫，蚀刻以除去开口的下表面上的氧化硅衬垫和氮化硅衬垫，将邻近下表面的氮化硅衬垫并且在开口中外延生长硅。由于底切产生的负斜率，硅片堆积层错误大大减少。

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