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1. 发明授权

US5073970A Vector processing apparatus allowing succeeding vector instruction chain processing upon completion of decoding of a preceding vector instruction chain 失效
标题翻译：矢量处理设备允许成功的矢量指示链处理完成前向矢量指令链的解码
公开(公告)号：US5073970A
公开(公告)日：1991-12-17
申请号：US471667
申请日：1990-01-24
申请人： Tamoo Aoyama , Yasuhiro Inagami , Hiroshi Nurayama
发明人： Tamoo Aoyama , Yasuhiro Inagami , Hiroshi Nurayama
IPC分类号： G06F17/16 , G06F15/78
CPC分类号： G06F15/8076
摘要： A vector processing apparatus includes a vector processing unit having a vector instruction decoder and a scalar processing unit including a scalar instruction decoder for activating the vector processing unit in response to a scalar instruction commanding initiation of the processing of a vector instruction chain. The vector processing unit further includes an incidation register which is set in response to the initiation of decodiung of the vector instruction chain by the vector instruction decoder and reset in response to the decoding of an end vector instruction of the vector instruction chain. So long as the indication circuit is in the reset state, the vector processing unit is allowed to initiate the processing of a vector instruction chain under the command of the scaler processing unit.
摘要翻译：矢量处理装置包括：矢量处理单元，具有矢量指示解码器和标量处理单元，该标量处理单元包括：标量指令解码器，用于响应于指示矢量指令链处理的标量指令来激活矢量处理单元。向量处理单元还包括一个写入寄存器，该寄存器响应于向量指令解码器解码向量指令链而被设置，并且响应于向量指令链的结束向量指令的解码而复位。只要指示电路处于复位状态，允许向量处理单元在缩放器处理单元的命令下启动向量指令链的处理。

2. 发明授权

US5857110A Priority control with concurrent switching of priorities of vector processors, for plural priority circuits for memory modules shared by the vector processors 失效
标题翻译：优先级控制，并行切换向量处理器的优先级，用于矢量处理器共享的存储器模块的多个优先级电路
公开(公告)号：US5857110A
公开(公告)日：1999-01-05
申请号：US760525
申请日：1996-12-05
申请人： Tadayuki Sakakibara , Teruo Tanaka , Katsuyoshi Kitai , Tadaaki Isobe , Shigeko Hashimoto , Yasuhiro Inagami , Yoshiko Tamaki
发明人： Tadayuki Sakakibara , Teruo Tanaka , Katsuyoshi Kitai , Tadaaki Isobe , Shigeko Hashimoto , Yasuhiro Inagami , Yoshiko Tamaki
IPC分类号： G06F13/18 , G06F13/40 , G06F13/00
CPC分类号： G06F13/4027 , G06F13/18
摘要： In a multiprocessor computer system, individual vector processors are provided with priority switching signal control circuits, respectively, and a storage control unit incorporating a priority control circuit. Priority bit information is provided for priority circuits incorporated in the storage control unit. Paths for priority switching signal issued in accordance with a number of requests as generated and types of instruction generating the requests are provided between the priority switching signal control circuits and the priority control circuit of the storage control unit, while paths for the priority switching signal as generated are provided between the priority control circuit and all the priority circuits.
摘要翻译：在多处理器计算机系统中，分别向各个矢量处理器提供优先切换信号控制电路，以及包含优先控制电路的存储控制单元。为存储控制单元中包含的优先级电路提供优先级位信息。在优先切换信号控制电路和存储控制单元的优先控制电路之间，设置根据产生的请求数量和产生请求的指令的类型发出的优先切换信号的路径，而优先切换信号的路径为生成的优先级控制电路和所有优先级电路之间。

3. 发明授权

US5437043A Information processing apparatus having a register file used interchangeably both as scalar registers of register windows and as vector registers 失效
标题翻译：具有可互换使用的寄存器文件作为寄存器窗口的标量寄存器和向量寄存器的信息处理装置
公开(公告)号：US5437043A
公开(公告)日：1995-07-25
申请号：US979327
申请日：1992-11-20
申请人： Hiroaki Fujii , Naoki Hamanaka , Teruo Tanaka , Yasuhiro Inagami , Yoshiko Tamaki
发明人： Hiroaki Fujii , Naoki Hamanaka , Teruo Tanaka , Yasuhiro Inagami , Yoshiko Tamaki
IPC分类号： G06F9/30 , G06F9/318 , G06F9/26 , G06F9/28 , G06F9/40
CPC分类号： G06F9/30127 , G06F9/30112 , G06F9/30138
摘要： An arrangement having a register file having registers greater in number than those which are designated by an instruction, a pipeline ALU, a current window pointer and window number modifier operating in a register window mode, an element counter and address counter operating in a vector register mode, and register determining circuits for determining physical register numbers from the register numbers designated by an instruction in one of the two modes. Each register determining circuit has a first register determining circuit using an output of the window number modifier, for using the register file as a register window configuration, and a second register determining circuit using an output of the element counter, for using the register file as a vector register configuration. Physical registers of the register file are used as scalar registers in the register window mode, and used as vector registers in the vector register modes.
摘要翻译：一种具有寄存器文件的布置，其寄存器数量大于由指令指定的寄存器文件，流水线ALU，以寄存器窗口模式操作的当前窗口指针和窗口编号修改器，在向量寄存器中操作的元件计数器和地址计数器模式和寄存器确定电路，用于根据由两种模式之一指令指定的寄存器号来确定物理寄存器号。每个寄存器确定电路具有使用窗口编号修改器的输出的第一寄存器确定电路，用于使用寄存器文件作为寄存器窗口配置，以及使用元件计数器的输出的第二寄存器确定电路，用于将寄存器文件用作矢量寄存器配置。寄存器文件的物理寄存器在寄存器窗口模式下用作标量寄存器，并用作向量寄存器模式中的向量寄存器。

4. 发明授权

US5396603A Data processor having resources and execution start control for starting execution of succeeding instruction in resource before completion of preceding instruction 失效
标题翻译：数据处理器具有资源和执行开始控制，用于在完成前一指令之前开始执行资源中的后续指令
公开(公告)号：US5396603A
公开(公告)日：1995-03-07
申请号：US634810
申请日：1990-12-31
申请人： Yoshiko Tamaki , Shigeko Yazawa , Yasuhiro Inagami , Katsuyoshi Kitai
发明人： Yoshiko Tamaki , Shigeko Yazawa , Yasuhiro Inagami , Katsuyoshi Kitai
IPC分类号： G06F9/38 , G06F15/78 , G06F17/16
CPC分类号： G06F9/3836 , G06F15/8084 , G06F9/3857 , G06F9/3867
摘要： A data processor having memory requesters to execute instructions, an instruction hold unit disposed for each resource to hold an instruction being executed in the resource and instructions to be executed therein, and execution control units to cause, in a case where an execution completion report of an instruction being executed in either one of the resources is received, an instruction held in an instruction hold unit corresponding to the resource to be immediately executed, thereby successively supplying the respective resources with data items to be employed for executions of the consecutive instructions in the resources.
摘要翻译：一种具有用于执行指令的存储器请求器的数据处理器，为每个资源设置的指令保持单元，用于保存正在该资源中执行的指令以及要在其中执行的指令;以及执行控制单元，其在执行完成报告在任一资源中执行的指令被接收，指令保持单元中保持的指令与要立即执行的资源相对应，从而向相应资源依次提供要用于执行连续指令的数据项资源。

5. 发明授权

US6049839A Data processor with multiple register queues 失效
标题翻译：具有多个寄存器队列的数据处理器
公开(公告)号：US6049839A
公开(公告)日：2000-04-11
申请号：US172170
申请日：1993-12-23
申请人： Hiroaki Fujii , Yasuhiro Inagami , Shigeo Takeuchi
发明人： Hiroaki Fujii , Yasuhiro Inagami , Shigeo Takeuchi
IPC分类号： G06F9/34 , G06F9/30 , G06F9/38 , G06F13/00
CPC分类号： G06F9/30134 , G06F9/384
摘要： A data processor includes a register group having registers of the number larger than the number of registers which can be designated by a register specifier field of an instruction. The register group consists of a plurality of register queues with respect to logical register numbers designated in the instruction, each register queue including a plurality of physical registers. In the data processor, a physical register number forming section is provided for converting the logical register number to a physical register number in the register queue corresponding to the logical register number, by using queue control information designated in the register specifier field and read/write information decided by the kind of the instruction and the position of the register specifier field in the instruction.
摘要翻译：数据处理器包括具有比可由指令的寄存器说明符字段指定的寄存器数量大的寄存器的寄存器组。寄存器组包括相对于指令中指定的逻辑寄存器号的多个寄存器队列，每个寄存器队列包括多个物理寄存器。在数据处理器中，提供物理寄存器号码形成部分，用于通过使用寄存器说明符字段中指定的队列控制信息和读取/写入将逻辑寄存器号码转换为对应于逻辑寄存器号码的寄存器队列中的物理寄存器号码指令种类决定的信息和指令中寄存器说明符字段的位置。

6. 发明授权

US5349653A Apparatus for converting parallel bits of an electrical data signal into serial bits of an optical data signal utilizing an optical time delay 失效
标题翻译：用于使用光时延将电数据信号的并行位转换为光数据信号的串行位的装置
公开(公告)号：US5349653A
公开(公告)日：1994-09-20
申请号：US775030
申请日：1991-10-11
申请人： Hiroshi Kurokawa , Yasushi Takahashi , Yasuhiro Inagami
发明人： Hiroshi Kurokawa , Yasushi Takahashi , Yasuhiro Inagami
IPC分类号： H03M9/00 , G06F5/00
CPC分类号： H03M9/00
摘要： A plurality of electric data signals representing parallel data bits are applied to a plurality of gates or control terminals on-off controlling optical switches, respectively. A single pulsed synchronizing signal is distributed to input terminals of the plurality of gates or the optical switches. Synchronizing signals, which have passed through gates or optical switches, which are in an ON state, among the plurality of gates or the optical switches are coupled to synchronize finally an optical signal. In this way a serial optical pulsed output signal can be obtained by utilizing optical delay in a process for distributing the synchronizing signals or a process for coupling the synchronizing signals.
摘要翻译：表示并行数据位的多个电数据信号分别被施加到多个门或控制端开关控制光开关。单个脉冲同步信号被分配到多个门或光开关的输入端。多个门或光开关之中已经通过栅极或光开关的处于ON状态的同步信号被耦合以使光信号最终同步。以这种方式，可以通过在用于分配同步信号的处理中利用光学延迟或者用于耦合同步信号的处理来获得串行光脉冲输出信号。

7. 发明授权

US4910667A Vector processor with vector buffer memory for read or write of vector data between vector storage and operation unit 失效
标题翻译：矢量处理器，带矢量缓冲存储器，用于在矢量存储和操作单元之间读取或写入矢量数据
公开(公告)号：US4910667A
公开(公告)日：1990-03-20
申请号：US184788
申请日：1988-04-22
申请人： Teruo Tanaka , Koichiro Omoda , Yasuhiro Inagami , Takayuki Nakagawa , Mamoru Sugie , Shigeo Nagashima
发明人： Teruo Tanaka , Koichiro Omoda , Yasuhiro Inagami , Takayuki Nakagawa , Mamoru Sugie , Shigeo Nagashima
IPC分类号： G06F12/08 , G06F15/78 , G06F17/16
CPC分类号： G06F15/8053
摘要： In a vector processor having vector registers, a vector buffer storage for temporarily storing vector data is arranged closer to the vector registers than to a main storage, and a vector buffer storage control including an identification storage for storing identification information of the vector data stored at storage locations of the buffer storage and a check circuit for checking if the vector data identification information is in the identificatgion storage is provided. The vector buffer storage control checks if the identification information of the vector data designated by a vector data fetch instruction for the main storage is in the indentification storage, and if it is in the identification storage, it fetches the vector data from the buffer storage and transfers it to the vector register, and if it is not in the identification storage, it instructs to fetch the vector data from the main storage, transfers the vector data fetched from the main storage to the vector register and stores it into the buffer storage.
摘要翻译：在具有向量寄存器的向量处理器中，用于临时存储向量数据的向量缓冲存储器比向主存储器靠近向量寄存器布置，并且向量缓冲器存储控制包括用于存储存储在提供缓冲存储器的存储位置和用于检查矢量数据识别信息是否在识别存储器中的检查电路。向量缓冲存储控制检查由主存储器的矢量数据获取指令指定的矢量数据的识别信息是否在识别存储器中，并且如果它在识别存储器中，则从缓冲存储器中取出向量数据，将其传送到向量寄存器，如果不在识别存储器中，则指示从主存储器获取向量数据，将从主存储器获取的向量数据传送到向量寄存器，并将其存储到缓冲存储器中。

8. 发明授权

US4881168A Vector processor with vector data compression/expansion capability 失效
标题翻译：矢量处理器具有矢量数据压缩/扩展能力
公开(公告)号：US4881168A
公开(公告)日：1989-11-14
申请号：US034950
申请日：1987-04-06
申请人： Yasuhiro Inagami , Takayuki Nakagawa , Yoshiko Tamaki , Shigeo Nagashima
发明人： Yasuhiro Inagami , Takayuki Nakagawa , Yoshiko Tamaki , Shigeo Nagashima
IPC分类号： G06F17/16 , G06F15/78 , G06T9/00
CPC分类号： G06F9/3824 , G06F15/8084 , G06F9/30043 , G06T9/008
摘要： A vector processor has a memory for storing vector data, a plurality of vector registers each capable of reading or writing plural (m) vector elements in parallel, at least one mask vector register capable of storing m mask bits in parallel, and a transfer section connected to the memory, the plurality of vector registers and the mask vector register and responsive to a store compression instruction or a load expansion instruction for transferring vector elements to or from regularly spaced address locations within the memory from or to selected storage locations of a selected vector register corresponding to valid mask bits. The transfer section includes at least one count unit connected to the mask vector register for counting a total number of valid mask bits within all of the already read out mask bits, and plural (m) access units operable concurrently and connected to the count unit and the mask vector register. Each access unit is responsive to the validity of a corresponding one within currently read out m mask bits, to a total number of valid mask bits or invalid mask bits included within the currently read m mask bits and having preceding sequential numbers of elements to that of the corresponding mask bit, and to the counted total number, and operates to generate an address of a location within the memory which holds a vector element to be transferred to a storage location corresponding to the corresponding mask bit within the selected vector register or which should receive a vector element read out from the storage location.
摘要翻译：矢量处理器具有用于存储矢量数据的存储器，能够并行地读取或写入多个（m）个矢量元素的多个矢量寄存器，能够并行存储m个掩码位的至少一个掩码向量寄存器，以及传送部分连接到存储器，多个向量寄存器和掩码向量寄存器，并且响应于存储器压缩指令或负载扩展指令，用于将存储器内的规则间隔地址位置中的向量元素传送到所选择的存储器或选定的存储位置向量寄存器对应于有效的掩码位。传送部分包括至少一个计数单元，连接到掩模向量寄存器，用于对所有已经读出的掩码位内的有效掩码位的总数进行计数;以及多个（m）个访问单元，可同时并行连接到计数单元，掩码向量寄存器。每个访问单元响应于当前读出的m个掩码位内的对应的有效值，到当前读取的m个掩码位内包括的有效屏蔽位或无效掩码位的总数，并且具有先前的顺序数目的元素对应的屏蔽位和计数的总数，并且操作以产生存储器内的位置的地址，该地址保存要传送到与所选择的向量寄存器内的对应掩码位相对应的存储位置的向量元素，或者应当接收从存储位置读出的向量元素。

9. 发明授权

US4782441A Vector processor capable of parallely executing instructions and reserving execution status order for restarting interrupted executions 失效
标题翻译：能够平行执行指令并保留执行状态顺序的矢量处理器重新启动中断的执行
公开(公告)号：US4782441A
公开(公告)日：1988-11-01
申请号：US872396
申请日：1986-06-10
申请人： Yasuhiro Inagami , Shigeo Nagashima , Koichiro Omoda , Takayuki Nakagawa , Teruo Tanaka
发明人： Yasuhiro Inagami , Shigeo Nagashima , Koichiro Omoda , Takayuki Nakagawa , Teruo Tanaka
IPC分类号： G06F9/46 , G06F9/38 , G06F9/48 , G06F15/78 , G06F17/16 , G06F9/28 , G06F7/00
CPC分类号： G06F15/8053
摘要： In a processor such as a vector processor in which a plurality of data are processed by one instruction and a plurality of instructions are parallely processed, apparatus is provided for storing, during an interruption of the program currently being executed, the instructions being executed in the conceptual order of appearance in the program of the instruction being executed, and the sequential count of the sets of data processed. The stored information is used to restart the execution of the interrupted program at the appropriate point.
摘要翻译：在其中通过一个指令处理多个数据并且多个指令并行处理的诸如矢量处理器的处理器中，提供装置，用于在当前执行的程序的中断期间存储在正在执行的指令的程序中出现的概念顺序，以及处理的数据组的顺序计数。存储的信息用于在适当的点重新启动中断的程序的执行。

10. 发明授权

US06330604B1 Exclusive control method with each node controlling issue of an exclusive use request to a shared resource, a computer system therefor and a computer system with a circuit for detecting writing of an event flag into a shared main storage 失效
标题翻译：独占控制方法，每个节点控制对共享资源的专用使用请求的问题，其计算机系统和具有用于检测将事件标志写入共享主存储器的电路的计算机系统
公开(公告)号：US06330604B1
公开(公告)日：2001-12-11
申请号：US09102812
申请日：1998-06-23
申请人： Tatsuo Higuchi , Toshiaki Tarui , Katsuyoshi Kitai , Shigeo Takeuchi , Tatsuru Toba , Machiko Asaie , Yasuhiro Inagami
发明人： Tatsuo Higuchi , Toshiaki Tarui , Katsuyoshi Kitai , Shigeo Takeuchi , Tatsuru Toba , Machiko Asaie , Yasuhiro Inagami
IPC分类号： G06F15167
CPC分类号： G06F9/52 , G06F15/17381 , H04L45/06
摘要： A computer system including a plurality of processing nodes, at least one resource provided for use by any of the processing nodes and a plurality of register sets. Each register set is provided in each of the processing nodes for storing in parallel use status information indicating whether the resource is in exclusive use status or not. The computer system can also include a plurality of request issue circuits, each being provided in each of the processing nodes, for issuing individually requests for exclusive use of the resource, a message exchanging circuit for serializing requests issued by the request issue circuits into a serialized order and broadcasting the request to all of the processing nodes in the serialized order and a plurality of status control circuits. Each status control circuit is provided in each of the processing nodes corresponding to each of the register sets to update individually a corresponding register set depending on use status information stored in the corresponding register set and each of the requests for exclusive use of the resource received at a corresponding node.
摘要翻译：一种包括多个处理节点的计算机系统，提供给任何处理节点使用的至少一个资源和多个寄存器组。在每个处理节点中提供每个寄存器组，用于并行地存储指示资源是否处于独占状态的状态信息。计算机系统还可以包括多个请求发布电路，每个请求发布电路分别设置在每个处理节点中，用于单独发出专用于资源的请求;消息交换电路，用于将请求发布电路发出的请求串行化为串行化以序列顺序向多个处理节点发送请求并将其发送给多个状态控制电路。每个状态控制电路被提供在与每个寄存器组相对应的每个处理节点中，以根据存储在相应寄存器组中的使用状态信息单独地更新对应的寄存器组，并且每个对专用的资源请求相应的节点。

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