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1. 发明授权

US6044450A Processor for VLIW instruction 失效
标题翻译：处理器用于VLIW指令
公开(公告)号：US6044450A
公开(公告)日：2000-03-28
申请号：US824486
申请日：1997-03-27
申请人： Yuji Tsushima , Yoshikazu Tanaka , Yoshiko Tamaki , Masanao Ito , Kentaro Shimada , Yonetaro Totsuka , Shigeo Nagashima
发明人： Yuji Tsushima , Yoshikazu Tanaka , Yoshiko Tamaki , Masanao Ito , Kentaro Shimada , Yonetaro Totsuka , Shigeo Nagashima
IPC分类号： G06F9/30 , G06F9/38 , G06F7/00
CPC分类号： G06F9/30025 , G06F9/30178 , G06F9/3853
摘要： Each small instruction in a VLIW instruction (long instruction) is added with the number of NOP instructions which succeed the small instruction, and these NOP instructions are deleted from the succeeding long instruction. A plurality of long instructions are therefore time-compressed. Thereafter, a plurality of small instructions in each long instruction are divided into a plurality of groups, and a combination of operation codes (OP codes) of small instructions in each group is replaced by a group code to generate a compressed, grouped instruction. Each long instruction is therefore space-compressed. An instruction expanding unit has an instruction expanding circuit for each grouped instruction. Each instruction expanding circuit expands one grouped instruction in a long instruction, generates a group of small instructions represented by the grouped instruction, and supplies the group of generated small instructions to respective function units via a decode unit. In this case, each instruction expanding circuit supplies after each small instruction NOP instructions same in number as that designated by a NOP number associated with each small instruction in this grouped instruction.
摘要翻译： VLIW指令（长指令）中的每个小指令都加上小指令成功的NOP指令数，并从后续长指令中删除这些NOP指令。因此，多个长指令被时间压缩。此后，每个长指令中的多个小指令被分成多个组，并且组中的小指令的操作码（OP代码）的组合被组代码替换以生成压缩的分组指令。因此，每个长指令都是空间压缩的。指令扩展单元具有用于每个分组指令的指令扩展电路。每个指令扩展电路在长指令中扩展一个分组指令，生成由分组指令表示的一组小指令，并且经由解码单元将所生成的小指令组提供给各个功能单元。在这种情况下，每个指令扩展电路在与分组指令中的每个小指令相关联的NOP号指定的每个小指令NOP指令之后提供数量相同的每个指令扩展电路。

2. 发明授权

US5465380A Data transfer method of transferring data between programs of a same program group in different processors using unique identifiers of the programs 失效
标题翻译：使用程序的唯一标识符在不同处理器中的相同程序组的程序之间传送数据的数据传输方法
公开(公告)号：US5465380A
公开(公告)日：1995-11-07
申请号：US222949
申请日：1994-04-04
申请人： Naoki Hamanaka , Teruo Tanaka , Koichiro Omoda , Shigeo Nagashima
发明人： Naoki Hamanaka , Teruo Tanaka , Koichiro Omoda , Shigeo Nagashima
IPC分类号： G06F9/46 , G06F15/16 , G06F9/00
CPC分类号： G06F9/54 , G06F15/161
摘要： A parallel processor system which includes a plurality of processors each for executing at least one of a plurality of mutually associated programs and a transfer circuit. The transfer circuit is connected to the processors, and is provided for transferring the data outputted from any one of the programs during execution of one program by any one of the processors to other processors to which a receiving program is allotted. The transfer operation is performed in response to a program identification code outputted during execution of the one program by one processor to identify the receiving program.
摘要翻译：一种并行处理器系统，其包括多个处理器，每个处理器用于执行多个相互关联的程序和传送电路中的至少一个。传送电路连接到处理器，并且被提供用于将由任何一个处理器执行一个程序期间的任何一个程序输出的数据传送到分配了接收程序的其他处理器。响应于由一个处理器执行一个程序期间输出的节目识别码来执行传送操作以识别接收节目。

3. 发明授权

US5043873A Method of parallel processing for avoiding competition control problems and data up dating problems common in shared memory systems 失效
标题翻译：并行处理方法，用于避免共享内存系统中常见的竞争控制问题和数据上传问题
公开(公告)号：US5043873A
公开(公告)日：1991-08-27
申请号：US395444
申请日：1989-08-17
申请人： Akira Muramatsu , Kousuke Sakoda , Ikuo Yoshihara , Kazuo Nakao , Makoto Nohmi , Naoki Hamanaka , Shigeo Nagashima , Teruo Tanaka
发明人： Akira Muramatsu , Kousuke Sakoda , Ikuo Yoshihara , Kazuo Nakao , Makoto Nohmi , Naoki Hamanaka , Shigeo Nagashima , Teruo Tanaka
IPC分类号： G06F9/45 , G06F9/50
CPC分类号： G06F9/5016 , G06F8/451 , G06F2209/484
摘要： A plurality of elemental processors each include a local memory for storing data and task programs and an execution section for executing the task programs. A communications section transfers data among the processors. In a method of parallel processing with these elemental processors, a task program is executed in one of the processors. A detection operation is conducted to determine whether the data from the task program is to be copied to the local memories of other processors. The detection is based on predetermined information which is stored in the local memory of the processor which performs the task program and indicates which of the other processors will need the data. The detection also determines which of the other processors that will require access to the data are ready to receive the data. Concurrently and in parallel with the execution of the task program, the data is transmitted to each of the elemental processors that are awaiting the data with only a write instruction and without any communications instruction.

4. 发明授权

US4992936A Address translation method and apparatus therefor 失效
标题翻译：地址转换方法及其设备
公开(公告)号：US4992936A
公开(公告)日：1991-02-12
申请号：US269058
申请日：1988-11-09
申请人： Hisashi Katada , Yasuhiro Inagami , Yoshiko Tamaki , Shigeo Nagashima
发明人： Hisashi Katada , Yasuhiro Inagami , Yoshiko Tamaki , Shigeo Nagashima
IPC分类号： G06F12/02 , G06F12/10
CPC分类号： G06F12/1009 , G06F2212/652
摘要： In a method and apparatus wherein a logical address of a main storage designated by a program is translated into a real address: an address translation table for each of a plurality of address translation sizes is prepared; the logical address designated by the program is fetched; an entry of an address translation table whose address translation size is larger than those of the other address translation tables among the plurality of address translation sizes is first identified based on the fetched logical address; a first information on an address translation size validity included in the first indentified entry is checked; address translation in units of translation size of the address translation table including the first identified entry is performed when the first information indicates valid; when the first information indicates invalid, an entry of an address translation table whose address translation size is next smaller than that of the address translation table including the first identified entry is second identified, based on the top address of the address translation table including the second identified entry and based on the fetched logical address; and address translation is further performed returning back to the above-mentioned step where the first information on the address translation size included in the first identified entry is checked.
摘要翻译：在将由程序指定的主存储器的逻辑地址转换为实际地址的方法和装置中，准备多个地址转换大小中的每一个的地址转换表; 获取程序指定的逻辑地址; 首先根据获取的逻辑地址来识别其地址转换大小大于多个地址转换大小中的其他地址转换表的地址转换表的条目; 检查包含在第一识别条目中的地址转换大小有效性的第一信息; 当第一信息表示有效时，执行包括第一识别条目的地址转换表的翻译大小单位的地址转换; 当第一信息指示无效时，基于包括第二信息的地址转换表的顶部地址，第二识别地址转换大小接下来小于包括第一标识条目的地址转换表的地址转换大小的条目的条目识别的条目并基于获取的逻辑地址; 进一步执行地址转换，返回上述步骤，其中检查包含在第一识别条目中的地址转换大小的第一信息。

5. 发明授权

US4951193A Parallel computer with distributed shared memories and distributed task activating circuits 失效
标题翻译：具有分布式共享存储器和分布式任务激活电路的并行计算机
公开(公告)号：US4951193A
公开(公告)日：1990-08-21
申请号：US85646
申请日：1987-08-14
申请人： Akira Muramatsu , Kousuke Sakoda , Ikuo Yoshihara , Kazuo Nakao , Makoto Nohmi , Naoki Hamanaka , Shigeo Nagashima , Teruo Tanaka
发明人： Akira Muramatsu , Kousuke Sakoda , Ikuo Yoshihara , Kazuo Nakao , Makoto Nohmi , Naoki Hamanaka , Shigeo Nagashima , Teruo Tanaka
IPC分类号： G06F9/45 , G06F9/50
CPC分类号： G06F9/5016 , G06F8/451 , G06F2209/484
摘要： In accessing a memory, each element processor executes a program constructed so as to designate an address belonging to a predetermined local address area for each element processor. When a memory write instruction is executed by an element processor, it is detected if the memory address designated by the instruction coincides with a predetermined address. If detected, a predetermined address belonging to a local address space of another element processor and assigned to the first-mentioned predetermined address, and the data written in response to the write instruction, are sent to the other element processor to instruct the data to be written therein as a copy data. A next task to be executed is decided independently for each element processor.
摘要翻译：在访问存储器时，每个元件处理器执行构造成为每个元件处理器指定属于预定本地地址区域的地址的程序。当由元件处理器执行存储器写入指令时，检测由指令指定的存储器地址是否与预定地址一致。如果检测到，则属于另一元件处理器的本地地址空间并分配给首先提到的预定地址的预定地址以及响应写指令写入的数据被发送到另一元件处理器以指示数据为在其中写入作为复制数据。对于每个元件处理器独立地确定要执行的下一个任务。

6. 发明授权

US4760545A Vector processing apparatus including vector registers having selectively accessible storage locations 失效
标题翻译：矢量处理装置包括具有选择性可访问的存储位置的向量寄存器
公开(公告)号：US4760545A
公开(公告)日：1988-07-26
申请号：US684786
申请日：1984-12-21
申请人： Yasuhiro Inagami , Shigeo Nagashima
发明人： Yasuhiro Inagami , Shigeo Nagashima
IPC分类号： G06F9/38 , G06F12/00 , G06F13/16 , G06F15/78 , G06F17/16 , G06F15/347
CPC分类号： G06F15/8084
摘要： A vector instruction which designates calculation of vector data or vector data transfer between vector registers and the main memory, is arranged in such a way as to specify an element in the vector register from which the read/write operation is to be commenced, in order to make it possible to start the reading or writing of the vector data stored in the vector register from any desired element, thereby allowing a partial reference to the array data to be made on the vector register. Further, a vector instruction, which designates the vector data transfer between each vector register and the main memory, is arranged in such a way as to be able to specify the number of vector data elements to be transferred, thereby allowing transfer of elements requisite and adequate for a plurality of partial references on the vector register.
摘要翻译：指定向量数据或向量寄存器与主存储器之间的矢量数据传送的计算的矢量指令以这样的方式被布置，以便指定要从其开始读/写操作的向量寄存器中的元素使得可以从任何期望的元素开始读取或写入存储在向量寄存器中的向量数据，从而允许对向量寄存器进行阵列数据的部分引用。此外，指定在每个向量寄存器和主存储器之间的向量数据传送的向量指令被布置成能够指定要传送的向量数据元素的数量，从而允许传送要素和对于向量寄存器上的多个部分引用是足够的。

7. 发明授权

US4712175A Data processing apparatus 失效
标题翻译：数据处理装置
公开(公告)号：US4712175A
公开(公告)日：1987-12-08
申请号：US633981
申请日：1984-07-24
申请人： Shunichi Torii , Shigeo Nagashima , Koichiro Omoda
发明人： Shunichi Torii , Shigeo Nagashima , Koichiro Omoda
IPC分类号： G06F17/16 , G06F9/38 , G06F15/78 , G06F15/347 , G06F15/16
CPC分类号： G06F15/8076 , G06F9/3885
摘要： A data processing apparatus comprises a plurality of sub-systems each including at least one arithmetic unit, a plurality of registers, a first selector for receiving vector data and selectively outputting the input data to the registers, and a second selector for receiving the vector data from the registers and selectively outputting the input data to a plurality of output lines. The data output of the arithmetic unit in each sub-system is supplied to the first selector in the same sub-system and the first selector in another sub-system, and the arithmetic unit in each sub-system receives the output data from the second selector in the same sub-system. The data output from the second selector in at least one sub-system is supplied to a main storage unit, and the data output from the main storage unit is supplied to the first selector in at least one sub-system.
摘要翻译：数据处理装置包括多个子系统，每个子系统包括至少一个算术单元，多个寄存器，用于接收向量数据的第一选择器，并且将输入数据选择性地输出到寄存器;以及第二选择器，用于接收向量数据从寄存器中选择性地将输入数据输出到多条输出线。每个子系统中的算术单元的数据输出被提供给同一子系统中的第一选择器和另一子系统中的第一选择器，并且每个子系统中的算术单元从第二子系统接收输出数据选择器在同一子系统中。在至少一个子系统中从第二选择器输出的数据被提供给主存储单元，并且从主存储单元输出的数据在至少一个子系统中提供给第一选择器。

8. 发明授权

US4004278A System for switching multiple virtual spaces 失效
标题翻译：用于切换多个虚拟空间的系统
公开(公告)号：US4004278A
公开(公告)日：1977-01-18
申请号：US452138
申请日：1974-03-18
申请人： Shigeo Nagashima
发明人： Shigeo Nagashima
IPC分类号： G06F12/10 , G06F9/20
CPC分类号： G06F12/1036
摘要： In a virtual memory system capable of embodying therein multiple virtual spaces used in a switching mode and having a high speed memory for storing address sets each including a virtual address of the virtual space and a real address of a real space corresponding to the virtual address and indicators for setting the validity or invalidity state of the corresponding address sets, a switching system such that when the multiple virtual spaces are switched, the virtual address in the addressed address set is compared with a special address stored in a register by a comparator, and the indicator corresponding to the addressed address set is set to the invalidity state when the result of comparison fulfills a predetermined condition.
摘要翻译：在能够体现在切换模式中使用的多个虚拟空间并且具有高速存储器的虚拟存储器系统中，所述高速存储器用于存储每个包括虚拟空间的虚拟地址和与该虚拟地址相对应的真实空间的实际地址的地址集，以及用于设置相应地址集的有效性或无效状态的指示符，切换系统，使得当切换多个虚拟空间时，将寻址地址集中的虚拟地址与比较器存储在寄存器中的专用地址进行比较，以及当比较结果满足预定条件时，对应于寻址地址集的指示符被设置为无效状态。

9. 发明授权

US08467642B2 Waveguide type optical device 有权
标题翻译：波导型光学器件
公开(公告)号：US08467642B2
公开(公告)日：2013-06-18
申请号：US12918406
申请日：2009-02-19
申请人： Daisuke Ogawa , Takashi Saida , Yuji Moriya , Shigeo Nagashima , Yasuyuki Inoue , Shin Kamei
发明人： Daisuke Ogawa , Takashi Saida , Yuji Moriya , Shigeo Nagashima , Yasuyuki Inoue , Shin Kamei
IPC分类号： G02B6/26 , G02B6/42 , G02B6/34
CPC分类号： G02B6/12026 , G02B6/12011 , G02B6/12014 , G02B6/12023
摘要： An arrayed waveguide grating optical multiplexer/demultiplexer according to the present invention including an input channel waveguide, an input slab waveguide, an arrayed waveguide, a polarization dependence eliminating means, an output slab waveguide, a temperature compensating means, and an output channel waveguide is characterized in that the temperature compensating means compensates for the temperature dependence of the optical path lengths in the channel waveguides of the arrayed waveguide, and the polarization dependence eliminating means eliminates the temperature dependence and the polarization dependence of the arrayed waveguide grating optical multiplexer/demultiplexer at the same time.
摘要翻译：根据本发明的阵列波导光栅光复用器/解复用器包括输入通道波导，输入平板波导，阵列波导，偏振相关性消除装置，输出平板波导，温度补偿装置和输出通道波导其特征在于，温度补偿装置补偿阵列波导的通道波导中光路长度的温度依赖性，并且偏振相关性消除装置消除阵列波导光栅光复用器/解复用器的温度依赖性和偏振度依赖性同一时间。

10. 发明授权

US5339396A Interconnection network and crossbar switch for the same 失效
标题翻译：互联网和交叉开关为一体
公开(公告)号：US5339396A
公开(公告)日：1994-08-16
申请号：US119601
申请日：1993-09-10
申请人： Akira Muramatsu , Ikuo Yoshihara , Kazuo Nakao , Takehisa Hayashi , Teruo Tanaka , Shigeo Nagashima
发明人： Akira Muramatsu , Ikuo Yoshihara , Kazuo Nakao , Takehisa Hayashi , Teruo Tanaka , Shigeo Nagashima
IPC分类号： G06F13/40 , G06F15/173 , G06F13/00
CPC分类号： G06F15/17375 , G06F13/4022 , G06F15/17381
摘要： In a parallel computer including L=n.sub.1 x n.sub.2 x - - - x n.sub.N processor element or external devices (hereafter represented by processor elements), an interconnection network of processor elements using L x (1/n.sub.1 +1/n.sub.2 +- - - +1/n.sub.N) crossbar switches in total comprises N dimensional lattice coordinates (i.sub.1, i.sub.2, - - - , i.sub.N) , 0.ltoreq.i.sub.1 .ltoreq.n.sub.1-1, 0.ltoreq.i.sub.2 .ltoreq.n.sub.2-1, - - - , 0.ltoreq.i.sub.n .ltoreq.n.sub.N-1 given to each processor element as the processor element number, crossbar switches for decoding a dimensional field in a processor element number having specific position and length depending upon the number of lattice points of a particular dimension and for performing the switching operation with regard to the dimension, interconnection of n.sub.k processor elements having processor element numbers, which are different only in the k-th dimensional coordinate for arbitrary k, i.e., having processor element numbers ##EQU1## by using one of the crossbar switches, each of the crossbar switches having n.sub.k inputs and n.sub.k outputs, and the interconnection performed with respect to all (L/n.sub.k sets) of coordinates(i.sub.1, i.sub.2, - - - , n.sub.k-1, n.sub.k+1, - - - , i.sub.N)of N-1 dimensional subspace excluding the k-th dimension, the interconnection being further performed for all values of k (1.ltoreq.k.ltoreq.N).
摘要翻译：在包括L = n 1 x n 2 x - - - x n N个处理器元件或者外部设备（以下由处理器元件表示）的并行计算机中，使用L x（1 / n1 + 1 / n2 + - - + 1 / nN）交叉开关总共包括N维网格坐标（i1，i2，...，iN），0 （ i1，i2，...，1，...，iN）。。。（i1，i2，...，nk-1，...，iN）通过使用一个交叉开关，每个交叉开关具有nk个输入和nk个输出，并且相对于所有（L / nk组）除了第k维之外的N-1维子空间的坐标（i1，i2， - - ，nk-1，nk + 1， - - ，iN），对于 k（1

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