专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4881168A Vector processor with vector data compression/expansion capability 失效
标题翻译：矢量处理器具有矢量数据压缩/扩展能力
公开(公告)号：US4881168A
公开(公告)日：1989-11-14
申请号：US034950
申请日：1987-04-06
申请人： Yasuhiro Inagami , Takayuki Nakagawa , Yoshiko Tamaki , Shigeo Nagashima
发明人： Yasuhiro Inagami , Takayuki Nakagawa , Yoshiko Tamaki , Shigeo Nagashima
IPC分类号： G06F17/16 , G06F15/78 , G06T9/00
CPC分类号： G06F9/3824 , G06F15/8084 , G06F9/30043 , G06T9/008
摘要： A vector processor has a memory for storing vector data, a plurality of vector registers each capable of reading or writing plural (m) vector elements in parallel, at least one mask vector register capable of storing m mask bits in parallel, and a transfer section connected to the memory, the plurality of vector registers and the mask vector register and responsive to a store compression instruction or a load expansion instruction for transferring vector elements to or from regularly spaced address locations within the memory from or to selected storage locations of a selected vector register corresponding to valid mask bits. The transfer section includes at least one count unit connected to the mask vector register for counting a total number of valid mask bits within all of the already read out mask bits, and plural (m) access units operable concurrently and connected to the count unit and the mask vector register. Each access unit is responsive to the validity of a corresponding one within currently read out m mask bits, to a total number of valid mask bits or invalid mask bits included within the currently read m mask bits and having preceding sequential numbers of elements to that of the corresponding mask bit, and to the counted total number, and operates to generate an address of a location within the memory which holds a vector element to be transferred to a storage location corresponding to the corresponding mask bit within the selected vector register or which should receive a vector element read out from the storage location.
摘要翻译：矢量处理器具有用于存储矢量数据的存储器，能够并行地读取或写入多个（m）个矢量元素的多个矢量寄存器，能够并行存储m个掩码位的至少一个掩码向量寄存器，以及传送部分连接到存储器，多个向量寄存器和掩码向量寄存器，并且响应于存储器压缩指令或负载扩展指令，用于将存储器内的规则间隔地址位置中的向量元素传送到所选择的存储器或选定的存储位置向量寄存器对应于有效的掩码位。传送部分包括至少一个计数单元，连接到掩模向量寄存器，用于对所有已经读出的掩码位内的有效掩码位的总数进行计数;以及多个（m）个访问单元，可同时并行连接到计数单元，掩码向量寄存器。每个访问单元响应于当前读出的m个掩码位内的对应的有效值，到当前读取的m个掩码位内包括的有效屏蔽位或无效掩码位的总数，并且具有先前的顺序数目的元素对应的屏蔽位和计数的总数，并且操作以产生存储器内的位置的地址，该地址保存要传送到与所选择的向量寄存器内的对应掩码位相对应的存储位置的向量元素，或者应当接收从存储位置读出的向量元素。

2. 发明授权

US4992936A Address translation method and apparatus therefor 失效
标题翻译：地址转换方法及其设备
公开(公告)号：US4992936A
公开(公告)日：1991-02-12
申请号：US269058
申请日：1988-11-09
申请人： Hisashi Katada , Yasuhiro Inagami , Yoshiko Tamaki , Shigeo Nagashima
发明人： Hisashi Katada , Yasuhiro Inagami , Yoshiko Tamaki , Shigeo Nagashima
IPC分类号： G06F12/02 , G06F12/10
CPC分类号： G06F12/1009 , G06F2212/652
摘要： In a method and apparatus wherein a logical address of a main storage designated by a program is translated into a real address: an address translation table for each of a plurality of address translation sizes is prepared; the logical address designated by the program is fetched; an entry of an address translation table whose address translation size is larger than those of the other address translation tables among the plurality of address translation sizes is first identified based on the fetched logical address; a first information on an address translation size validity included in the first indentified entry is checked; address translation in units of translation size of the address translation table including the first identified entry is performed when the first information indicates valid; when the first information indicates invalid, an entry of an address translation table whose address translation size is next smaller than that of the address translation table including the first identified entry is second identified, based on the top address of the address translation table including the second identified entry and based on the fetched logical address; and address translation is further performed returning back to the above-mentioned step where the first information on the address translation size included in the first identified entry is checked.
摘要翻译：在将由程序指定的主存储器的逻辑地址转换为实际地址的方法和装置中，准备多个地址转换大小中的每一个的地址转换表; 获取程序指定的逻辑地址; 首先根据获取的逻辑地址来识别其地址转换大小大于多个地址转换大小中的其他地址转换表的地址转换表的条目; 检查包含在第一识别条目中的地址转换大小有效性的第一信息; 当第一信息表示有效时，执行包括第一识别条目的地址转换表的翻译大小单位的地址转换; 当第一信息指示无效时，基于包括第二信息的地址转换表的顶部地址，第二识别地址转换大小接下来小于包括第一标识条目的地址转换表的地址转换大小的条目的条目识别的条目并基于获取的逻辑地址; 进一步执行地址转换，返回上述步骤，其中检查包含在第一识别条目中的地址转换大小的第一信息。

3. 发明授权

US5506980A Method and apparatus for parallel processing of a large data array utilizing a shared auxiliary memory 失效
标题翻译：利用共享辅助存储器并行处理大数据阵列的方法和装置
公开(公告)号：US5506980A
公开(公告)日：1996-04-09
申请号：US964845
申请日：1992-10-22
申请人： Yasuhiro Inagami , Yoshiko Tamaki , Katsuyoshi Kitai , Teruo Tanaka , Tadayuki Sakakibara
发明人： Yasuhiro Inagami , Yoshiko Tamaki , Katsuyoshi Kitai , Teruo Tanaka , Tadayuki Sakakibara
IPC分类号： G06F15/173 , G06F12/00 , G06F13/00
CPC分类号： G06F15/17368
摘要： In a multiprocessor system having a plurality of main memories and a shared extended memory, each main memory is associated with an extended memory partial write control. When an extended memory partial write instruction is issued, tag information identifying updated portions of main memory data is transferred to the associated extended memory partial write control along with the main memory data. Each time a subblock of the main memory data arrives, the extended memory partial write control performs a partial write operation to substitute those portions of the main memory data which are identified by the tag information for the corresponding portions of a data subblock in a specified extended memory area. During this partial write operation, that specified extended memory area is kept locked.
摘要翻译：在具有多个主存储器和共享扩展存储器的多处理器系统中，每个主存储器与扩展存储器部分写入控制相关联。当发出扩展存储器部分写入指令时，识别主存储器数据的更新部分的标签信息与主存储器数据一起传送到相关联的扩展存储器部分写入控制。每当主存储器数据的子块到达时，扩展存储器部分写入控制执行部分写入操作，以将由标签信息识别的主存储器数据的那些部分替换为指定扩展中的数据子块的对应部分记忆区。在该部分写入操作期间，指定的扩展内存区域被保持锁定。

4. 发明授权

US5392443A Vector processor with a memory assigned with skewed addresses adapted for concurrent fetching of a number of vector elements belonging to the same vector data 失效
标题翻译：矢量处理器具有分配了倾斜地址的存储器，适用于并发取出属于相同向量数据的多个向量元素
公开(公告)号：US5392443A
公开(公告)日：1995-02-21
申请号：US855056
申请日：1992-03-19
申请人： Tadayuki Sakakibara , Katsuyoshi Kitai , Yasuhiro Inagami , Yoshiko Tamaki , Teruo Tanaka , Tadaaki Isobe , Shigeko Yazawa , Masanao Ito
发明人： Tadayuki Sakakibara , Katsuyoshi Kitai , Yasuhiro Inagami , Yoshiko Tamaki , Teruo Tanaka , Tadaaki Isobe , Shigeko Yazawa , Masanao Ito
IPC分类号： G06F12/06 , G06F15/78 , G06F15/16
CPC分类号： G06F15/8076 , G06F12/0607
摘要： A plurality of storage control units are employed in the storage control unit section; moreover, two requester modules are adopted in association with these storage control units. Each memory module is constituted with as many access bank groups as there are storage control units. The access bank groups operate in concurrent fashion and are accessible from any one of the storage control units. In the element assignment, a plurality of request control units in each requester module and a plurality of vector data controllers in each vector register unit are respectively assigned with serial numbers beginning from zero. For a vector data controller, a number assigned thereto is divided by the request module count to attain a remainder such that the vector data controller is assigned to a request module having a number identical to the value of the remainder. Furthermore, a request queue is disposed at a stage preceding each priority unit and a request send-out unit is arranged to store therein a state of the request queue and to control a request transmission from each request control unit. Addresses are assigned to the respective memory modules, bank groups, and banks according to skew schemes respectively suitable therefor.
摘要翻译：在存储控制单元部分中采用多个存储控制单元; 此外，与这些存储控制单元相关联地采用两个请求者模块。每个存储器模块由与存储控制单元一样多的存取组组构成。访问存储组以并行方式操作，并且可以从任何一个存储控制单元访问。在元素分配中，每个请求者模块中的多个请求控制单元和每个向量寄存器单元中的多个向量数据控制器分别被分配从零开始的序列号。对于矢量数据控制器，分配给它的数字被请求模块计数除以获得余数，使得矢量数据控制器被分配给具有与其余值相同数目的请求模块。此外，请求队列设置在每个优先级单元之前的阶段，并且请求发送单元被布置为在其中存储请求队列的状态并且控制来自每个请求控制单元的请求传输。根据分别适合的偏移方案将地址分配给相应的存储器模块，存储体组和存储体。

5. 发明授权

US5857110A Priority control with concurrent switching of priorities of vector processors, for plural priority circuits for memory modules shared by the vector processors 失效
标题翻译：优先级控制，并行切换向量处理器的优先级，用于矢量处理器共享的存储器模块的多个优先级电路
公开(公告)号：US5857110A
公开(公告)日：1999-01-05
申请号：US760525
申请日：1996-12-05
申请人： Tadayuki Sakakibara , Teruo Tanaka , Katsuyoshi Kitai , Tadaaki Isobe , Shigeko Hashimoto , Yasuhiro Inagami , Yoshiko Tamaki
发明人： Tadayuki Sakakibara , Teruo Tanaka , Katsuyoshi Kitai , Tadaaki Isobe , Shigeko Hashimoto , Yasuhiro Inagami , Yoshiko Tamaki
IPC分类号： G06F13/18 , G06F13/40 , G06F13/00
CPC分类号： G06F13/4027 , G06F13/18
摘要： In a multiprocessor computer system, individual vector processors are provided with priority switching signal control circuits, respectively, and a storage control unit incorporating a priority control circuit. Priority bit information is provided for priority circuits incorporated in the storage control unit. Paths for priority switching signal issued in accordance with a number of requests as generated and types of instruction generating the requests are provided between the priority switching signal control circuits and the priority control circuit of the storage control unit, while paths for the priority switching signal as generated are provided between the priority control circuit and all the priority circuits.
摘要翻译：在多处理器计算机系统中，分别向各个矢量处理器提供优先切换信号控制电路，以及包含优先控制电路的存储控制单元。为存储控制单元中包含的优先级电路提供优先级位信息。在优先切换信号控制电路和存储控制单元的优先控制电路之间，设置根据产生的请求数量和产生请求的指令的类型发出的优先切换信号的路径，而优先切换信号的路径为生成的优先级控制电路和所有优先级电路之间。

6. 发明授权

US5437043A Information processing apparatus having a register file used interchangeably both as scalar registers of register windows and as vector registers 失效
标题翻译：具有可互换使用的寄存器文件作为寄存器窗口的标量寄存器和向量寄存器的信息处理装置
公开(公告)号：US5437043A
公开(公告)日：1995-07-25
申请号：US979327
申请日：1992-11-20
申请人： Hiroaki Fujii , Naoki Hamanaka , Teruo Tanaka , Yasuhiro Inagami , Yoshiko Tamaki
发明人： Hiroaki Fujii , Naoki Hamanaka , Teruo Tanaka , Yasuhiro Inagami , Yoshiko Tamaki
IPC分类号： G06F9/30 , G06F9/318 , G06F9/26 , G06F9/28 , G06F9/40
CPC分类号： G06F9/30127 , G06F9/30112 , G06F9/30138
摘要： An arrangement having a register file having registers greater in number than those which are designated by an instruction, a pipeline ALU, a current window pointer and window number modifier operating in a register window mode, an element counter and address counter operating in a vector register mode, and register determining circuits for determining physical register numbers from the register numbers designated by an instruction in one of the two modes. Each register determining circuit has a first register determining circuit using an output of the window number modifier, for using the register file as a register window configuration, and a second register determining circuit using an output of the element counter, for using the register file as a vector register configuration. Physical registers of the register file are used as scalar registers in the register window mode, and used as vector registers in the vector register modes.
摘要翻译：一种具有寄存器文件的布置，其寄存器数量大于由指令指定的寄存器文件，流水线ALU，以寄存器窗口模式操作的当前窗口指针和窗口编号修改器，在向量寄存器中操作的元件计数器和地址计数器模式和寄存器确定电路，用于根据由两种模式之一指令指定的寄存器号来确定物理寄存器号。每个寄存器确定电路具有使用窗口编号修改器的输出的第一寄存器确定电路，用于使用寄存器文件作为寄存器窗口配置，以及使用元件计数器的输出的第二寄存器确定电路，用于将寄存器文件用作矢量寄存器配置。寄存器文件的物理寄存器在寄存器窗口模式下用作标量寄存器，并用作向量寄存器模式中的向量寄存器。

7. 发明授权

US5396603A Data processor having resources and execution start control for starting execution of succeeding instruction in resource before completion of preceding instruction 失效
标题翻译：数据处理器具有资源和执行开始控制，用于在完成前一指令之前开始执行资源中的后续指令
公开(公告)号：US5396603A
公开(公告)日：1995-03-07
申请号：US634810
申请日：1990-12-31
申请人： Yoshiko Tamaki , Shigeko Yazawa , Yasuhiro Inagami , Katsuyoshi Kitai
发明人： Yoshiko Tamaki , Shigeko Yazawa , Yasuhiro Inagami , Katsuyoshi Kitai
IPC分类号： G06F9/38 , G06F15/78 , G06F17/16
CPC分类号： G06F9/3836 , G06F15/8084 , G06F9/3857 , G06F9/3867
摘要： A data processor having memory requesters to execute instructions, an instruction hold unit disposed for each resource to hold an instruction being executed in the resource and instructions to be executed therein, and execution control units to cause, in a case where an execution completion report of an instruction being executed in either one of the resources is received, an instruction held in an instruction hold unit corresponding to the resource to be immediately executed, thereby successively supplying the respective resources with data items to be employed for executions of the consecutive instructions in the resources.
摘要翻译：一种具有用于执行指令的存储器请求器的数据处理器，为每个资源设置的指令保持单元，用于保存正在该资源中执行的指令以及要在其中执行的指令;以及执行控制单元，其在执行完成报告在任一资源中执行的指令被接收，指令保持单元中保持的指令与要立即执行的资源相对应，从而向相应资源依次提供要用于执行连续指令的数据项资源。

8. 发明授权

US5530881A Vector processing apparatus for processing different instruction set architectures corresponding to mingled-type programs and separate-type programs 失效
标题翻译：用于处理与混合型程序和单独类型程序相对应的不同指令集架构的矢量处理装置
公开(公告)号：US5530881A
公开(公告)日：1996-06-25
申请号：US894633
申请日：1992-06-05
申请人： Yasuhiro Inagami , Teruo Tanaka , Yoshiko Tamaki , Katsuyoshi Kitai , Tadayuki Sakakibara
发明人： Yasuhiro Inagami , Teruo Tanaka , Yoshiko Tamaki , Katsuyoshi Kitai , Tadayuki Sakakibara
IPC分类号： G06F9/318 , G06F9/38 , G06F15/78 , G06F9/30
CPC分类号： G06F9/30189 , G06F15/8076 , G06F9/30036 , G06F9/3877
摘要： A vector processor system for processing vector instructions and scaler instructions fetched from storages includes a memory storage, a first and a second scaler processing units connected to the memory storage, a vector processing unit being connected to the memory storage and the two scaler processing units and for processing a vector instruction fetched from the memory storage during processing of scaler instruction/vector instruction separate type programs and a vector instruction received from the second scaler processing unit during processing of scaler instruction/vector instruction mingled type programs. More particularly, for scaler instruction/vector instruction mingled type programs, the vector processing unit receives the vector instruction from the scaler processing unit, whereas for scaler instruction/vector instruction separate type programs, the vector processing unit retrieves the vector instruction directly from the memory storage.
摘要翻译：用于处理从存储器取出的向量指令和缩放器指令的向量处理器系统包括存储器存储器，连接到存储器存储器的第一和第二定标器处理单元，连接到存储器存储器和两个定标器处理单元的矢量处理单元，以及用于在缩放器指令/向量指令混合类型程序的处理期间处理在缩放器指令/向量指令单独类型程序和从第二缩放器处理单元接收的向量指令的处理期间处理从存储器存储器获取的向量指令。更具体地说，对于缩放器指令/向量指令混合型程序，向量处理单元从缩放器处理单元接收向量指令，而对于缩放器指令/向量指令单独类型程序，向量处理单元直接从存储器检索向量指令存储。

9. 发明授权

US5440750A Information processing system capable of executing a single instruction for watching and waiting for writing of information for synchronization by another processor 失效
标题翻译：信息处理系统能够执行用于观看和等待另一个处理器同步的信息的写入的单个指令
公开(公告)号：US5440750A
公开(公告)日：1995-08-08
申请号：US643121
申请日：1991-01-18
申请人： Katsuyoshi Kitai , Yasuhiro Inagami , Yoshiko Tamaki , Yoshikazu Tanaka
发明人： Katsuyoshi Kitai , Yasuhiro Inagami , Yoshiko Tamaki , Yoshikazu Tanaka
IPC分类号： G06F15/16 , G06F9/30 , G06F9/46 , G06F11/16 , G06F15/177
CPC分类号： G06F9/52 , G06F9/30087
摘要： Each processor of a multiprocessor system which shares a main storage has a execution circuit for executing a compare and watch instruction provided for watching information for synchronization written into a main storage. When one program being executed by one of the processors issues an instruction, the circuit fetches information for synchronization from a location within the main storage designated by the instruction, compares that fetched information with another information designated by the instruction. If they do not have a specific relation, the fetching and the comparison is repeated. The circuit has a circuit for limiting the repetition with a limited number of times. The circuit further has a circuit for counting a total amount of CPU time spent for execution of plural watching instructions issued by the same program.
摘要翻译：共享主存储器的多处理器系统的每个处理器具有执行电路，用于执行提供用于观看同步信息的比较和观看指令，写入主存储器。当由一个处理器执行的一个程序发出指令时，电路从由指令指定的主存储器内的位置获取用于同步的信息，将获取的信息与该指令指定的另一个信息进行比较。如果它们没有特定关系，则重复获取和比较。该电路具有用于限制次数的重复的电路。该电路还具有用于计算用于执行由相同程序发出的多个观看指令所花费的CPU时间的总量的电路。

10. 发明授权

US5193186A Processor system for executing processes in parallel under multitask, control method of waiting for event of process 失效
标题翻译：用于在多任务下并行执行进程的处理器系统，等待进程事件的控制方法
公开(公告)号：US5193186A
公开(公告)日：1993-03-09
申请号：US647754
申请日：1991-01-30
申请人： Yoshiko Tamaki , Katsuyoshi Kitai , Yasuhiro Inagami , Yoshikazu Tanaka
发明人： Yoshiko Tamaki , Katsuyoshi Kitai , Yasuhiro Inagami , Yoshikazu Tanaka
IPC分类号： G06F15/16 , G06F9/46 , G06F9/52 , G06F15/177
CPC分类号： G06F9/52
摘要： In a processor system for executing a plurality of tasks, which respectively control execution of one or more of a plurality of processes, a method of restarting execution of a first process which is under control of a specific task being executed, after the first process is stopped to wait for occurrence of an event associated with at least one second process different from the first process, includes the steps of (a) detecting whether or not the event associated with the second process has occurred; (b) restarting the execution of the first process when it is detected that the event has occurred; (c) determining whether or not there is an execution waiting process when the event has not yet occurred; (d) executing an executing waiting process when there is any; and (e) repeating the steps (a) to (d) after execution of an execution waiting process when there is any or after the step (c) when there is not such an execution waiting process.
摘要翻译：在用于执行分别控制多个处理中的一个或多个处理的执行的多个任务的处理器系统中，在第一处理之后重新启动正在执行的特定任务正在执行的第一进程的执行的方法停止等待与与第一处理不同的至少一个第二进程相关联的事件的发生，包括以下步骤：（a）检测与第二进程相关联的事件是否已经发生; （b）当检测到事件发生时重新启动第一进程的执行; （c）当事件尚未发生时确定是否存在执行等待处理; （d）当有任何时候执行执行的等待进程; 以及（e）当在没有这样的执行等待处理时存在步骤（c）之后或之后执行执行等待处理之后，重复步骤（a）至（d）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式