专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06980385B2 Apparatus for information recording and reproducing 失效
标题翻译：用于信息记录和再现的装置
公开(公告)号：US06980385B2
公开(公告)日：2005-12-27
申请号：US10914243
申请日：2004-08-10
申请人： Takatoshi Kato , Takushi Nishiya , Hideyuki Yamakawa , Takashi Nara , Nobuaki Nakai , Hiroshi Ide , Shintaro Suzumura , Terumi Takashi
发明人： Takatoshi Kato , Takushi Nishiya , Hideyuki Yamakawa , Takashi Nara , Nobuaki Nakai , Hiroshi Ide , Shintaro Suzumura , Terumi Takashi
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , G11B20/14
CPC分类号： G11B20/10009 , G11B5/012 , G11B5/09 , G11B20/1403
摘要： In order to generate a sampling clock having a higher accuracy, a synchronous signal generating circuit is provided with a phase error detector, detecting a phase error of a read out signal digitized on the basis of FDTS algorithm, and a VCO, controlling an oscillation frequency on the basis of a phase error detected by the phase error detector, to generate a synchronous signal by the VCO. On the basis of the synchronous signal generated by the synchronous signal generating circuit, an ADC digitizes the read out signal. The digitized read out signal is then converted to binary data by a detection circuit.
摘要翻译：为了产生具有更高精度的采样时钟，同步信号发生电路设置有相位误差检测器，检测基于FDTS算法数字化的读出信号的相位误差和控制振荡频率的VCO 基于由相位误差检测器检测到的相位误差，由VCO产生同步信号。基于由同步信号发生电路产生的同步信号，ADC对读出的信号进行数字化。然后，数字化读出信号由检测电路转换成二进制数据。

2. 发明授权

US06791776B2 Apparatus for information recording and reproducing 失效
标题翻译：用于信息记录和再现的装置
公开(公告)号：US06791776B2
公开(公告)日：2004-09-14
申请号：US09793924
申请日：2001-02-28
申请人： Takatoshi Kato , Takushi Nishiya , Hideyuki Yamakawa , Takashi Nara , Nobuaki Nakai , Hiroshi Ide , Shintaro Suzumura , Terumi Takashi
发明人： Takatoshi Kato , Takushi Nishiya , Hideyuki Yamakawa , Takashi Nara , Nobuaki Nakai , Hiroshi Ide , Shintaro Suzumura , Terumi Takashi
IPC分类号： G11B509
CPC分类号： G11B20/10009 , G11B5/012 , G11B5/09 , G11B20/1403
摘要： In order to generate a sampling clock having a higher accuracy, a synchronous signal generating circuit is provided with a phase error detector, detecting a phase error of a read out signal digitized on the basis of FDTS algorithm, and a VCO, controlling an oscillation frequency on the basis of a phase error detected by the phase error detector, to generate a synchronous signal by the VCO. On the basis of the synchronous signal generated by the synchronous signal generating circuit, an ADC digitizes the read out signal. The digitized read out signal is then converted to binary data by a detection circuit.
摘要翻译：为了产生具有更高精度的采样时钟，同步信号发生电路设置有相位误差检测器，检测基于FDTS算法数字化的读出信号的相位误差和控制振荡频率的VCO 基于由相位误差检测器检测到的相位误差，由VCO产生同步信号。基于由同步信号发生电路产生的同步信号，ADC对读出的信号进行数字化。然后，数字化读出信号由检测电路转换成二进制数据。

3. 发明申请

US20050041316A1 Apparatus for information recording and reproducing 失效
公开(公告)号：US20050041316A1
公开(公告)日：2005-02-24
申请号：US10914243
申请日：2004-08-10
申请人： Takatoshi Kato , Takushi Nishiya , Hideyuki Yamakawa , Takashi Nara , Nobuaki Nakai , Hiroshi Ide , Shintaro Suzumura , Terumi Takashi
发明人： Takatoshi Kato , Takushi Nishiya , Hideyuki Yamakawa , Takashi Nara , Nobuaki Nakai , Hiroshi Ide , Shintaro Suzumura , Terumi Takashi
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , G11B20/14 , G11B20/20
CPC分类号： G11B20/10009 , G11B5/012 , G11B5/09 , G11B20/1403
摘要： In order to generate a sampling clock having a higher accuracy, a synchronous signal generating circuit is provided with a phase error detector, detecting a phase error of a read out signal digitized on the basis of FDTS algorithm, and a VCO, controlling an oscillation frequency on the basis of a phase error detected by the phase error detector, to generate a synchronous signal by the VCO. On the basis of the synchronous signal generated by the synchronous signal generating circuit, an ADC digitizes the read out signal. The digitized read out signal is then converted to binary data by a detection circuit.

4. 发明授权

US5844741A System for reproducing high-density magnetic record data with viterbi detector for generating quadripartite reproduction data 失效
标题翻译：用于产生四方再生数据的维特比检测器再现高密度磁记录数据的系统
公开(公告)号：US5844741A
公开(公告)日：1998-12-01
申请号：US548956
申请日：1995-10-27
申请人： Hideyuki Yamakawa , Takushi Nishiya , Takashi Nara , Terumi Takashi
发明人： Hideyuki Yamakawa , Takushi Nishiya , Takashi Nara , Terumi Takashi
IPC分类号： G11B20/14 , G11B5/012 , G11B5/09 , G11B20/10 , G11B20/18 , H03M13/23 , H04L25/08 , H04L25/497 , G11B5/035
CPC分类号： G11B20/10175 , G11B20/10009 , G11B5/012 , G11B5/09
摘要： A system for reproducing data recorded on a magnetic recording medium at high density is provided as a simple configuration. Quadripartite reproduction data is output from a Viterbi detection circuit to an adder, which then subtracts the quadripartite reproduction data from a signal before PR4-ML method data determination. An adder is used to perform a (1+D) process for the result. An error signal pattern detection circuit performs maximum likelihood estimation for an PR4-ML method detection error. Further, when a detected determination error matches an actual reproduction data string, a data correction circuit corrects the reproduction data string.
摘要翻译：作为简单的结构，提供了以高密度再现记录在磁记录介质上的数据的系统。四维重放数据从维特比检测电路输出到加法器，然后从PR4-ML方法数据确定之前的信号中减去四方再生数据。使用加法器对结果执行（1 + D）处理。误差信号图案检测电路对PR4-ML方法检测误差进行最大似然估计。此外，当检测到的确定错误与实际再现数据串匹配时，数据校正电路校正再现数据串。

5. 发明授权

US5677802A Phase locked loop circuit with adjustable offset characteristic, method for adjustment and apparatus 失效
标题翻译：具有可调偏移特性的锁相环电路，调节方法和装置
公开(公告)号：US5677802A
公开(公告)日：1997-10-14
申请号：US405895
申请日：1995-03-17
申请人： Eisaku Saiki , Masashi Mori , Shintaro Suzumura , Shoichi Miyazawa , Terumi Takashi
发明人： Eisaku Saiki , Masashi Mori , Shintaro Suzumura , Shoichi Miyazawa , Terumi Takashi
IPC分类号： G11B19/02 , G11B20/14 , G11B20/18 , H03L7/06 , H03L7/08 , H03M1/10 , H03M1/12 , H04L7/033 , G11B5/09 , G11B27/36
CPC分类号： G11B20/10055 , G11B19/02 , G11B20/1403 , G11B20/182
摘要： A phase locked loop circuit having a voltage controlled oscillator for generating a clock signal with a frequency determined by a voltage control signal supplied to the voltage controlled oscillator, an AD-conversion circuit for sampling a target signal with a timing determined by the clock signal and for converting sampled values into digital data, a phase locked loop control circuit for generating control data with values representing values of the digital data, and a DA-conversion circuit having an adjustable conversion characteristic for converting the control data into an analog signal and for outputting the analog signal to the voltage controlled oscillator as the voltage control signal. The adjustable conversion characteristic of the DA-conversion circuit is adjusted on the basis of an input signal having predetermined playback characteristics and when the phase locked loop circuit is part of a recording and reproducing apparatus, the input signal is a reproduced signal from a signal recorded on a recording medium.
摘要翻译：一种锁相环电路，具有用于产生由提供给压控振荡器的电压控制信号确定的频率的时钟信号的压控振荡器，用于由时钟信号确定的定时对目标信号进行采样的AD转换电路，以及用于将采样值转换为数字数据的锁相环控制电路，用于产生具有表示数字数据值的值的控制数据的锁相环控制电路，以及具有用于将控制数据转换成模拟信号并具有可变输出的可调转换特性的DA转换电路将压控振荡器的模拟信号作为电压控制信号。基于具有预定播放特性的输入信号调整DA转换电路的可调转换特性，并且当锁相环电路是记录和再现装置的一部分时，输入信号是从记录的信号的再现信号在记录介质上。

6. 发明授权

US06700721B2 Magnetic recording and reproducing apparatus and semiconductor integrated circuit for use in the same comprising a read/write signal processor having an interleave write data generator 失效
标题翻译：磁记录和再现装置和用于其中的半导体集成电路包括具有交错写入数据发生器的读/写信号处理器
公开(公告)号：US06700721B2
公开(公告)日：2004-03-02
申请号：US10191562
申请日：2002-07-10
申请人： Eisaku Saiki , Shintaro Suzumura , Terumi Takashi , Kazutoshi Ashikawa , Tsuguyoshi Hirooka , Shoichi Miyazawa , Masashi Mori
发明人： Eisaku Saiki , Shintaro Suzumura , Terumi Takashi , Kazutoshi Ashikawa , Tsuguyoshi Hirooka , Shoichi Miyazawa , Masashi Mori
IPC分类号： G11B509
CPC分类号： G11B5/09 , G11B5/012 , G11B5/02 , G11B20/10009 , H03F3/45089 , H03F3/45103 , H03F3/72 , H03F2203/45316
摘要： A magnetic recording and reproducing apparatus includes a R/W signal processor having a write data generator arranged to be of an interleave system and transmitting/receiving data to/from the R/W amplifier via a plurality of signal lines. In addition, the R/W amplifier has a compound circuit provided for the write data of the interleave system from the R/W signal processor and is formed as an integrated circuit, moreover, a ½ prescaler is provided at the output of the write data generator, making transmitting and receiving write data in NRZI CODE.
摘要翻译：磁记录和重放装置包括一个R / W信号处理器，其具有被布置成交错系统的写入数据发生器，并经由多个信号线向/从R / W放大器发送/接收数据。此外，R / W放大器具有为来自R / W信号处理器的交错系统的写入数据提供的复合电路，并且形成为集成电路，此外，在写入数据的输出端提供½预分频器发送器，在NRZI CODE中发送和接收写入数据。

7. 发明授权

US06452736B1 Magnetic recording and reproducing apparatus and a read/write amplifier having a signal transmission system with high speed of data write signal 失效
标题翻译：磁记录和再现装置以及具有高速数据写入信号的信号传输系统的读/写放大器
公开(公告)号：US06452736B1
公开(公告)日：2002-09-17
申请号：US08450245
申请日：1995-05-25
申请人： Eisaku Saiki , Shintaro Suzumura , Terumi Takashi , Kazutoshi Ashikawa , Tsuguyoshi Hirooka , Shoichi Miyazawa , Masashi Mori
发明人： Eisaku Saiki , Shintaro Suzumura , Terumi Takashi , Kazutoshi Ashikawa , Tsuguyoshi Hirooka , Shoichi Miyazawa , Masashi Mori
IPC分类号： G11B509
CPC分类号： G11B5/09 , G11B5/012 , G11B5/02 , G11B20/10009 , H03F3/45089 , H03F3/45103 , H03F3/72 , H03F2203/45316
摘要： A magnetic recording and reproducing apparatus includes a read/write signal processor having a write data generator arranged to be of an interleave system and transmitting/receiving data to/from the read/write amplifier via a plurality of signal lines. In addition, the read/write amplifier has a compound circuit provided for the write data of the interleave system from the read/write signal processor and is formed as an integrated circuit, moreover, a 1/2 prescaler is provided at the output of the write data generator, transmitting and receiving write data in Non-Return-To-Zero-Interleave CODE.
摘要翻译：磁记录和再现装置包括一个读/写信号处理器，该读/写信号处理器具有布置成交错系统的写数据发生器，并经由多个信号线向读/写放大器发送/接收数据。此外，读/写放大器具有为来自读/写信号处理器的交错系统的写入数据提供的复合电路，并且形成为集成电路，此外，在该输出处提供1/2预分频器写数据生成器，在非归零交错CODE中发送和接收写入数据。

8. 发明授权

US5448424A AGC circuit and recording and reproducing apparatus using AGC circuit 失效
标题翻译： AGC电路和使用AGC电路的记录和再现设备
公开(公告)号：US5448424A
公开(公告)日：1995-09-05
申请号：US196478
申请日：1994-02-15
申请人： Akihiko Hirano , Terumi Takashi , Kazunori Iwabuchi , Hideyuki Yamakawa , Yoshiteru Ishida , Minoru Kosuge
发明人： Akihiko Hirano , Terumi Takashi , Kazunori Iwabuchi , Hideyuki Yamakawa , Yoshiteru Ishida , Minoru Kosuge
IPC分类号： G11B5/09 , G11B20/04 , G11B20/10 , G11B20/12 , G11B20/14 , H03G3/00 , H03G3/20 , H03G3/30 , H03G11/00 , G11B5/035
CPC分类号： G11B20/10055 , G11B20/10009 , G11B20/1403 , H03G3/001 , G11B20/1252
摘要： An AGC circuit is provided with a variable gain amplifier which changes an amplification gain of an input signal in accordance with an instruction; an extraction unit for extracting a value of an output of the variable gain amplifier at a predetermined interval; and a variable gain control unit for instructing the amplification gain of the variable gain amplifier in a manner such that the amplitude of the input signal is equal to a predetermined amplitude on the basis of the value extracted by the extraction unit. The variable gain control unit is provided with an error signal output device for squaring the value extracted by the extraction unit and for generating an error signal to instruct the amplification gain of the variable gain amplifier in a manner such that the amplitude of the input signal is equal to a predetermined amplitude on the basis of the square value and a square value just before it; and an integrating device for integrating the error signal from the error signal output device and for instructing the amplification gain of the variable gain amplifier.
摘要翻译： AGC电路设置有根据指令改变输入信号的放大增益的可变增益放大器; 提取单元，用于以预定间隔提取可变增益放大器的输出值; 以及可变增益控制单元，用于以使得输入信号的幅度基于由提取单元提取的值等于预定幅度的方式来指示可变增益放大器的放大增益。可变增益控制单元设置有误差信号输出装置，用于对由提取单元提取的值进行平方，并产生误差信号，以使得输入信号的振幅为基于正方形值等于预定幅度和刚好在其前的平方值; 以及用于积分来自误差信号输出装置的误差信号并用于指示可变增益放大器的放大增益的积分装置。

9. 发明授权

US5553104A Information recording/reproducing apparatus having a clock timing extraction circuit for extracting a clock signal from an input data signal 失效
标题翻译：具有用于从输入数据信号中提取时钟信号的时钟定时提取电路的信息记录/再现装置
公开(公告)号：US5553104A
公开(公告)日：1996-09-03
申请号：US266779
申请日：1994-06-29
申请人： Terumi Takashi , Akihiko Hirano , Kazunori Iwabuchi , Hideyuki Yamakawa , Yoshiteru Ishida , Kazuhisa Shiraishi , Kazutoshi Ashikawa
发明人： Terumi Takashi , Akihiko Hirano , Kazunori Iwabuchi , Hideyuki Yamakawa , Yoshiteru Ishida , Kazuhisa Shiraishi , Kazutoshi Ashikawa
IPC分类号： G11B20/14 , G11B27/30 , H03L7/06 , H03L7/081 , H03L7/099 , H03L7/183 , H04L7/033 , H03D3/24
CPC分类号： H03L7/0996 , G11B20/1403 , G11B27/30 , H03L7/081 , H03L7/183 , H04L7/0337
摘要： A clock timing extraction circuit for use in an information recording/reproducing apparatus has a phase comparator for comparing the reproduced signal with a selected clock signal to generate a phase error signal, a clock signal generation circuit for adjusting frequency to cause the error signal to approach zero according to the phase error signal and outputting a plurality of clock signals having mutually different phase differences, a selection circuit for outputting one of the plurality of clock signals on the basis of a selection signal, a phase difference judgement circuit for determining one of the plurality of clock signals having a minimum phase error (Vdet) and generating a selection signal for selection of the clock signal having the minimum phase difference, and a freeze circuit for blocking an output of the phase comparator until the clock signal having the minimum phase error is selected. The information recording/reproducing apparatus has an AGC circuit for limiting an amplitude of a reproduced signal received from a recording medium, the aforementioned clock timing extraction circuit, and a decoder circuit. The clock timing extraction circuit extracts a clock signal from an output signal of the AGC circuit and the decoder decodes the output signal of the AGC circuit on the basis of the extracted clock signal.
摘要翻译：用于信息记录/再现装置的时钟定时提取电路具有一个相位比较器，用于将再生信号与所选择的时钟信号进行比较以产生相位误差信号;时钟信号产生电路，用于调整频率以使误差信号接近根据相位误差信号输出零，并输出具有相互不同的相位差的多个时钟信号，用于基于选择信号输出多个时钟信号中的一个的选择电路，用于确定其中之一的相位差判定电路具有最小相位误差（Vdet）的多个时钟信号，并且产生用于选择具有最小相位差的时钟信号的选择信号，以及用于阻止相位比较器的输出的冻结电路，直到具有最小相位误差的时钟信号被选中。信息记录/重放装置具有用于限制从记录介质接收的再现信号的幅度的AGC电路，上述时钟定时提取电路和解码器电路。时钟定时提取电路从AGC电路的输出信号中提取时钟信号，解码器根据所提取的时钟信号对AGC电路的输出信号进行解码。

10. 发明授权

US08117518B2 Signal processing apparatus and a data recording and reproducing apparatus including local memory processor 有权
标题翻译：信号处理装置和包括本地存储处理器的数据记录和再现装置
公开(公告)号：US08117518B2
公开(公告)日：2012-02-14
申请号：US12003270
申请日：2007-12-21
申请人： Terumi Takashi , Seiichi Mita , Atsushi Saito
发明人： Terumi Takashi , Seiichi Mita , Atsushi Saito
IPC分类号： G06F11/00
CPC分类号： G11B20/10009 , G11B20/00086 , G11B20/10055 , G11B20/10074 , G11B20/10481 , G11B20/18 , G11B2020/10638 , G11B2020/183
摘要： In a data recovery processing, the conventional overhead, primarily, latency due to a rotational recording media is removed. Secondary, in a signal processing or in a recording and reproducing apparatus, reliability of data reproduction is improved by repeatedly processing data. These processing are achieved that input signal, i.e., raw analog signal read from the recording media is digitized to be stored in a secondary storage such as a memory or a FIFO memory. The apparatus includes a signal processing circuit to repeatedly process the stored digital signal in the secondary storage. When detecting data, operation of the circuit is efficiently controlled by a change over detector parameters, in which characteristics for the detecting performance. Resultantly, data recovery processing speed is increased and reliability of data reproduced is improved.
摘要翻译：在数据恢复处理中，传统的开销，主要是由旋转记录介质引起的等待时间被去除。在信号处理或记录和再现装置中，通过重复处理数据来提高数据再现的可靠性。实现这些处理，即将从记录介质读取的原始模拟信号的输入信号数字化以存储在诸如存储器或FIFO存储器的辅助存储器中。该装置包括信号处理电路，用于重复处理二次存储器中存储的数字信号。当检测到数据时，通过改变检测器参数来有效地控制电路的操作，其中检测性能的特性。从而提高数据恢复处理速度，提高数据再现的可靠性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式