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    • 1. 发明授权
    • Information recording/reproducing apparatus having a clock timing
extraction circuit for extracting a clock signal from an input data
signal
    • 具有用于从输入数据信号中提取时钟信号的时钟定时提取电路的信息记录/再现装置
    • US5553104A
    • 1996-09-03
    • US266779
    • 1994-06-29
    • Terumi TakashiAkihiko HiranoKazunori IwabuchiHideyuki YamakawaYoshiteru IshidaKazuhisa ShiraishiKazutoshi Ashikawa
    • Terumi TakashiAkihiko HiranoKazunori IwabuchiHideyuki YamakawaYoshiteru IshidaKazuhisa ShiraishiKazutoshi Ashikawa
    • G11B20/14G11B27/30H03L7/06H03L7/081H03L7/099H03L7/183H04L7/033H03D3/24
    • H03L7/0996G11B20/1403G11B27/30H03L7/081H03L7/183H04L7/0337
    • A clock timing extraction circuit for use in an information recording/reproducing apparatus has a phase comparator for comparing the reproduced signal with a selected clock signal to generate a phase error signal, a clock signal generation circuit for adjusting frequency to cause the error signal to approach zero according to the phase error signal and outputting a plurality of clock signals having mutually different phase differences, a selection circuit for outputting one of the plurality of clock signals on the basis of a selection signal, a phase difference judgement circuit for determining one of the plurality of clock signals having a minimum phase error (Vdet) and generating a selection signal for selection of the clock signal having the minimum phase difference, and a freeze circuit for blocking an output of the phase comparator until the clock signal having the minimum phase error is selected. The information recording/reproducing apparatus has an AGC circuit for limiting an amplitude of a reproduced signal received from a recording medium, the aforementioned clock timing extraction circuit, and a decoder circuit. The clock timing extraction circuit extracts a clock signal from an output signal of the AGC circuit and the decoder decodes the output signal of the AGC circuit on the basis of the extracted clock signal.
    • 用于信息记录/再现装置的时钟定时提取电路具有一个相位比较器,用于将再生信号与所选择的时钟信号进行比较以产生相位误差信号;时钟信号产生电路,用于调整频率以使误差信号接近 根据相位误差信号输出零,并输出具有相互不同的相位差的多个时钟信号,用于基于选择信号输出多个时钟信号中的一个的选择电路,用于确定其中之一的相位差判定电路 具有最小相位误差(Vdet)的多个时钟信号,并且产生用于选择具有最小相位差的时钟信号的选择信号,以及用于阻止相位比较器的输出的冻结电路,直到具有最小相位误差的时钟信号 被选中。 信息记录/重放装置具有用于限制从记录介质接收的再现信号的幅度的AGC电路,上述时钟定时提取电路和解码器电路。 时钟定时提取电路从AGC电路的输出信号中提取时钟信号,解码器根据所提取的时钟信号对AGC电路的输出信号进行解码。
    • 5. 发明授权
    • Digital magnetic writing and reading apparatus
    • 数字磁读写装置
    • US5337198A
    • 1994-08-09
    • US909997
    • 1992-07-07
    • Nobumasa NishiyamaToshiaki TsuyoshiHajime AoiTetsuji KameokaMasaya TanakaKazuhisa Shiraishi
    • Nobumasa NishiyamaToshiaki TsuyoshiHajime AoiTetsuji KameokaMasaya TanakaKazuhisa Shiraishi
    • G11B5/09G11B5/035
    • G11B5/09G11B20/10046
    • A waveform equalizer for processing a signal read by a magnetic head from a magnetic written medium includes a slimming circuit which, in turn, has a first delay unit for delaying the read signal, a first attenuator connected in parallel with the first delay unit, a first differentiating circuit for receiving the output from the first delay unit and the output from the first attenuator, and a resistor connected to a first delay unit side input of the first differential circuit; and a pseudo-peak elimination circuit connected in series with the slimming circuit and including a circuit for separating the from the read signal the read signal or a signal reverse in phase to the read signal, a second delay unit for delaying the separated signal, a second attenuator for attenuating the amplitude of the separated signal, and a second differential circuit for receiving the read signal and the separated, delayed and attenuated signal.
    • 用于处理由磁性写入介质由磁头读取的信号的波形均衡器包括减弱电路,该减幅电路又具有用于延迟读取信号的第一延迟单元,与第一延迟单元并联连接的第一衰减器, 用于接收来自第一延迟单元的输出和来自第一衰减器的输出的第一微分电路,以及连接到第一差分电路的第一延迟单元侧输入的电阻器; 以及与所述减肥电路串联连接的伪峰值消除电路,并且包括用于将读取信号或相反相反的信号与读取信号分离的读取信号的电路,用于延迟分离的信号的第二延迟单元, 第二衰减器,用于衰减分离信号的振幅;以及第二差分电路,用于接收读取信号和分离的,延迟和衰减的信号。