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    • 10. 发明授权
    • Phase-locked loop IC having ECL buffers
    • 具有ECL缓冲器的锁相环IC
    • US5157354A
    • 1992-10-20
    • US799442
    • 1991-11-27
    • Eisaku SaikiShintaro SuzumuraFukashi OhiAkira UragamiTsuyoshi Tateyama
    • Eisaku SaikiShintaro SuzumuraFukashi OhiAkira UragamiTsuyoshi Tateyama
    • G11B20/12G11B20/14H03D13/00H03K19/0175H03L7/06H03L7/10H03L7/107H03L7/113
    • G11B20/1403H03D13/004H03K19/017518H03L7/107H03L7/113G11B20/1258
    • A phase locked loop IC comprising a voltage controlled oscillator which generates a clock signal in accordance with a control voltage, a first ECL input buffer which is an input buffer for a signal to be synchronized, a phase-lock capture circuit for producing a current determinative of the control voltage in accordance with the phase difference and the frequency difference between the signal to be synchronized and the clock signal, and a phase-lock follow-up circuit for producing a current determinative of the control voltage in accordance with the phase difference between the clock signal and the signal to be synchronized; wherein the supply voltage system of the first ECL input buffer is so disposed as to be isolated from any of the supply voltage systems of the voltage-controlled oscillator, the phase-lock capture circuit and the phase lock follow-up circuit, while the ground system of the first ECL input buffer is so disposed as to be insolated from any of the ground systems of the voltage-controlled oscillator, the phase-lock capture circuit and the phase-lock follow-up circuit.
    • 一种锁相环IC,包括根据控制电压产生时钟信号的压控振荡器,作为用于待同步信号的输入缓冲器的第一ECL输入缓冲器,用于产生电流确定性的锁相捕获电路 根据相位差和要同步的信号与时钟信号之间的频率差的控制电压,以及相位锁定跟随电路,用于根据相位差的相位差产生控制电压的电流确定 时钟信号和要同步的信号; 其中第一ECL输入缓冲器的电源电压系统被布置为与压控振荡器,锁相捕获电路和锁相跟随电路的任何一个电压系统隔离,而地 第一ECL输入缓冲器的系统被布置成从压控振荡器,锁相捕获电路和锁相跟随电路的任何地面系统中被绝缘。