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1. 发明授权

US4845537A Vertical type MOS transistor and method of formation thereof 失效
标题翻译：垂直型MOS晶体管及其形成方法
公开(公告)号：US4845537A
公开(公告)日：1989-07-04
申请号：US127138
申请日：1987-12-01
申请人： Tadashi Nishimura , Kazuyuki Sugahara , Shigeru Kusunoki , Akihiko Ohsaki
发明人： Tadashi Nishimura , Kazuyuki Sugahara , Shigeru Kusunoki , Akihiko Ohsaki
IPC分类号： H01L27/10 , H01L21/336 , H01L21/8242 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10841 , H01L29/7827
摘要： A vertical MOS transistor having its channel length determined by the thickness of an insulating layer provided over a semiconductor substrate, rather than by the depth of a trench in which the transistor is formed. As a result, the characteristics of the transistor as relatively unaffected by doping and heat-treatment steps which are performed during formation. Also, the transistor may be formed so as to occupy very little surface area, making it suitable for application in high-density DRAMs. 0O048455372
摘要翻译：一种垂直MOS晶体管，其沟道长度由设置在半导体衬底上的绝缘层的厚度确定，而不是由形成晶体管的沟槽的深度确定。结果，晶体管的特性相对不受在形成期间进行的掺杂和热处理步骤的影响。此外，晶体管可以形成为占据非常小的表面积，使其适用于高密度DRAM。 0048455372

2. 发明授权

US4953125A Semiconductor memory device having improved connecting structure of bit line and memory cell 失效
标题翻译：半导体存储器件具有改进的位线和存储单元的连接结构
公开(公告)号：US4953125A
公开(公告)日：1990-08-28
申请号：US173749
申请日：1988-03-25
申请人： Yoshinori Okumura , Akihiko Ohsaki , Kazuyuki Sugahara , Tatsuhiko Ikeda
发明人： Yoshinori Okumura , Akihiko Ohsaki , Kazuyuki Sugahara , Tatsuhiko Ikeda
IPC分类号： H01L29/41 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10829
摘要： A semiconductor memory device includes a first trench serving as a memory cell formed in a p type semiconductor substrate, a first n type semiconductor region formed adjacent to the trench region and on the major surface of the semiconductor substrate, a conductive layer serving as an electron active region formed adjacent to the first n type region and on the major surface of the semiconductor substrate, a second n type semiconductor region formed adjacent to the electron active region and on the major surface of the semiconductor substrate, a second trench formed adjacent to the second n type semiconductor region in the major surface of the semiconductor substrate which is shallower than the first trench, an interconnection layer serving as a bit line formed in a self-aligning manner in the sidewall portion of the second trench which is shallower than the first trench and a gate electrode serving as a word line formed in the upper portion of the conductive layer through an oxide film.
摘要翻译：半导体存储器件包括用作形成在p型半导体衬底中的存储单元的第一沟槽，与沟槽区相邻并且在半导体衬底的主表面上形成的第一n型半导体区，用作电子活性的导电层形成在与第一n型区域相邻并且在半导体衬底的主表面上形成的第二n型半导体区域，形成在与电子有源区相邻并且在半导体衬底的主表面上，第二沟槽，在半导体衬底的主表面上比第一沟槽浅的n型半导体区域，在第二沟槽的侧壁部分中以自对准的方式形成的位线的互连层比第一沟槽浅以及用作通过氧化膜形成在导电层的上部的字线的栅电极。

3. 发明授权

US5017504A Vertical type MOS transistor and method of formation thereof 失效
标题翻译：垂直型MOS晶体管及其形成方法
公开(公告)号：US5017504A
公开(公告)日：1991-05-21
申请号：US341596
申请日：1989-04-21
申请人： Tadashi Nishimura , Kazukyuki Sugahara , Shigeru Kusunori , Akihiko Ohsaki
发明人： Tadashi Nishimura , Kazukyuki Sugahara , Shigeru Kusunori , Akihiko Ohsaki
IPC分类号： H01L27/108 , H01L29/78
CPC分类号： H01L27/10841 , H01L29/7827
摘要： A vertical MOS transistor having its channel length determined by the thickness of an insulating layer provided over a semiconductor substrate, rather than by the depth of a trench in which the transistor is formed. As a result, the characteristics of the transistor as relatively unaffected by doping and heat-treatment steps which are performed during formation. Also, the transistor may be formed so as to occupy very little surface area, making it suitable for application in high-density DRAMs.
摘要翻译：一种垂直MOS晶体管，其沟道长度由设置在半导体衬底上的绝缘层的厚度确定，而不是由形成晶体管的沟槽的深度确定。结果，晶体管的特性相对不受在形成期间进行的掺杂和热处理步骤的影响。此外，晶体管可以形成为占据极小的表面积，使其适用于高密度DRAM。

4. 发明授权

US06624516B2 Structure for connecting interconnect lines with interposed layer including metal layers and metallic compound layer 有权
标题翻译：用于连接具有包括金属层和金属化合物层的插入层的互连线的结构
公开(公告)号：US06624516B2
公开(公告)日：2003-09-23
申请号：US09978005
申请日：2001-10-17
申请人： Masahiko Fujisawa , Akihiko Ohsaki , Noboru Morimoto
发明人： Masahiko Fujisawa , Akihiko Ohsaki , Noboru Morimoto
IPC分类号： H01L2348
CPC分类号： H01L21/76846 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A metal layer (7), a metallic compound layer (8) and a metal layer (9) are stacked in this order when viewed from the side of a first copper interconnect line (2) and an interlayer insulating film (5) to constitute a second conductive barrier layer (20). As the material for the metal layers (7) and (9), an element having an atomic weight higher than that of copper such as tungsten (W) or tantalum (Ta) is applicable. A second copper interconnect line (6) is conductively connected to the first copper interconnect line (2) at a contact hole (12) through the second conductive barrier layer (20). As the ratio of the volume of the second copper interconnect line (6) at the region for filling a trench (11) to the volume of the second copper interconnect line (6) at the region for filling the contact hole (12) increases, tensile stress to be concentrated at the contact hole (12) becomes greater. As a result, a void is likely to be generated in the contact hole (12). In view of this, in order to improve the adhesion especially between the second copper interconnect line (6) at the region for filling the contact hole (12) and the second conductive barrier layer (20), the metal layer (9) is provided.
摘要翻译：从第一铜互连线（2）和层间绝缘膜（5）的侧面观察时，依次层叠金属层（7），金属化合物层（8）和金属层（9），构成第二导电阻挡层（20）。作为金属层（7）和（9）的材料，可以使用原子量高于诸如钨（W）或钽（Ta）的铜的元素。第二铜互连线（6）通过第二导电阻挡层（20）在接触孔（12）处导电地连接到第一铜互连线（2）。由于在填充接触孔（12）的区域处，用于填充沟槽（11）的区域处的第二铜互连线（6）的体积与第二铜互连线（6）的体积的比率增加，要集中在接触孔（12）处的拉伸应力变大。结果，在接触孔（12）中容易产生空隙。鉴于此，为了改善在用于填充接触孔（12）的区域和第二导电阻挡层（20）之间的第二铜互连线（6）之间的粘合性，提供了金属层（9）。

5. 发明申请

US20090212437A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20090212437A1
公开(公告)日：2009-08-27
申请号：US12389071
申请日：2009-02-19
申请人： Yukihiro Kumagai , Hiroyuki Ohta , Naotaka Tanaka , Masahiko Fujisawa , Akihiko Ohsaki
发明人： Yukihiro Kumagai , Hiroyuki Ohta , Naotaka Tanaka , Masahiko Fujisawa , Akihiko Ohsaki
IPC分类号： H01L23/532
CPC分类号： H01L23/53238 , H01L23/3128 , H01L23/53295 , H01L23/585 , H01L24/45 , H01L24/48 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/73204 , H01L2924/00014 , H01L2924/01015 , H01L2924/12041 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00015 , H01L2924/00012 , H01L2224/0401
摘要： In a semiconductor device having a Low-k film as an interlayer insulator, peeling of the interlayer insulator in a thermal cycle test is prevented, thereby providing a highly reliable semiconductor device. In a semiconductor device having a structure in which interlayer insulators in which buried wires each having a main electric conductive layer made of copper are formed and cap insulators of the buried wires are stacked, the cap insulator having a relatively high Young's modulus and contacting by its upper surface with the interlayer insulator made of a Low-k film having a relatively low Young's modulus is formed so as not to be provided in an edge portion of the semiconductor device.
摘要翻译：在具有Low-k膜作为层间绝缘体的半导体器件中，防止了热循环试验中的层间绝缘体的剥离，从而提供高可靠性的半导体器件。在具有这样的结构的半导体器件中，其中形成有由铜制成的主导电层的埋入布线和层叠埋入导线的帽绝缘体的层间绝缘体，所述盖绝缘体具有较高的杨氏模量并且通过其接触形成具有相对低的杨氏模量的由Low-k膜制成的层间绝缘体的上表面，以便不设置在半导体器件的边缘部分中。

6. 发明授权

US06780769B2 Method of manufacturing structure for connecting interconnect lines including metal layer with thickness larger than thickness of metallic compound layer 有权
标题翻译：制造包括厚度大于金属化合物层厚度的金属层的互连线的结构的制造方法
公开(公告)号：US06780769B2
公开(公告)日：2004-08-24
申请号：US10464502
申请日：2003-06-19
申请人： Masahiko Fujisawa , Akihiko Ohsaki , Noboru Morimoto
发明人： Masahiko Fujisawa , Akihiko Ohsaki , Noboru Morimoto
IPC分类号： H01L2144
CPC分类号： H01L21/76846 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A metal layer (7), a metallic compound layer (8) and a metal layer (9) are stacked in this order when viewed from the side of a first copper interconnect line (2) and an interlayer insulating film (5) to constitute a second conductive barrier layer (20). As the material for the metal layers (7) and (9), an element having an atomic weight higher than that of copper such as tungsten (W) or tantalum (Ta) is applicable. A second copper interconnect line (6) is conductively connected to the first copper interconnect line (2) at a contact hole (12) through the second conductive barrier layer (20). As the ratio of the volume of the second copper interconnect line (6) at the region for filling a trench (11) to the volume of the second copper interconnect line (6) at the region for filling the contact hole (12) increases, tensile stress to be concentrated at the contact hole (12) becomes greater. As a result, a void is likely to be generated in the contact hole (12). In view of this, in order to improve the adhesion especially between the second copper interconnect line (6) at the region for filling the contact hole (12) and the second conductive barrier layer (20), the metal layer (9) is provided.
摘要翻译：从第一铜互连线（2）和层间绝缘膜（5）的侧面观察时，依次层叠金属层（7），金属化合物层（8）和金属层（9），构成第二导电阻挡层（20）。作为金属层（7）和（9）的材料，可以使用原子量高于诸如钨（W）或钽（Ta）的铜的元素。第二铜互连线（6）通过第二导电阻挡层（20）在接触孔（12）处导电地连接到第一铜互连线（2）。由于在填充接触孔（12）的区域处，用于填充沟槽（11）的区域处的第二铜互连线（6）的体积与第二铜互连线（6）的体积的比率增加，要集中在接触孔（12）处的拉伸应力变大。结果，在接触孔（12）中容易产生空隙。鉴于此，为了改善在用于填充接触孔（12）的区域和第二导电阻挡层（20）之间的第二铜互连线（6）之间的粘合性，提供了金属层（9）。

7. 发明授权

US5712140A Method of manufacturing interconnection structure of a semiconductor device 失效
标题翻译：制造半导体器件的互连结构的方法
公开(公告)号：US5712140A
公开(公告)日：1998-01-27
申请号：US816201
申请日：1997-03-25
申请人： Atsushi Ishii , Yoshifumi Takata , Akihiko Ohsaki , Kazuyoshi Maekawa
发明人： Atsushi Ishii , Yoshifumi Takata , Akihiko Ohsaki , Kazuyoshi Maekawa
IPC分类号： H01L23/522 , H01L21/768 , H01L23/532 , H01L21/283
CPC分类号： H01L23/53223 , H01L2924/0002 , Y10S257/915
摘要： An aluminum interconnection film has a three layered structure of an aluminum alloy film, a tungsten film, and a titanium nitride film. An aluminum interconnection film and a second aluminum interconnection film are electrically connected through a through hole formed in a silicon oxide film. Because light reflectivity of the titanium nitride film is low, the exposed area of the resist can be kept within a predetermined area even if photolithography is carried out above a step where light is irregularly reflected. Therefore, it is possible to form a through hole of a desired dimension even if the through hole is formed above the step. Even if the titanium nitride film is etched and removed in forming the through hole, the aluminum alloy film is not exposed since the etching speed of the silicon oxide film is considerably slower than that of the tungsten film. The problem of denatured layer formation and residue formation caused by exposure of aluminum alloy film does not occur.
摘要翻译：铝互连膜具有铝合金膜，钨膜和氮化钛膜的三层结构。铝互连膜和第二铝互连膜通过形成在氧化硅膜中的通孔电连接。由于氮化钛膜的光反射率低，所以即使在光不规则地反射的步骤上进行光刻，也可以将抗蚀剂的露出面积保持在规定的面积内。因此，即使在台阶上方形成通孔，也可以形成所需尺寸的通孔。即使在形成通孔时蚀刻和去除氮化钛膜，由于氧化硅膜的蚀刻速度比钨膜的蚀刻速度慢得多，因此铝合金膜不暴露。不会发生由铝合金膜暴露引起的变性层形成和残留物形成的问题。

8. 发明授权

US5565708A Semiconductor device comprising composite barrier layer 失效
标题翻译：包括复合阻挡层的半导体器件
公开(公告)号：US5565708A
公开(公告)日：1996-10-15
申请号：US440808
申请日：1995-05-15
申请人： Akihiko Ohsaki , Sumio Yamaguchi , Atsushi Ishii , Kazuyoshi Maekawa , Masahiko Fujisawa
发明人： Akihiko Ohsaki , Sumio Yamaguchi , Atsushi Ishii , Kazuyoshi Maekawa , Masahiko Fujisawa
IPC分类号： H01L21/28 , C23C14/06 , C23C14/18 , C23C14/58 , H01L21/203 , H01L21/205 , H01L21/285 , H01L21/768 , H01L23/485 , H01L23/522 , H01L23/532 , H01L23/48 , H01L29/46 , H01L29/54 , H01L29/62
CPC分类号： C23C14/5806 , C23C14/0641 , C23C14/185 , H01L21/28518 , H01L21/76843 , H01L21/76846 , H01L21/76855 , H01L21/76856 , H01L23/485 , H01L23/53257 , H01L2924/0002 , Y10S257/915
摘要： A semiconductor device comprising conductors electrically connected through a contact hole interlayer insulation layer with a trilayer barrier layer comprising a titanium silicide layer, titanium silicide layer formed on the titanium silicide by collimation sputtering, and a thermally nitrided titanium formed on the titanium nitride layer. The use of a trilayer barrier layer enables through the capacity of the collimation sputtering apparatus to be increased, prevents particles from occurring, and formation of a low resistance electrical connection between conductors, in addition to preventing diffusion from the titanium nitride layer and the second titanium layer to the thermally nitrided titanium layer, and between conductors.
摘要翻译：一种半导体器件，包括通过接触孔层间绝缘层与通过准直溅射形成在硅化钛上的钛硅化物层，硅化钛层和形成在氮化钛层上的热氮化钛的三层势垒层电连接的导体。除了防止从氮化钛层和第二钛的扩散之外，使用三层阻挡层能够增加准直溅射装置的容量，防止颗粒发生，以及形成导体之间的低电阻电连接层到热氮化钛层和导体之间。

9. 发明授权

US5475267A Multilayer interconnection structure for a semiconductor device 失效
标题翻译：半导体器件的多层互连结构
公开(公告)号：US5475267A
公开(公告)日：1995-12-12
申请号：US354737
申请日：1994-12-08
申请人： Atsushi Ishii , Yoshifumi Takata , Akihiko Ohsaki , Kazuyoshi Maekawa
发明人： Atsushi Ishii , Yoshifumi Takata , Akihiko Ohsaki , Kazuyoshi Maekawa
IPC分类号： H01L23/522 , H01L21/768 , H01L23/532 , H01L29/43
CPC分类号： H01L23/53223 , H01L2924/0002 , Y10S257/915
摘要： An aluminum interconnection film has a three layered structure of an aluminum alloy film, a tungsten film, and a titanium nitride film. An aluminum interconnection film and an aluminum interconnection film are electrically connected through a through hole formed in a silicon oxide film, one embodiment using a tungsten plug for the electrical connection. Because light reflectivity of the titanium nitride film is low, the exposed area of the resist can be kept within a predetermined area even if photolithography is carried out above a step where light is irregularly reflected. Therefore, it is possible to form a through hole of a desired dimension even if the through hole is formed above the step. Even if the titanium nitride film is etched and removed in forming the through hole, the aluminum alloy film is not exposed since the etching speed of the silicon oxide film is considerably slower than that of the tungsten film. The problem of denatured layer formation and residue formation caused by exposure of aluminum alloy film does not occur.
摘要翻译：铝互连膜具有铝合金膜，钨膜和氮化钛膜的三层结构。铝互连膜和铝互连膜通过形成在氧化硅膜中的通孔电连接，一个实施例使用用于电连接的钨塞。由于氮化钛膜的光反射率低，所以即使在光不规则地反射的步骤上进行光刻，也可以将抗蚀剂的露出面积保持在规定的面积内。因此，即使在台阶上方形成通孔，也可以形成所需尺寸的通孔。即使在形成通孔时蚀刻和去除氮化钛膜，由于氧化硅膜的蚀刻速度比钨膜的蚀刻速度慢得多，因此铝合金膜不暴露。不会发生由铝合金膜暴露引起的变性层形成和残留物形成的问题。

10. 发明授权

US06198143B1 Semiconductor device including a layer of thermally stable titanium silicide 失效
标题翻译：半导体器件包括一层热稳定的硅化钛
公开(公告)号：US06198143B1
公开(公告)日：2001-03-06
申请号：US08637009
申请日：1996-04-24
申请人： Akihiko Ohsaki
发明人： Akihiko Ohsaki
IPC分类号： H01L2348
CPC分类号： H01L21/76889 , H01L21/2257 , H01L21/28052 , H01L21/28518 , H01L21/32105 , H01L23/53257 , H01L27/10808 , H01L29/41775 , H01L29/41783 , H01L29/4933 , H01L29/665 , H01L29/6659 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： Highly refractory titanium silicide structure comprises a titanium silicide film formed on a silicon crystal surface and a thermal oxide film formed on this titanium silicide film. A manufacturing method of the highly refractory titanium silicide is as follows. Initially, titanium is deposited on surfaces including a silicon crystal surface to form a titanium film (12) of a predetermined thickness. This titanium film (12) is then heat-treated in vacuum or in a certain atmosphere which does not cause any oxidation, to form a titanium silicide film (13). Subsequently, further heat treatment at temperatures between 600° C. and 1,000° C. in oxygen atmosphere is done for a predetermined time to oxidize the surface of the titanium silicide film (13). This oxidization of the surface of the titanium silicide film (13) restrains agglomeration in the titanium silicide which might occur in the subsequent annealing, so that the resistance value increase can be prevented.
摘要翻译：高耐火钛硅化物结构包括在硅晶体表面上形成的硅化钛膜和在该硅化钛膜上形成的热氧化膜。高耐火钛硅化物的制造方法如下。首先，将钛沉积在包括硅晶体表面的表面上以形成预定厚度的钛膜（12）。然后将该钛膜（12）在真空中或在不引起任何氧化的某一气氛中进行热处理，形成硅化钛膜（13）。随后，在氧气氛中在600℃和1000℃之间的温度下进行进一步的热处理预定时间以氧化硅化钛膜（13）的表面。硅化钛膜（13）的表面的这种氧化抑制了可能在随后的退火中发生的硅化钛中的团聚，从而可以防止电阻值增加。

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