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1. 发明公开

CN1036666A 场效应控制的双极型功率半导体器件及其制造方法无效
公开(公告)号：CN1036666A
公开(公告)日：1989-10-25
申请号：CN89101864.6
申请日：1989-02-22
申请人：亚瑞亚·勃朗·勃威力有限公司
发明人：弗里德·海姆·鲍尔
IPC分类号： H01L29/72 , H01L29/54 , H01L29/62 , H01L29/78 , H01L21/285 , H01L21/60
CPC分类号： H01L29/665 , H01L21/28518 , H01L29/41741 , H01L29/456 , H01L29/4933 , H01L29/7395
摘要：在IGT(绝缘栅晶体管)中，用埋在结构中的专门的金属硅化物导电层使n型区(5c)与n型发射层的ρ型区(4b)，以及ρ型基极层短路。n型区(5c)的长度缩短与阴极接触层(8)和栅极(7)之间的距离无关，使器件实际上不会闭锁。

2. 发明申请

WO9010309A3 FERMI THRESHOLD FIELD EFFECT TRANSISTOR 审中-公开
标题翻译： FERMI阈值场效应晶体管
公开(公告)号：WO9010309A3
公开(公告)日：1991-01-24
申请号：PCT/US9001158
申请日：1990-03-01
申请人： THUNDERBIRD TECH INC
发明人： VINAL ALBERT W
IPC分类号： H01L29/78 , H01L21/8238 , H01L27/092 , H01L29/10 , H01L29/36 , H01L29/49 , H01L29/772 , H01L29/62 , H01L29/784
CPC分类号： H01L29/4916 , H01L29/4925 , H01L29/7831 , H01L29/7836 , H01L29/7838
摘要： A field effect transistor (FET) operates in the enhancement mode without requiring inversion by setting the device's threshold voltage to twice the Fermi potential of the semiconductor material. The FET, referred to as a Fermi Threshold FET or Fermi-FET, has a threshold voltage which is independent of oxide thickness, channel length, drain voltage and substrate doping, the vertical electric field in the channel becomes zero, thereby maximizing carrier mobility, and minimizing hot electron effects. A high speed device, substantially independent of device dimensions is thereby provided, which may be manufactured using relaxed groundrules, to provide low cost, high yield devices. Temperature dependence of threshold voltage may also be eliminated by providing a semiconductor gate contact which neutralizes the effect of substrate contact potential. Source and drain subdiffusion regions may be provided to simultaneously maximize the punch-through and impact ionization voltages of the devices, so that short channel devices do not require scaled-down power supply voltages. Multi gate devices may be provided. An accelerator gate, adjacent the drain, may further improve performance. The Fermi-FET criteria may be maintained, while allowing for a deep channel by providing a substrate contact for the Fermi-FET and applying a substrate bias to this contact. Substrate enhancement pocket regions adjacent the source and drain regions may be provided to produce a continuous depletion region under the source, drain and channel regions to thereby minimize punch-through effects.

3. 发明申请

WO1987001511A1 NON-VOLATILE SEMICONDUCTOR MEMORIES 审中-公开
标题翻译：非易失性半导体存储器
公开(公告)号：WO1987001511A1
公开(公告)日：1987-03-12
申请号：PCT/GB1986000509
申请日：1986-08-27
申请人： HUGHES MICROELECTRONICS LIMITED , WEST, James, Lionel , OWEN, Alan, Ernest , KRISHNA, Komanduri, Venkata , DELIMA, Joaquim, Joao
发明人： HUGHES MICROELECTRONICS LIMITED
IPC分类号： H01L29/62
CPC分类号： H01L29/513 , H01L29/517 , H01L29/518 , H01L29/792
摘要： Insulating layers responsible for the trapping of electric charge in non-volatile semiconductor memories, such as FAMOS or MNOS, are fabricated as thicker layers when doped with metals having partially filled d or f electron shells. Typically the insulating layer is silicon oxide doped with up to 10 atomic % of a first transition series metal.
摘要翻译：当掺杂有具有部分填充的d或f电子壳的金属时，负责在非易失性半导体存储器（例如FAMOS或MNOS）中捕获电荷的绝缘层被制造为更厚的层。通常，绝缘层是掺杂有多达10原子％的第一过渡系列金属的氧化硅。

4. 发明申请

WO1983002199A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREFOR 审中-公开
标题翻译：非挥发性半导体存储器件及其制造方法
公开(公告)号：WO1983002199A1
公开(公告)日：1983-06-23
申请号：PCT/US1982001731
申请日：1982-12-10
申请人： NCR CORPORATION
发明人： NCR CORPORATION , YEN, Yung-Chau
IPC分类号： H01L29/62
CPC分类号： H01L29/66833 , H01L21/3145 , H01L29/792
摘要： A non-volatile semiconductor memory device (50) includes, formed in successive layers on a substrate (10), a silicon oxide layer (13), a silicon oxynitride layer (14), a silicon nitride layer (15), a further silicon oxynitride layer (16) and a silicon gate electrode (19). At least one of the oxynitride layers (14, 16) is of graded oxygen:nitrogen composition. An alternative embodiment includes only a single oxynitride layer (14) formed on the oxide layer (13), the single oxynitride layer (14) being graded. The grading of the oxynitride layers (14, 16) is in incremental steps. The oxynitride layers (14, 16) and the nitride layer (15) are formed by low pressure chemical vapor deposition at the same temperature. The devices have the advantage of high retention.
摘要翻译：非易失性半导体存储器件（50）包括在衬底（10）上的连续层中形成氧化硅层（13），氧氮化硅层（14），氮化硅层（15），另外的硅氧氮化物层（16）和硅栅电极（19）。氧氮化物层（14,16）中的至少一个具有分级氧：氮组成。一个替代实施例仅包括形成在氧化物层（13）上的单个氮氧化物层（14），单个氮氧化物层（14）被分级。氮氧化物层（14,16）的分级是逐步的。氧氮化物层（14,16）和氮化物层（15）通过在相同温度下的低压化学气相沉积形成。这些器件具有高保留率的优点。

5. 发明专利

SG44467A1 Improved silicide formation on polysilicon 未知
公开(公告)号：SG44467A1
公开(公告)日：1997-12-19
申请号：SG1996000653
申请日：1992-08-20
申请人： AT & T CORP
发明人： VELAGA ANKINEEDU , ROY PRADIP KUMAR , CHITTIPEDDI SAILESH
IPC分类号： H01L21/28 , H01L21/336 , H01L29/78 , H01L21/3205 , H01L29/62
摘要： An integrated circuit includes a doped polysilicon/silicide ("polycide") gate electrode. The doped polysilicon layer comprises sub-layers (41, 42, 43, 44). The sub-layers are formed by varying the silicon deposition conditions, typically including the deposition rate, while decreasing the dopant concentration. The metal silicide layer (45) is then formed on top of the doped polysilicon layer. An improvement in uniformity and planarity of the structure is obtained as a result of stress accommodation. In addition, the sub-layers reduce the channeling effect that occurs during high energy source/drain dopant implantation. These effects allow for a reduced stack height of the gate electrode, resulting in improvements in very small (sub-micron) device structures.

6. 发明专利

HK116194A Method for producing highly integrated circuits of p- and n-channel mos transistors with gate electrodes consisting of a double layer of polysilicon and metal silicide 未知
公开(公告)号：HK116194A
公开(公告)日：1994-11-04
申请号：HK116194
申请日：1994-10-27
申请人： SIEMENS AG
发明人： HEIKE GLERISCH DIPL-PHYS , NEPPL FRANZ DR
IPC分类号： H01L27/092 , H01L21/3215 , H01L21/82 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L29/49 , H01L29/62
摘要： A process for the production of highly integrated circuits contaiining p- and n-channel MOS transistors including gate electrodes which consist of a doped double layer of polysilicon and metal silicide. The gates are doped with boron and are produced by diffusion from the metal silicide layer which has previously been doped with boron by ion implantation into the undoped polysilicon layer. The metal silicide layer preferably consisting of tantalum silicide is provided with a masking layer consisting of SiO2, and the structuring of the boron-doped silicide gate and the masking layer is carried out after the boron atoms have been diffused in. The process serves to safely avoid undesired boron penetration effects which considerably influence the short channel properties of the transistors. The process is used for the production of CMOS-circuits having a high packing density.

7. 发明专利

DE3888672T2 未知
公开(公告)号：DE3888672T2
公开(公告)日：1994-06-30
申请号：DE3888672
申请日：1988-08-15
申请人： HUGHES AIRCRAFT CO
发明人： JOSEFOWICZ JACK , RENSCH DAVID , RODOV VLADIMIR , BARTUR MEIR
IPC分类号： H01L29/78 , H01L21/28 , H01L21/283 , H01L21/31 , H01L21/312 , H01L29/423 , H01L29/43 , H01L29/49 , H01L29/51 , H01L29/94 , H01L29/62 , H01L29/76
摘要： A GaAs circuit structure is described which interposes a Langmuir-Blodgett (L-B) layer between the substrate and a conductive contact. The thickness of the layer is controlled to determine the operating characteristics of the device. The L-B layer has been found to both increase the gate barrier height for an FET, and to passivate dangling bonds and surface defects in the GaAs substrate to enable inversion mode operation. Specific FET and diode devices are described.

8. 发明专利

DE3884712T2 未知
公开(公告)号：DE3884712T2
公开(公告)日：1994-05-05
申请号：DE3884712
申请日：1988-07-27
申请人： SHARP KK
发明人： ASHIDA TSUTOMU , OKADA MIKIRO
IPC分类号： H01L21/8246 , H01L21/8247 , H01L27/112 , H01L29/78 , H01L27/10 , H01L21/82 , H01L29/62 , G11C17/00
摘要： A matrix type semiconductor memory device with higher complexity comprising: (a) a p-type (or n-type) semiconductor substrate, (b) a group of n-type (or p-type) semiconductor regions formed in the surface layer of the substrate in the from of strips arranged in parallel at a predetermined spacing, the semiconductor regions providing alternating source regions and drain regions and defining gate regions between the alternating regions, (c) a group of strips of first gate insulating film formed on the surface of the substrate at a predetermined spacing and intersecting the group of semiconductor regions, (d) a first gate electrode formed on each of the strips of first gate insulating film, (e) a group of portions of second gate insulating film formed on the exposed surface of the substrate between the strips of first gate insulating film, and (f) a second gate electrode formed on each of the portions of second gate insulating film and held out of contact with the first gate electrode, whereby a matrix of MIS semiconductor cells is formed, each of the cells being provided by the intersection of each gate region with one of the first and second electrodes, the gate regions of some of the cells being selectively doped with a p-type (or n-type) impurity substance at a higher concentration than the substrate.

9. 发明专利

DE68912071T2 未知
公开(公告)号：DE68912071T2
公开(公告)日：1994-04-28
申请号：DE68912071
申请日：1989-10-27
申请人： CASIO COMPUTER CO LTD
发明人： MATSUMOTO HIROSHI P D DEV DIV , YAMADA HIROYASU P D DEV DIV HA , YAMAMURA NOBUYUKI P D DEV DIV , SHIMOMAKI SHINICHI P D DEV DIV , KONYA NAOHIRO P D DEV DIV HAMU , BABA KYUYA P D DEV DIV HAMURA
IPC分类号： H01L27/115 , H01L29/792 , G11C11/34 , G11C17/00 , H01L29/62
摘要： A memory element is formed of a thin film transistor. The thin film transistor has a semiconductor layer (4), a source electrode (6) electrically connected to the semiconductor layer, a drain electrode (7) electrically connected to the semiconductor layer and formed separately from the source electrode, a gate electrode (2) for controlling formation of a channel of the semiconductor layer, and a gate insulation film (3) for isolating the gate electrode (2) and the semiconductor layer (4) from each other and causing a hysteresis in the relation between the drain current and the gate circuit. The insulation film is a silicon nitride film whose composition ratio of silicon to nitrogen is in a range of approx. 0.85 to 1.1. According to this invention, the relation between the gate voltage and the drain current can be set to have a hysteresis. Therefore, the thin film transistor can be used as a memory element. Further, according to this invention, data can be written, erased and read out by selectively applying an electric field to the gate insulation film. Therefore, the thin film transistor can be used as a memory element.

10. 发明专利

DE68912071D1 未知
公开(公告)号：DE68912071D1
公开(公告)日：1994-02-17
申请号：DE68912071
申请日：1989-10-27
申请人： CASIO COMPUTER CO LTD
发明人： MATSUMOTO HIROSHI P D DEV DIV , YAMADA HIROYASU P D DEV DIV HA , YAMAMURA NOBUYUKI P D DEV DIV , SHIMOMAKI SHINICHI P D DEV DIV , KONYA NAOHIRO P D DEV DIV HAMU , BABA KYUYA P D DEV DIV HAMURA
IPC分类号： H01L27/115 , H01L29/792 , G11C11/34 , G11C17/00 , H01L29/62
摘要： A memory element is formed of a thin film transistor. The thin film transistor has a semiconductor layer (4), a source electrode (6) electrically connected to the semiconductor layer, a drain electrode (7) electrically connected to the semiconductor layer and formed separately from the source electrode, a gate electrode (2) for controlling formation of a channel of the semiconductor layer, and a gate insulation film (3) for isolating the gate electrode (2) and the semiconductor layer (4) from each other and causing a hysteresis in the relation between the drain current and the gate circuit. The insulation film is a silicon nitride film whose composition ratio of silicon to nitrogen is in a range of approx. 0.85 to 1.1. According to this invention, the relation between the gate voltage and the drain current can be set to have a hysteresis. Therefore, the thin film transistor can be used as a memory element. Further, according to this invention, data can be written, erased and read out by selectively applying an electric field to the gate insulation film. Therefore, the thin film transistor can be used as a memory element.

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