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    • 1. 发明授权
    • Semiconductor memory device having improved connecting structure of bit
line and memory cell
    • 半导体存储器件具有改进的位线和存储单元的连接结构
    • US4953125A
    • 1990-08-28
    • US173749
    • 1988-03-25
    • Yoshinori OkumuraAkihiko OhsakiKazuyuki SugaharaTatsuhiko Ikeda
    • Yoshinori OkumuraAkihiko OhsakiKazuyuki SugaharaTatsuhiko Ikeda
    • H01L29/41H01L21/8242H01L27/10H01L27/108
    • H01L27/10829
    • A semiconductor memory device includes a first trench serving as a memory cell formed in a p type semiconductor substrate, a first n type semiconductor region formed adjacent to the trench region and on the major surface of the semiconductor substrate, a conductive layer serving as an electron active region formed adjacent to the first n type region and on the major surface of the semiconductor substrate, a second n type semiconductor region formed adjacent to the electron active region and on the major surface of the semiconductor substrate, a second trench formed adjacent to the second n type semiconductor region in the major surface of the semiconductor substrate which is shallower than the first trench, an interconnection layer serving as a bit line formed in a self-aligning manner in the sidewall portion of the second trench which is shallower than the first trench and a gate electrode serving as a word line formed in the upper portion of the conductive layer through an oxide film.
    • 半导体存储器件包括用作形成在p型半导体衬底中的存储单元的第一沟槽,与沟槽区相邻并且在半导体衬底的主表面上形成的第一n型半导体区,用作电子活性的导电层 形成在与第一n型区域相邻并且在半导体衬底的主表面上形成的第二n型半导体区域,形成在与电子有源区相邻并且在半导体衬底的主表面上,第二沟槽, 在半导体衬底的主表面上比第一沟槽浅的n型半导体区域,在第二沟槽的侧壁部分中以自对准的方式形成的位线的互连层比第一沟槽浅 以及用作通过氧化膜形成在导电层的上部的字线的栅电极 。