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1. 发明授权

US08736617B2 Hybrid graphic display 有权
标题翻译：混合图形显示
公开(公告)号：US08736617B2
公开(公告)日：2014-05-27
申请号：US12185698
申请日：2008-08-04
申请人： Stephen Lew , Bruce R. Intihar , Abraham B. de Waal , David G. Reed , Tony Tamasi , David Wyatt , Franck R. Diard , Brad Simeral
发明人： Stephen Lew , Bruce R. Intihar , Abraham B. de Waal , David G. Reed , Tony Tamasi , David Wyatt , Franck R. Diard , Brad Simeral
IPC分类号： G06F15/16 , G06F15/80
CPC分类号： G06T1/20
摘要： A method of displaying graphics data is described. The method involves accessing the graphics data in a memory subsystem associated with one graphics subsystem. The graphics data is transmitted to a second graphics subsystem, where it is displayed on a monitor coupled to the second graphics subsystem.
摘要翻译：描述显示图形数据的方法。该方法涉及访问与一个图形子系统相关联的存储器子系统中的图形数据。图形数据被发送到第二图形子系统，其中它显示在耦合到第二图形子系统的监视器上。

2. 发明申请

US20100026692A1 HYBRID GRAPHIC DISPLAY 有权
标题翻译：混合图形显示
公开(公告)号：US20100026692A1
公开(公告)日：2010-02-04
申请号：US12185698
申请日：2008-08-04
申请人： Stephen Lew , Bruce R. Intihar , Abraham B. de Waal , David G. Reed , Tony Tamasi , David Wyatt , Franck R. Diard , Brad Simeral
发明人： Stephen Lew , Bruce R. Intihar , Abraham B. de Waal , David G. Reed , Tony Tamasi , David Wyatt , Franck R. Diard , Brad Simeral
IPC分类号： G06T1/20
CPC分类号： G06T1/20
摘要： A method of displaying graphics data is described. The method involves accessing the graphics data in a memory subsystem associated with one graphics subsystem. The graphics data is transmitted to a second graphics subsystem, where it is displayed on a monitor coupled to the second graphics subsystem.
摘要翻译：描述显示图形数据的方法。该方法涉及访问与一个图形子系统相关联的存储器子系统中的图形数据。图形数据被发送到第二图形子系统，其中它显示在耦合到第二图形子系统的监视器上。

3. 发明申请

US20060095677A1 System, apparatus and method for issuing predictions from an inventory to access a memory 有权
标题翻译：从库存发出预测以访问存储器的系统，装置和方法
公开(公告)号：US20060095677A1
公开(公告)日：2006-05-04
申请号：US10920610
申请日：2004-08-17
申请人： Ziyad Hakura , Brian Langendorf , Stefano Pescador , Radoslay Danilak , Brad Simeral
发明人： Ziyad Hakura , Brian Langendorf , Stefano Pescador , Radoslay Danilak , Brad Simeral
IPC分类号： G06F12/00
CPC分类号： G06F9/3802 , G06F9/383 , G06F9/3832
摘要： A system, apparatus, and method are disclosed for managing predictive accesses to memory. In one embodiment, an exemplary apparatus is configured as a prediction inventory that stores predictions in a number of queues. Each queue is configured to maintain predictions until a subset of the predictions is either issued to access a memory or filtered out as redundant. In another embodiment, an exemplary prefetcher predicts accesses to a memory. The prefetcher comprises a speculator for generating a number of predictions and a prediction inventory, which includes queues each configured to maintain a group of items. The group of items typically includes a triggering address that corresponds to the group. Each item of the group is of one type of prediction. Also, the prefetcher includes an inventory filter configured to compare the number of predictions against one of the queues having the either the same or different prediction type as the number of predictions.
摘要翻译：公开了一种用于管理对存储器的预测访问的系统，装置和方法。在一个实施例中，示例性装置被配置为在多个队列中存储预测的预测库存。每个队列被配置为维持预测，直到预测的一部分被发出以访问存储器或被过滤掉为冗余。在另一个实施例中，示例性预取器预测对存储器的访问。预取器包括用于生成多个预测的投机者和预测库存，其包括各自配置为维护一组物品的队列。该组项通常包括对应于组的触发地址。该组的每个项目都是一种类型的预测。此外，预取器还包括库存过滤器，其被配置为将预测数量与具有与预测数量相同或不同的预测类型的一个队列进行比较。

4. 发明授权

US09823990B2 System and process for accounting for aging effects in a computing device 有权
公开(公告)号：US09823990B2
公开(公告)日：2017-11-21
申请号：US13604283
申请日：2012-09-05
申请人： Brad Simeral
发明人： Brad Simeral
IPC分类号： G06F11/30 , G06F17/50 , G06F11/34 , G01R31/00 , G06F17/00 , G01R31/28
CPC分类号： G06F11/3058 , G01R31/00 , G01R31/2855 , G06F11/3003 , G06F11/3409 , G06F17/00 , G06F17/5009 , G06F2217/76
摘要： Embodiments of the claimed subject matter are directed to methods and systems that allow tracking and accounting of wear and other aging effects in integrated circuits and products which include integrated circuits over time, and the dynamic adjustment of operating conditions to increase or decrease wear in response to the accumulated wear relative to the expected wear during the lifetime of the circuit and/or product.

5. 发明申请

US20140068298A1 SYSTEM AND PROCESS FOR ACCOUNTING FOR AGING EFFECTS IN A COMPUTING DEVICE 有权
标题翻译：用于计算设备中老化影响的系统和过程
公开(公告)号：US20140068298A1
公开(公告)日：2014-03-06
申请号：US13604283
申请日：2012-09-05
申请人： Brad Simeral
发明人： Brad Simeral
IPC分类号： G06F1/32 , G06F1/26 , G06F9/50
CPC分类号： G06F11/3058 , G01R31/00 , G01R31/2855 , G06F11/3003 , G06F11/3409 , G06F17/00 , G06F17/5009 , G06F2217/76
摘要： Embodiments of the claimed subject matter are directed to methods and systems that allow tracking and accounting of wear and other aging effects in integrated circuits and products which include integrated circuits over time, and the dynamic adjustment of operating conditions to increase or decrease wear in response to the accumulated wear relative to the expected wear during the lifetime of the circuit and/or product.
摘要翻译：所要求保护的主题的实施例涉及允许跟踪和计算集成电路和产品中的磨损和其他老化效应的方法和系统，其包括随时间的集成电路，以及响应于在电路和/或产品的寿命期间相对于预期磨损的累积磨损。

6. 发明申请

US20070143640A1 Data path controller with integrated power management to manage power consumption of a computing device and its components 有权
标题翻译：具有集成电源管理功能的数据路径控制器，用于管理计算设备及其组件的功耗
公开(公告)号：US20070143640A1
公开(公告)日：2007-06-21
申请号：US11305816
申请日：2005-12-16
申请人： Brad Simeral , David Reed , Dmitry Vyshetsky , Roman Surgutchick , Robert Chapman , Joshua Titus , Anand Srinivasan , Hari Krishnan
发明人： Brad Simeral , David Reed , Dmitry Vyshetsky , Roman Surgutchick , Robert Chapman , Joshua Titus , Anand Srinivasan , Hari Krishnan
IPC分类号： G06F1/26
CPC分类号： G06F1/28 , G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A data path controller, a computer device, an apparatus and a method are disclosed for integrating power management functions into a data path controller to manage power consumed by processors and peripheral devices. By embedding power management within the data path controller, the data path controller can advantageously modify its criteria in-situ so that it can adapt its power management actions in response to changes in processors and peripheral devices. In addition, the data path controller includes a power-managing interface that provides power-monitoring ports for monitoring and/or quantifying power consumption of various components. In one embodiment, the data path controller includes a power-monitoring interface for selectably monitoring power of a component. It also includes a controller for adjusting operational characteristics of the component for modifying the power consumed by the component to comply with a performance profile, which generally specifies permissible power consumption levels for the component.
摘要翻译：公开了一种数据路径控制器，计算机设备，装置和方法，用于将电源管理功能集成到数据路径控制器中，以管理由处理器和外围设备消耗的功率。通过在数据路径控制器内部嵌入电源管理，数据路径控制器可以有利地在现场修改其标准，使得其能够根据处理器和外围设备的变化来适应其功率管理动作。此外，数据路径控制器包括功率管理接口，其提供用于监视和/或量化各种组件的功耗的功率监控端口。在一个实施例中，数据路径控制器包括用于可选地监视组件的功率的功率监视接口。它还包括用于调整部件的操作特性的控制器，用于修改部件消耗的功率以符合性能曲线，其通常指定部件的允许功率消耗水平。

7. 发明申请

US20060041723A1 System, apparatus and method for predicting accesses to a memory 有权
标题翻译：用于预测对存储器的访问的系统，装置和方法
公开(公告)号：US20060041723A1
公开(公告)日：2006-02-23
申请号：US10921026
申请日：2004-08-17
申请人： Ziyad Hakura , Brian Langendorf , Stefano Pescador , Radoslav Danilak , Brad Simeral
发明人： Ziyad Hakura , Brian Langendorf , Stefano Pescador , Radoslav Danilak , Brad Simeral
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F12/0875 , G06F2212/6026
摘要： A system, apparatus, and method are disclosed for predicting accesses to memory. In one embodiment, an exemplary apparatus comprises a processor configured to execute program instructions and process program data, a memory including the program instructions and the program data, and a memory processor. The memory processor can include a speculator configured to receive an address containing the program instructions or the program data. Such a speculator can comprise a sequential predictor for generating a configurable number of sequential addresses. The speculator can also include a nonsequential predictor configured to associate a subset of addresses to the address and to predict a group of addresses based on at least one address of the subset, wherein at least one address of the subset is unpatternable to the address.
摘要翻译：公开了一种用于预测对存储器的访问的系统，装置和方法。在一个实施例中，示例性设备包括被配置为执行程序指令和处理程序数据的处理器，包括程序指令和程序数据的存储器以及存储器处理器。存储器处理器可以包括被配置为接收包含程序指令或程序数据的地址的投机器。这样的投机者可以包括用于生成可配置数量的顺序地址的顺序预测器。推测器还可以包括非顺序预测器，其被配置为将地址的子集与地址相关联，并且基于子集的至少一个地址来预测一组地址，其中该子集的至少一个地址对该地址是不可编程的。

8. 发明申请

US20060041722A1 System, apparatus and method for performing look-ahead lookup on predictive information in a cache memory 有权
标题翻译：用于对高速缓冲存储器中的预测信息进行预先查找的系统，装置和方法
公开(公告)号：US20060041722A1
公开(公告)日：2006-02-23
申请号：US10920995
申请日：2004-08-17
申请人： Ziyad Hakura , Radoslav Danilak , Brad Simeral , Brian Langendorf , Stefano Pescador , Dmitry Vyshetsky
发明人： Ziyad Hakura , Radoslav Danilak , Brad Simeral , Brian Langendorf , Stefano Pescador , Dmitry Vyshetsky
IPC分类号： G06F12/00
CPC分类号： G06F12/0862
摘要： A system, apparatus, and method are disclosed for storing predictions as well as examining and using one or more caches for anticipating accesses to a memory. In one embodiment, an exemplary apparatus is a prefetcher for managing predictive accesses with a memory. The prefetcher can include a speculator to generate a range of predictions, and multiple caches. For example, the prefetcher can include a first cache and a second cache to store predictions. An entry of the first cache is addressable by a first representation of an address from the range of predictions, whereas an entry of the second cache is addressable by a second representation of the address. The first and the second representations are compared in parallel against the stored predictions of either the first cache and the second cache, or both.
摘要翻译：公开了用于存储预测以及检查和使用一个或多个高速缓存以预测对存储器的访问的系统，装置和方法。在一个实施例中，示例性装置是用于管理具有存储器的预测访问的预取器。预取器可以包括一个投机者来生成一系列预测，以及多个高速缓存。例如，预取器可以包括第一缓存和第二高速缓存来存储预测。第一高速缓存的条目可由来自预测范围的地址的第一表示来寻址，而第二高速缓存的条目可由地址的第二表示寻址。将第一和第二表示与第一高速缓存和第二高速缓存或两者的存储的预测并行地进行比较。

9. 发明申请

US20060041721A1 System, apparatus and method for generating nonsequential predictions to access a memory 有权
标题翻译：用于生成访问存储器的不相关预测的系统，装置和方法
公开(公告)号：US20060041721A1
公开(公告)日：2006-02-23
申请号：US10920682
申请日：2004-08-17
申请人： Ziyad Hakura , Brian Langendorf , Stefano Pescador , Radoslav Danilak , Brad Simeral
发明人： Ziyad Hakura , Brian Langendorf , Stefano Pescador , Radoslav Danilak , Brad Simeral
IPC分类号： G06F12/00
CPC分类号： G06F12/0875 , G06F9/345 , G06F9/383 , G06F9/3832 , G06F12/0862
摘要： A system, apparatus, and method are disclosed for storing and prioritizing predictions to anticipate nonsequential accesses to a memory. In one embodiment, an exemplary apparatus is configured as a prefetcher for predicting accesses to a memory. The prefetcher includes a prediction generator configured to generate a prediction that is unpatternable to an address. Also, the prefetcher also can include a target cache coupled to the prediction generator to maintain the prediction in a manner that determines a priority for the prediction. In another embodiment, the prefetcher can also include a priority adjuster. The priority adjuster sets a priority for a prediction relative to other predictions. In some cases, the placement of the prediction is indicative of the priority relative to priorities for the other predictions. In yet another embodiment, the prediction generator uses the priority to determine that the prediction is to be generated before other predictions.
摘要翻译：公开了一种系统，装置和方法，用于存储预先确定对存储器的不连续访问的预测的优先级。在一个实施例中，示例性装置被配置为用于预测对存储器的访问的预取器。预取器包括被配置为生成对于地址是不可描述的预测的预测生成器。此外，预取器还可以包括耦合到预测发生器的目标高速缓存以以确定预测的优先级的方式来维持预测。在另一个实施例中，预取器还可以包括优先级调整器。优先级调整器设置预测相对于其他预测的优先级。在某些情况下，预测的放置表示相对于其他预测的优先级的优先级。在另一个实施例中，预测生成器使用优先级来确定在其它预测之前将产生预测。

10. 发明授权

US06957298B1 System and method for a high bandwidth-low latency memory controller 有权
标题翻译：高带宽低延迟存储器控制器的系统和方法
公开(公告)号：US06957298B1
公开(公告)日：2005-10-18
申请号：US10657957
申请日：2003-09-08
申请人： James M. Van Dyke , Nicholas J. Foskett , Brad Simeral , Sean Treichler
发明人： James M. Van Dyke , Nicholas J. Foskett , Brad Simeral , Sean Treichler
IPC分类号： G06F13/16 , G06F12/00
CPC分类号： G06F13/1642
摘要： A memory controller system is provided including a plurality of memory controller subsystems each coupled between memory and one of a plurality of computer components. Each memory controller subsystem includes at least one queue for managing pages in the memory. In use, each memory controller subsystem is capable of being loaded from the associated computer component independent of the state of the memory. Since high bandwidth and low latency are conflicting requirements in high performance memory systems, the present invention separates references from various computer components into multiple command streams. Each stream thus can hide activate bank preparation commands within its own stream for maximum bandwidth. A page context switch technique may be employed that allows instantaneous switching from one look ahead stream to another to allow low latency and high bandwidth while preserving maximum bank state from the previous stream.
摘要翻译：提供了存储器控制器系统，其包括多个存储器控制器子系统，每个存储器控制器子系统连接在存储器和多个计算机组件之一之间。每个存储器控制器子系统包括用于管理存储器中的页面的至少一个队列。在使用中，每个存储器控制器子系统能够独立于存储器的状态从相关联的计算机组件加载。由于高带宽和低延迟是高性能存储器系统中的冲突要求，本发明将来自各种计算机组件的引用分为多个命令流。因此，每个流可以隐藏在其自己的流内的激活银行准备命令以获得最大带宽。可以采用页面上下文切换技术，其允许从一个前瞻流到另一个的瞬时切换，以允许低等待时间和高带宽，同时保留来自先前流的最大库状态。

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