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1. 发明授权

US08069355B2 Data path controller with integrated power management to manage power consumption of a computing device and its components 有权
标题翻译：具有集成电源管理功能的数据路径控制器，用于管理计算设备及其组件的功耗
公开(公告)号：US08069355B2
公开(公告)日：2011-11-29
申请号：US12342865
申请日：2008-12-23
申请人： Brad W. Simeral , David G. Reed , Dmitry Vyshetsky , Roman Surgutchik , Robert William Chapman , Joshua Titus , Anand Srinivasan , Hari U. Krishnan
发明人： Brad W. Simeral , David G. Reed , Dmitry Vyshetsky , Roman Surgutchik , Robert William Chapman , Joshua Titus , Anand Srinivasan , Hari U. Krishnan
IPC分类号： G06F1/32
CPC分类号： G06F1/28 , G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A data path controller, a computer device, an apparatus and a method are disclosed for integrating power management functions into a data path controller to manage power consumed by processors and peripheral devices. By embedding power management within the data path controller, the data path controller can advantageously modify its criteria in-situ so that it can adapt its power management actions in response to changes in processors and peripheral devices. In addition, the data path controller includes a power-managing interface that provides power-monitoring ports for monitoring and/or quantifying power consumption of various components. In one embodiment, the data path controller includes a power-monitoring interface for selectably monitoring power of a component. It also includes a controller for adjusting operational characteristics of the component for modifying the power consumed by the component to comply with a performance profile, which generally specifies permissible power consumption levels for the component.
摘要翻译：公开了一种数据路径控制器，计算机设备，装置和方法，用于将电源管理功能集成到数据路径控制器中，以管理由处理器和外围设备消耗的功率。通过在数据路径控制器内部嵌入电源管理，数据路径控制器可以有利地在现场修改其标准，使得其能够根据处理器和外围设备的变化来适应其功率管理动作。此外，数据路径控制器包括功率管理接口，其提供用于监视和/或量化各种组件的功耗的功率监控端口。在一个实施例中，数据路径控制器包括用于可选地监视组件的功率的功率监视接口。它还包括用于调整部件的操作特性的控制器，用于修改部件消耗的功率以符合性能曲线，其通常指定部件的允许功率消耗水平。

2. 发明申请

US20110169845A1 SCREEN COMPRESSION FOR MOBILE APPLICATIONS 有权
标题翻译：用于移动应用的屏幕压缩
公开(公告)号：US20110169845A1
公开(公告)日：2011-07-14
申请号：US13050708
申请日：2011-03-17
申请人： Krishnan Sreenivas , Koen Bennebroek , Karthik Bhat , Stefano A. Pescador , David G. Reed , Brad W. Simeral , Edward M. Veeser
发明人： Krishnan Sreenivas , Koen Bennebroek , Karthik Bhat , Stefano A. Pescador , David G. Reed , Brad W. Simeral , Edward M. Veeser
IPC分类号： G06F13/14
CPC分类号： G09G5/363 , G09G2330/021 , G09G2340/02
摘要： One embodiment of the invention sets forth a technique for compressing and storing display data and optionally compressing and storing cursor data in a memory that is local to a graphics processing unit to reduce the power consumed by a mobile computing device when refreshing the screen. Compressing the display data and optionally the cursor data also reduces the relative cost of the invention by reducing the size of the local memory relative to the size that would be necessary if the display data were stored locally in uncompressed form. Thus, the invention may improve mobile computing device battery life, while keeping additional costs low.
摘要翻译：本发明的一个实施例提出了一种用于压缩和存储显示数据的技术，并且可选地将光标数据压缩并存储在图形处理单元本地的存储器中，以减少当刷新屏幕时由移动计算设备消耗的功率。如果显示数据以非压缩形式本地存储，则压缩显示数据和可选的光标数据也可以通过相对于所需尺寸减小本地存储器的大小来降低本发明的相对成本。因此，本发明可以改善移动计算设备的电池寿命，同时保持较低的成本。

3. 发明授权

US07571296B2 Memory controller-adaptive 1T/2T timing control 有权
标题翻译：内存控制器自适应1T / 2T定时控制
公开(公告)号：US07571296B2
公开(公告)日：2009-08-04
申请号：US10987022
申请日：2004-11-11
申请人： David G. Reed
发明人： David G. Reed
IPC分类号： G06F13/00 , G06F13/36 , G06F13/38
CPC分类号： G06F13/1684
摘要： Circuits, methods, and apparatus that adaptively control 1T and 2T timing for a memory controller interface. An embodiment of the present invention provides a first memory interface as well as an additional memory interface, each having a number of address and control lines. The address and control lines of the redundant memory interface may be individually enabled and disabled. If a line in the additional interface is enabled, it and its corresponding line in the first interface drive a reduced load and may operate at the higher 1T data rate. If a line in the additional interface is disabled, then its corresponding line in the first interface drives a higher load and may operate at the slower 2T data rate. In either case, the operating speed of the interface may also be considered in determining whether each line operates with 1T or 2T timing.
摘要翻译：自适应地控制1T和2T定时的存储器控制器接口的电路，方法和装置。本发明的实施例提供了第一存储器接口以及附加存储器接口，每个存储器接口具有多个地址和控制线。可以单独启用和禁用冗余存储器接口的地址和控制线。如果附加接口中的一条线路被使能，那么其第一个接口中的线路和相应的线路将减少负载，并可能以较高的1T数据速率工作。如果附加接口中的一条线路被禁用，则其第一个接口中的相应线路驱动较高的负载，并且可能以较慢的2T数据速率运行。在任一种情况下，在确定每条线路是否以1T或2T定时运行时，也可考虑接口的工作速度。

4. 发明申请

US20090089477A1 DEADLOCK AVOIDANCE IN A BUS FABRIC 有权
标题翻译：在一个公共汽车织物上的死亡避风
公开(公告)号：US20090089477A1
公开(公告)日：2009-04-02
申请号：US12330515
申请日：2008-12-09
申请人： David G. Reed
发明人： David G. Reed
IPC分类号： G06F13/372
CPC分类号： G06F13/4036 , G06F13/1642
摘要： Circuits, apparatus, and methods for avoiding deadlock conditions in a bus fabric. One exemplary embodiment provides an address decoder for determining whether a received posted request is a peer-to-peer request. If it is, the posted request is sent as a non-posted request. A limit on the number of pending non-posted requests is maintained and not exceed, such that deadlock is avoided. Another exemplary embodiment provides an arbiter that tracks a number of pending posted requests. When the number pending posted requests reaches a predetermined or programmable level, a Block Peer-to-Peer signal is sent to the arbiter's clients, again avoiding deadlock.
摘要翻译：用于避免总线结构中死锁状况的电路，装置和方法。一个示例性实施例提供了一种地址解码器，用于确定接收到的发送的请求是否是对等请求。如果是，发布的请求将作为未发布的请求发送。对待处理的未发布的请求数量的限制将保持不超过，从而避免死锁。另一示例性实施例提供了一种仲裁器，其跟踪多个未决发布的请求。当等待发送的请求数量达到预定或可编程的级别时，块对等信号被发送给仲裁者的客户端，同时避免死锁。

5. 发明申请

US20090083506A1 Method and system for memory thermal load sharing using memory on die termination 有权
标题翻译：使用存储器进行存储器热负载共享的方法和系统
公开(公告)号：US20090083506A1
公开(公告)日：2009-03-26
申请号：US12005968
申请日：2007-12-28
申请人： David G. Reed , Brad W. Simeral , Roman Surgutchik , Joshua Titus
发明人： David G. Reed , Brad W. Simeral , Roman Surgutchik , Joshua Titus
IPC分类号： G06F12/16 , G11C99/00
CPC分类号： G11C7/1051 , G11C7/04 , G11C7/1057 , G11C7/1078 , G11C7/109
摘要： Memory component temperature information is used to implement a method for ODT (on die termination) thermal load management. A respective temperature of a plurality of memory components are accessed, and based on this temperature, an ODT cycle is directed to a first of the memory components to avoid imposing a thermal load from the ODT cycle on a second of the memory components.
摘要翻译：内存组件温度信息用于实现用于ODT（终端）热负载管理的方法。访问多个存储器组件的相应温度，并且基于该温度，ODT周期针对第一存储器组件以避免在第二存储器组件上施加来自ODT周期的热负载。

6. 发明授权

US07478189B2 Deadlock avoidance in a bus fabric 有权
标题翻译：总线架构中的死锁避免
公开(公告)号：US07478189B2
公开(公告)日：2009-01-13
申请号：US11673971
申请日：2007-02-12
申请人： David G. Reed
发明人： David G. Reed
IPC分类号： G06F13/36 , G06F13/00
CPC分类号： G06F13/4036 , G06F13/1642
摘要： Circuits, apparatus, and methods for avoiding deadlock conditions in a bus fabric. One exemplary embodiment provides an address decoder for determining whether a received posted request is a peer-to-peer request. If it is, the posted request is sent as a non-posted request. A limit on the number of pending non-posted requests is maintained and not exceed, such that deadlock is avoided. Another exemplary embodiment provides an arbiter that tracks a number of pending posted requests. When the number pending posted requests reaches a predetermined or programmable level, a Block Peer-to-Peer signal is sent to the arbiter's clients, again avoiding deadlock.
摘要翻译：用于避免总线结构中死锁状况的电路，装置和方法。一个示例性实施例提供了一种地址解码器，用于确定接收到的发送的请求是否是对等请求。如果是，发布的请求将作为未发布的请求发送。对待处理的未发布的请求数量的限制将保持不超过，从而避免死锁。另一示例性实施例提供了一种仲裁器，其跟踪多个未决发布的请求。当等待发送的请求数量达到预定或可编程的级别时，块对等信号被发送给仲裁者的客户端，同时避免死锁。

7. 发明授权

US07287145B1 System, apparatus and method for reclaiming memory holes in memory composed of identically-sized memory devices 有权
标题翻译：用于回收由相同大小的存储器件组成的存储器中的存储器孔的系统，装置和方法
公开(公告)号：US07287145B1
公开(公告)日：2007-10-23
申请号：US11012006
申请日：2004-12-13
申请人： Brad W. Simeral , Sean Jeffrey Treichler , David G. Reed , Roman Surgutchik
发明人： Brad W. Simeral , Sean Jeffrey Treichler , David G. Reed , Roman Surgutchik
IPC分类号： G06F9/26 , G06F9/34 , G06F12/00
CPC分类号： G06F12/0223 , G06F12/06
摘要： A system, apparatus, and method are disclosed for increasing the physical memory size accessible to a processor, at least in part, by reclaiming physical address space typically associated with addresses of a restricted linear address space (i.e., addresses that are otherwise unusable by the processor as system memory). In one embodiment, an exemplary memory controller redirects a linear address associated with a range of addresses to access a reclaimed memory hole. The memory controller includes an address translator configured to determine an amount of restricted addresses and to establish a baseline address identified as a first number being a first integer power of 2. The range of addresses can be located at another address identified as a second number being a second integer power of 2. As such, the address translator translates the linear address into a translated address associated with the reclaimed memory hole based on the baseline address.
摘要翻译：公开了一种用于增加处理器可访问的物理存储器大小的系统，装置和方法，至少部分地通过回收通常与受限线性地址空间的地址相关联的物理地址空间（即，否则不能由处理器作为系统内存）。在一个实施例中，示例性存储器控制器重定向与一系列地址相关联的线性地址以访问再生存储器孔。存储器控制器包括地址转换器，其被配置为确定受限地址的量并且建立被标识为第一个数字的基准地址，该第一个数字是第一个整数2的幂。地址的范围可以位于被标识为第二个数字的另一个地址第二整数幂为2.因此，地址转换器基于基线地址将线性地址转换为与再生存储器空穴相关联的翻译地址。

8. 发明授权

US07240179B1 System, apparatus and method for reclaiming memory holes in memory composed of arbitrarily-sized memory devices 有权
标题翻译：用于回收由任意大小的存储器件组成的存储器中的存储器孔的系统，装置和方法
公开(公告)号：US07240179B1
公开(公告)日：2007-07-03
申请号：US11012025
申请日：2004-12-13
申请人： Sean Jeffrey Treichler , Brad W. Simeral , David G. Reed , Roman Surgutchik
发明人： Sean Jeffrey Treichler , Brad W. Simeral , David G. Reed , Roman Surgutchik
IPC分类号： G06F9/26 , G06F9/34 , G06F12/00
CPC分类号： G06F12/023 , G06F12/0292
摘要： A system, apparatus, and method are disclosed for increasing the physical memory address space accessible to a processor, at least in part, by translating linear addresses associated with a memory hole into a subset of physical memory addresses that otherwise is inaccessible as system memory by a processor. In one embodiment, a memory controller reclaims memory holes in a system memory divided into ranges of linear addresses, where the system memory includes a number of arbitrarily-sized memory devices. The memory controller includes a memory configuration evaluator configured to determine a translated memory hole size for a memory hole, the memory hole including restricted linear addresses that translate into a subset of physical addresses. Also, memory configuration evaluator can be configured to form adjusted ranges to translate at least one linear address into a subset of physical addresses. As such, the system memory increases by at least the subset of physical addresses.
摘要翻译：公开了一种用于增加处理器可访问的物理存储器地址空间的系统，装置和方法，至少部分地通过将与存储器孔相关联的线性地址转换成物理存储器地址的子集，否则该物理存储器地址的子集不能作为系统存储器访问一个处理器在一个实施例中，存储器控制器回收分成线性地址范围的系统存储器中的存储器空间，其中系统存储器包括多个任意大小的存储器件。存储器控制器包括被配置为确定用于存储器孔的转换的存储器孔尺寸的存储器配置评估器，所述存储器孔包括转换为物理地址子集的受限线性地址。此外，存储器配置评估器可以被配置为形成调整的范围，以将至少一个线性地址转换为物理地址的子集。因此，系统存储器至少增加物理地址的子集。

9. 发明授权

US07054987B1 Apparatus, system, and method for avoiding data writes that stall transactions in a bus interface 有权
标题翻译：用于避免在总线接口中停止事务的数据写入的装置，系统和方法
公开(公告)号：US07054987B1
公开(公告)日：2006-05-30
申请号：US10741069
申请日：2003-12-19
申请人： David G. Reed , Brian K. Langendorf , Brad W. Simeral , Anand Srinivasan
发明人： David G. Reed , Brian K. Langendorf , Brad W. Simeral , Anand Srinivasan
IPC分类号： G06F13/00 , G06F13/14 , G06F13/38 , G06F11/00 , G06F12/00
CPC分类号： G06F13/16
摘要： A bus interface unit is adapted to receive transaction requests for at least two different targets. The bus interface unit monitors a capacity of a resource associated with servicing transaction requests to the targets, such as a posted write buffer. If a transaction request would fill the resource beyond a current remaining capacity of the resource such that the execution of other pipelined transactions would become stalled, the bus interface generates a retry response so that the request is retried at a later time, permitting other transactions to proceed while the resource drains.
摘要翻译：总线接口单元适于接收至少两个不同目标的交易请求。总线接口单元监视与针对目标的事务请求的服务相关联的资源的容量，例如已发布的写入缓冲器。如果事务请求将超过资源的当前剩余容量填充资源，使得其他流水线事务的执行将变得停滞，则总线接口产生重试响应，以便稍后重试该请求，允许其他事务在资源耗尽时继续进行。

10. 外观设计

USD494109S1 Walker 失效
标题翻译：沃克
公开(公告)号：USD494109S1
公开(公告)日：2004-08-10
申请号：US29188934
申请日：2003-08-25
申请人： Craig E. Karasin , Thomas J. Powers , David G. Reed
设计人： Craig E. Karasin , Thomas J. Powers , David G. Reed

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