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1. 发明申请

US20070088959A1 Chipset security offload engine 有权
标题翻译：芯片组安全卸载引擎
公开(公告)号：US20070088959A1
公开(公告)日：2007-04-19
申请号：US11304116
申请日：2005-12-14
申请人： Michael Cox , Henry Moreton , Brian Langendorf , David Reed
发明人： Michael Cox , Henry Moreton , Brian Langendorf , David Reed
IPC分类号： G06F12/14
CPC分类号： H04N21/4367 , G06F21/72 , H04N5/775 , H04N5/85 , H04N5/913 , H04N7/1675 , H04N21/4113 , H04N21/4122 , H04N21/42646 , H04N21/4325 , H04N2005/91364
摘要： A bridge is disclosed having a security engine. The bridge permit cryptographic services to be offloaded from a central processing unit to the bridge.
摘要翻译：公开了一种具有安全引擎的桥。该桥允许加密服务从中央处理单元卸载到桥。

2. 发明申请

US20060095677A1 System, apparatus and method for issuing predictions from an inventory to access a memory 有权
标题翻译：从库存发出预测以访问存储器的系统，装置和方法
公开(公告)号：US20060095677A1
公开(公告)日：2006-05-04
申请号：US10920610
申请日：2004-08-17
申请人： Ziyad Hakura , Brian Langendorf , Stefano Pescador , Radoslay Danilak , Brad Simeral
发明人： Ziyad Hakura , Brian Langendorf , Stefano Pescador , Radoslay Danilak , Brad Simeral
IPC分类号： G06F12/00
CPC分类号： G06F9/3802 , G06F9/383 , G06F9/3832
摘要： A system, apparatus, and method are disclosed for managing predictive accesses to memory. In one embodiment, an exemplary apparatus is configured as a prediction inventory that stores predictions in a number of queues. Each queue is configured to maintain predictions until a subset of the predictions is either issued to access a memory or filtered out as redundant. In another embodiment, an exemplary prefetcher predicts accesses to a memory. The prefetcher comprises a speculator for generating a number of predictions and a prediction inventory, which includes queues each configured to maintain a group of items. The group of items typically includes a triggering address that corresponds to the group. Each item of the group is of one type of prediction. Also, the prefetcher includes an inventory filter configured to compare the number of predictions against one of the queues having the either the same or different prediction type as the number of predictions.
摘要翻译：公开了一种用于管理对存储器的预测访问的系统，装置和方法。在一个实施例中，示例性装置被配置为在多个队列中存储预测的预测库存。每个队列被配置为维持预测，直到预测的一部分被发出以访问存储器或被过滤掉为冗余。在另一个实施例中，示例性预取器预测对存储器的访问。预取器包括用于生成多个预测的投机者和预测库存，其包括各自配置为维护一组物品的队列。该组项通常包括对应于组的触发地址。该组的每个项目都是一种类型的预测。此外，预取器还包括库存过滤器，其被配置为将预测数量与具有与预测数量相同或不同的预测类型的一个队列进行比较。

3. 发明授权

US5630094A Integrated bus bridge and memory controller that enables data streaming to a shared memory of a computer system using snoop ahead transactions 失效
标题翻译：集成总线桥接器和存储器控制器，使数据可以使用前置处理事务进行数据流传输到计算机系统的共享存储器
公开(公告)号：US5630094A
公开(公告)日：1997-05-13
申请号：US375972
申请日：1995-01-20
申请人： George Hayek , Ali S. Oztaskin , Brian Langendorf , Bruce Young
发明人： George Hayek , Ali S. Oztaskin , Brian Langendorf , Bruce Young
IPC分类号： G06F12/08 , G06F13/16 , G06F13/40 , G06F13/00 , G06F3/00
CPC分类号： G06F12/0835 , G06F13/1684 , G06F13/4059
摘要： A computer system having an integrated bus bridge and memory controller circuit and method for enabling access to a shared memory with high bandwidth data streaming are disclosed. The integrated bus bridge and memory controller circuit performs a series of snoop ahead transactions over a first bus during access transactions to the shared memory that originate over a second bus and thereby enables high bandwidth data streaming on the second bus. The integrated bus bridge and memory controller circuit includes a peripheral write buffer that buffers write data received over the second bus and that stores a snoop done flag for the write data that indicates whether a corresponding snoop ahead transaction for the write data is complete. The integrated bus bridge and memory controller circuit further includes a peripheral read prefetch buffer that prefetches read data during read transactions over the second bus only after a corresponding snoop ahead transaction for the read data is complete.
摘要翻译：公开了具有集成总线桥和存储器控制器电路和方法的计算机系统，该电路和方法能够访问具有高带宽数据流的共享存储器。集成总线桥接器和存储器控制器电路在通过第二总线发起到共享存储器的访问事务期间通过第一总线执行一系列前置提前事务，从而实现第二总线上的高带宽数据流传输。集成总线桥接器和存储器控制器电路包括外围写入缓冲器，其缓冲通过第二总线接收的写入数据，并且存储用于写入数据的窥探完成标志，该数据指示用于写入数据的对应的窥探事件是否完成。集成总线桥接器和存储器控制器电路还包括一个外设读取预取缓冲器，只有在读取数据的相应窥探事件完成之后，才能通过第二总线在读取事务期间预取读取数据。

4. 发明申请

US20050128203A1 System and method for accelerating a special purpose processor 有权
标题翻译：用于加速专用处理器的系统和方法
公开(公告)号：US20050128203A1
公开(公告)日：2005-06-16
申请号：US10732445
申请日：2003-12-11
申请人： Jen-Hsun Huang , Michael Cox , Ziyad Hakura , John Montrym , Brad Simeral , Brian Langendorf , Blanton Kephart , Franck Diard
发明人： Jen-Hsun Huang , Michael Cox , Ziyad Hakura , John Montrym , Brad Simeral , Brian Langendorf , Blanton Kephart , Franck Diard
IPC分类号： G06T1/00 , G06T1/20 , G06T15/00
CPC分类号： G06T1/20 , G06T15/005
摘要： Embodiments of the invention accelerate at least one special purpose processor, such as a GPU, or a driver managing a special purpose processor, by using at least one co-processor. Advantageously, embodiments of the invention are fault-tolerant in that the at least one GPU or other special purpose processor is able to execute all computations, although perhaps at a lower level of performance, if the at least one co-processor is rendered inoperable. The co-processor may also be used selectively, based on performance considerations.
摘要翻译：本发明的实施例通过使用至少一个协处理器来加速至少一个专用处理器，例如GPU或者管理专用处理器的驱动器。有利地，本发明的实施例是容错的，因为如果使至少一个协处理器变得不可操作，则至少一个GPU或其他专用处理器能够执行所有计算，尽管可能处于较低的性能水平。可以基于性能考虑，有选择地使用协处理器。

5. 发明申请

US20060041722A1 System, apparatus and method for performing look-ahead lookup on predictive information in a cache memory 有权
标题翻译：用于对高速缓冲存储器中的预测信息进行预先查找的系统，装置和方法
公开(公告)号：US20060041722A1
公开(公告)日：2006-02-23
申请号：US10920995
申请日：2004-08-17
申请人： Ziyad Hakura , Radoslav Danilak , Brad Simeral , Brian Langendorf , Stefano Pescador , Dmitry Vyshetsky
发明人： Ziyad Hakura , Radoslav Danilak , Brad Simeral , Brian Langendorf , Stefano Pescador , Dmitry Vyshetsky
IPC分类号： G06F12/00
CPC分类号： G06F12/0862
摘要： A system, apparatus, and method are disclosed for storing predictions as well as examining and using one or more caches for anticipating accesses to a memory. In one embodiment, an exemplary apparatus is a prefetcher for managing predictive accesses with a memory. The prefetcher can include a speculator to generate a range of predictions, and multiple caches. For example, the prefetcher can include a first cache and a second cache to store predictions. An entry of the first cache is addressable by a first representation of an address from the range of predictions, whereas an entry of the second cache is addressable by a second representation of the address. The first and the second representations are compared in parallel against the stored predictions of either the first cache and the second cache, or both.
摘要翻译：公开了用于存储预测以及检查和使用一个或多个高速缓存以预测对存储器的访问的系统，装置和方法。在一个实施例中，示例性装置是用于管理具有存储器的预测访问的预取器。预取器可以包括一个投机者来生成一系列预测，以及多个高速缓存。例如，预取器可以包括第一缓存和第二高速缓存来存储预测。第一高速缓存的条目可由来自预测范围的地址的第一表示来寻址，而第二高速缓存的条目可由地址的第二表示寻址。将第一和第二表示与第一高速缓存和第二高速缓存或两者的存储的预测并行地进行比较。

6. 发明申请

US20060041721A1 System, apparatus and method for generating nonsequential predictions to access a memory 有权
标题翻译：用于生成访问存储器的不相关预测的系统，装置和方法
公开(公告)号：US20060041721A1
公开(公告)日：2006-02-23
申请号：US10920682
申请日：2004-08-17
申请人： Ziyad Hakura , Brian Langendorf , Stefano Pescador , Radoslav Danilak , Brad Simeral
发明人： Ziyad Hakura , Brian Langendorf , Stefano Pescador , Radoslav Danilak , Brad Simeral
IPC分类号： G06F12/00
CPC分类号： G06F12/0875 , G06F9/345 , G06F9/383 , G06F9/3832 , G06F12/0862
摘要： A system, apparatus, and method are disclosed for storing and prioritizing predictions to anticipate nonsequential accesses to a memory. In one embodiment, an exemplary apparatus is configured as a prefetcher for predicting accesses to a memory. The prefetcher includes a prediction generator configured to generate a prediction that is unpatternable to an address. Also, the prefetcher also can include a target cache coupled to the prediction generator to maintain the prediction in a manner that determines a priority for the prediction. In another embodiment, the prefetcher can also include a priority adjuster. The priority adjuster sets a priority for a prediction relative to other predictions. In some cases, the placement of the prediction is indicative of the priority relative to priorities for the other predictions. In yet another embodiment, the prediction generator uses the priority to determine that the prediction is to be generated before other predictions.
摘要翻译：公开了一种系统，装置和方法，用于存储预先确定对存储器的不连续访问的预测的优先级。在一个实施例中，示例性装置被配置为用于预测对存储器的访问的预取器。预取器包括被配置为生成对于地址是不可描述的预测的预测生成器。此外，预取器还可以包括耦合到预测发生器的目标高速缓存以以确定预测的优先级的方式来维持预测。在另一个实施例中，预取器还可以包括优先级调整器。优先级调整器设置预测相对于其他预测的优先级。在某些情况下，预测的放置表示相对于其他预测的优先级的优先级。在另一个实施例中，预测生成器使用优先级来确定在其它预测之前将产生预测。

7. 发明授权

US6115796A Integrated bus bridge and memory controller that enables data streaming to a shared memory of a computer system using snoop ahead transactions 失效
标题翻译：集成总线桥接器和存储器控制器，使数据可以使用前置处理事务进行数据流传输到计算机系统的共享存储器
公开(公告)号：US6115796A
公开(公告)日：2000-09-05
申请号：US806524
申请日：1997-02-24
申请人： George Hayek , Ali S. Oztaskin , Brian Langendorf , Bruce Young
发明人： George Hayek , Ali S. Oztaskin , Brian Langendorf , Bruce Young
IPC分类号： G06F12/08 , G06F13/16 , G06F13/40 , G06F13/00 , G06F3/00
CPC分类号： G06F12/0835 , G06F13/1684 , G06F13/4059
摘要： A computer system having an integrated bus bridge and memory controller circuit and method for enabling access to a shared memory with high bandwidth data streaming are disclosed. The integrated bus bridge and memory controller circuit performs a series of snoop ahead transactions over a first bus during access transactions to the shared memory that originate over a second bus and thereby enables high bandwidth data streaming on the second bus. The integrated bus bridge and memory controller circuit includes a peripheral write buffer that buffers write data received over the second bus and that stores a snoop done flag for the write data that indicates whether a corresponding snoop ahead transaction for the write data is complete. The integrated bus bridge and memory controller circuit further includes a peripheral read prefetch buffer that prefetches read data during read transactions over the second bus only after a corresponding snoop ahead transaction for the read data is complete.
摘要翻译：公开了具有集成总线桥和存储器控制器电路和方法的计算机系统，该电路和方法能够访问具有高带宽数据流的共享存储器。集成总线桥接器和存储器控制器电路在通过第二总线发起到共享存储器的访问事务期间通过第一总线执行一系列前置提前事务，从而实现第二总线上的高带宽数据流传输。集成总线桥接器和存储器控制器电路包括外围写入缓冲器，其缓冲通过第二总线接收的写入数据，并且存储用于写入数据的窥探完成标志，该数据指示用于写入数据的对应的窥探事件是否完成。集成总线桥接器和存储器控制器电路还包括一个外设读取预取缓冲器，只有在读取数据的相应窥探事件完成之后，才能通过第二总线在读取事务期间预取读取数据。

8. 发明申请

US20060041723A1 System, apparatus and method for predicting accesses to a memory 有权
标题翻译：用于预测对存储器的访问的系统，装置和方法
公开(公告)号：US20060041723A1
公开(公告)日：2006-02-23
申请号：US10921026
申请日：2004-08-17
申请人： Ziyad Hakura , Brian Langendorf , Stefano Pescador , Radoslav Danilak , Brad Simeral
发明人： Ziyad Hakura , Brian Langendorf , Stefano Pescador , Radoslav Danilak , Brad Simeral
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F12/0875 , G06F2212/6026
摘要： A system, apparatus, and method are disclosed for predicting accesses to memory. In one embodiment, an exemplary apparatus comprises a processor configured to execute program instructions and process program data, a memory including the program instructions and the program data, and a memory processor. The memory processor can include a speculator configured to receive an address containing the program instructions or the program data. Such a speculator can comprise a sequential predictor for generating a configurable number of sequential addresses. The speculator can also include a nonsequential predictor configured to associate a subset of addresses to the address and to predict a group of addresses based on at least one address of the subset, wherein at least one address of the subset is unpatternable to the address.
摘要翻译：公开了一种用于预测对存储器的访问的系统，装置和方法。在一个实施例中，示例性设备包括被配置为执行程序指令和处理程序数据的处理器，包括程序指令和程序数据的存储器以及存储器处理器。存储器处理器可以包括被配置为接收包含程序指令或程序数据的地址的投机器。这样的投机者可以包括用于生成可配置数量的顺序地址的顺序预测器。推测器还可以包括非顺序预测器，其被配置为将地址的子集与地址相关联，并且基于子集的至少一个地址来预测一组地址，其中该子集的至少一个地址对该地址是不可编程的。

9. 发明授权

US06442632B1 System resource arbitration mechanism for a host bridge 有权
标题翻译：主机桥系统资源仲裁机制
公开(公告)号：US06442632B1
公开(公告)日：2002-08-27
申请号：US09662365
申请日：2000-09-13
申请人： George Hayek , Brian Langendorf , Aniruddha Kundu , Gary Solomon , Peter D. MacWilliams , James M. Dodd
发明人： George Hayek , Brian Langendorf , Aniruddha Kundu , Gary Solomon , Peter D. MacWilliams , James M. Dodd
IPC分类号： G06F1300
CPC分类号： G06F13/4031
摘要： A computer system is disclosed with a host bridge that arbitrates access to a system resource from a CPU via a host bus and from a set of bus agents via a peripheral bus. A separate set of priority classes are provided to the CPU and to the bus agents and programmable timers are included to tune system resource allocation between the host and processor busses.
摘要翻译：公开了一种计算机系统，其具有主机桥，其经由主机总线以及经由外围总线从一组总线代理仲裁对来自CPU的系统资源的访问。向CPU和总线代理提供了一组单独的优先级，并且包括可编程定时器来调整主机和处理器总线之间的系统资源分配。

10. 发明授权

US06212589B1 System resource arbitration mechanism for a host bridge 失效
标题翻译：主机桥系统资源仲裁机制
公开(公告)号：US06212589B1
公开(公告)日：2001-04-03
申请号：US08924209
申请日：1997-09-05
申请人： George Hayek , Brian Langendorf , Aniruddha Kundu , Gary Solomon , Peter D. MacWilliams , James M. Dodd
发明人： George Hayek , Brian Langendorf , Aniruddha Kundu , Gary Solomon , Peter D. MacWilliams , James M. Dodd
IPC分类号： G06F1300
CPC分类号： G06F13/4031
摘要： A computer system is disclosed with a host bridge that arbitrates access to a system resource from a CPU via a host bus and from a set of bus agents via a peripheral bus. A separate set of priority classes are provided to the CPU and to the bus agents and programmable timers are included to tune system resource allocation between the host and processor busses.
摘要翻译：公开了一种计算机系统，其具有主机桥，其经由主机总线以及经由外围总线从一组总线代理仲裁对来自CPU的系统资源的访问。向CPU和总线代理提供了一组单独的优先级，并且包括可编程定时器来调整主机和处理器总线之间的系统资源分配。

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