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1. 发明申请

US20060041722A1 System, apparatus and method for performing look-ahead lookup on predictive information in a cache memory 有权
标题翻译：用于对高速缓冲存储器中的预测信息进行预先查找的系统，装置和方法
公开(公告)号：US20060041722A1
公开(公告)日：2006-02-23
申请号：US10920995
申请日：2004-08-17
申请人： Ziyad Hakura , Radoslav Danilak , Brad Simeral , Brian Langendorf , Stefano Pescador , Dmitry Vyshetsky
发明人： Ziyad Hakura , Radoslav Danilak , Brad Simeral , Brian Langendorf , Stefano Pescador , Dmitry Vyshetsky
IPC分类号： G06F12/00
CPC分类号： G06F12/0862
摘要： A system, apparatus, and method are disclosed for storing predictions as well as examining and using one or more caches for anticipating accesses to a memory. In one embodiment, an exemplary apparatus is a prefetcher for managing predictive accesses with a memory. The prefetcher can include a speculator to generate a range of predictions, and multiple caches. For example, the prefetcher can include a first cache and a second cache to store predictions. An entry of the first cache is addressable by a first representation of an address from the range of predictions, whereas an entry of the second cache is addressable by a second representation of the address. The first and the second representations are compared in parallel against the stored predictions of either the first cache and the second cache, or both.
摘要翻译：公开了用于存储预测以及检查和使用一个或多个高速缓存以预测对存储器的访问的系统，装置和方法。在一个实施例中，示例性装置是用于管理具有存储器的预测访问的预取器。预取器可以包括一个投机者来生成一系列预测，以及多个高速缓存。例如，预取器可以包括第一缓存和第二高速缓存来存储预测。第一高速缓存的条目可由来自预测范围的地址的第一表示来寻址，而第二高速缓存的条目可由地址的第二表示寻址。将第一和第二表示与第一高速缓存和第二高速缓存或两者的存储的预测并行地进行比较。

2. 发明申请

US20060041723A1 System, apparatus and method for predicting accesses to a memory 有权
标题翻译：用于预测对存储器的访问的系统，装置和方法
公开(公告)号：US20060041723A1
公开(公告)日：2006-02-23
申请号：US10921026
申请日：2004-08-17
申请人： Ziyad Hakura , Brian Langendorf , Stefano Pescador , Radoslav Danilak , Brad Simeral
发明人： Ziyad Hakura , Brian Langendorf , Stefano Pescador , Radoslav Danilak , Brad Simeral
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F12/0875 , G06F2212/6026
摘要： A system, apparatus, and method are disclosed for predicting accesses to memory. In one embodiment, an exemplary apparatus comprises a processor configured to execute program instructions and process program data, a memory including the program instructions and the program data, and a memory processor. The memory processor can include a speculator configured to receive an address containing the program instructions or the program data. Such a speculator can comprise a sequential predictor for generating a configurable number of sequential addresses. The speculator can also include a nonsequential predictor configured to associate a subset of addresses to the address and to predict a group of addresses based on at least one address of the subset, wherein at least one address of the subset is unpatternable to the address.
摘要翻译：公开了一种用于预测对存储器的访问的系统，装置和方法。在一个实施例中，示例性设备包括被配置为执行程序指令和处理程序数据的处理器，包括程序指令和程序数据的存储器以及存储器处理器。存储器处理器可以包括被配置为接收包含程序指令或程序数据的地址的投机器。这样的投机者可以包括用于生成可配置数量的顺序地址的顺序预测器。推测器还可以包括非顺序预测器，其被配置为将地址的子集与地址相关联，并且基于子集的至少一个地址来预测一组地址，其中该子集的至少一个地址对该地址是不可编程的。

3. 发明申请

US20060041721A1 System, apparatus and method for generating nonsequential predictions to access a memory 有权
标题翻译：用于生成访问存储器的不相关预测的系统，装置和方法
公开(公告)号：US20060041721A1
公开(公告)日：2006-02-23
申请号：US10920682
申请日：2004-08-17
申请人： Ziyad Hakura , Brian Langendorf , Stefano Pescador , Radoslav Danilak , Brad Simeral
发明人： Ziyad Hakura , Brian Langendorf , Stefano Pescador , Radoslav Danilak , Brad Simeral
IPC分类号： G06F12/00
CPC分类号： G06F12/0875 , G06F9/345 , G06F9/383 , G06F9/3832 , G06F12/0862
摘要： A system, apparatus, and method are disclosed for storing and prioritizing predictions to anticipate nonsequential accesses to a memory. In one embodiment, an exemplary apparatus is configured as a prefetcher for predicting accesses to a memory. The prefetcher includes a prediction generator configured to generate a prediction that is unpatternable to an address. Also, the prefetcher also can include a target cache coupled to the prediction generator to maintain the prediction in a manner that determines a priority for the prediction. In another embodiment, the prefetcher can also include a priority adjuster. The priority adjuster sets a priority for a prediction relative to other predictions. In some cases, the placement of the prediction is indicative of the priority relative to priorities for the other predictions. In yet another embodiment, the prediction generator uses the priority to determine that the prediction is to be generated before other predictions.
摘要翻译：公开了一种系统，装置和方法，用于存储预先确定对存储器的不连续访问的预测的优先级。在一个实施例中，示例性装置被配置为用于预测对存储器的访问的预取器。预取器包括被配置为生成对于地址是不可描述的预测的预测生成器。此外，预取器还可以包括耦合到预测发生器的目标高速缓存以以确定预测的优先级的方式来维持预测。在另一个实施例中，预取器还可以包括优先级调整器。优先级调整器设置预测相对于其他预测的优先级。在某些情况下，预测的放置表示相对于其他预测的优先级的优先级。在另一个实施例中，预测生成器使用优先级来确定在其它预测之前将产生预测。

4. 发明授权

US07260686B2 System, apparatus and method for performing look-ahead lookup on predictive information in a cache memory 有权
标题翻译：用于对高速缓冲存储器中的预测信息进行预先查找的系统，装置和方法
公开(公告)号：US07260686B2
公开(公告)日：2007-08-21
申请号：US10920995
申请日：2004-08-17
申请人： Ziyad S. Hakura , Radoslav Danilak , Brad W. Simeral , Brian Keith Langendorf , Stefano A. Pescador , Dmitry Vyshetsky
发明人： Ziyad S. Hakura , Radoslav Danilak , Brad W. Simeral , Brian Keith Langendorf , Stefano A. Pescador , Dmitry Vyshetsky
IPC分类号： G06F12/00
CPC分类号： G06F12/0862
摘要： A system, apparatus, and method are disclosed for storing predictions as well as examining and using one or more caches for anticipating accesses to a memory. In one embodiment, an exemplary apparatus is a prefetcher for managing predictive accesses with a memory. The prefetcher can include a speculator to generate a range of predictions, and multiple caches. For example, the prefetcher can include a first cache and a second cache to store predictions. An entry of the first cache is addressable by a first representation of an address from the range of predictions, whereas an entry of the second cache is addressable by a second representation of the address. The first and the second representations are compared in parallel against the stored predictions of either the first cache and the second cache, or both.
摘要翻译：公开了用于存储预测以及检查和使用一个或多个高速缓存以预测对存储器的访问的系统，装置和方法。在一个实施例中，示例性装置是用于管理具有存储器的预测访问的预取器。预取器可以包括一个投机者来生成一系列预测，以及多个高速缓存。例如，预取器可以包括第一缓存和第二高速缓存来存储预测。第一高速缓存的条目可由来自预测范围的地址的第一表示来寻址，而第二高速缓存的条目可由地址的第二表示寻址。将第一和第二表示与第一高速缓存和第二高速缓存或两者的存储的预测并行地进行比较。

5. 发明授权

US09792074B2 System, method, and computer program product for interfacing one or more storage devices with a plurality of bridge chips 有权
公开(公告)号：US09792074B2
公开(公告)日：2017-10-17
申请号：US12498162
申请日：2009-07-06
申请人： Ross John Stenfort , Radoslav Danilak
发明人： Ross John Stenfort , Radoslav Danilak
IPC分类号： G06F3/00 , G06F3/06
CPC分类号： G06F3/0661 , G06F3/061 , G06F3/0674
摘要： A system, method, and computer program product are provided for interfacing one or more storage devices with a plurality of bridge chips. One or more storage devices are provided. Additionally, a plurality of bridge chips are provided. Furthermore, at least one multiplexing device is provided for interfacing the one or more storage devices with the plurality of bridge chips.

6. 发明授权

US09396104B1 Accessing compressed data of varying-sized quanta in non-volatile memory 有权
标题翻译：访问非易失性存储器中不同大小量子的压缩数据
公开(公告)号：US09396104B1
公开(公告)日：2016-07-19
申请号：US13053175
申请日：2011-03-21
申请人： Radoslav Danilak , Ladislav Steffko , Rodney Norman Mullendore
发明人： Radoslav Danilak , Ladislav Steffko , Rodney Norman Mullendore
IPC分类号： G06F12/02 , G11C16/10 , G06F3/06
CPC分类号： G06F12/0246 , G06F3/0613 , G06F3/064 , G06F3/0679 , G06F2212/2022 , G06F2212/7211 , G11C16/102
摘要： Accessing data of varying-sized quanta in non-volatile memory provides improved storage efficiency in some situations. For example, a Solid-State Disk (SSD) controller receives (e.g. uncompressed) data from a computing host (e.g. a disk write command), compresses the data, and stores the compressed data into non-volatile (e.g. flash) memory. In response to a subsequent request from the host (e.g. a disk read command), the SSD controller reads and uncompresses the compressed data from the memory. The compressed data is stored in the memory according to varying-sized quanta, due to, e.g., compression algorithm, operating mode, and compression effectiveness on various data. The SSD controller uncompresses the data in part by consulting an included map table to locate header(s) stored in the memory, parsing the header(s) to locate appropriate (compressed) data stored in the memory, and uncompressing the appropriate data from the memory to produce the uncompressed data.
摘要翻译：在一些情况下，访问非易失性存储器中不同大小量子的数据提高了存储效率。例如，固态磁盘（SSD）控制器从计算主机（例如磁盘写入命令）接收（例如未压缩的）数据，压缩数据，并将压缩的数据存储到非易失性（例如闪存）存储器中。响应于来自主机的后续请求（例如，磁盘读取命令），SSD控制器从存储器读取和解压缩压缩数据。由于例如压缩算法，操作模式和各种数据的压缩效果，压缩数据根据不同大小的量子被存储在存储器中。 SSD控制器部分地通过参考包括的映射表来解压缩数据，以定位存储在存储器中的标题，解析标题以定位存储在存储器中的适当（压缩的）数据，以及从内存来产生未压缩的数据。

7. 发明授权

US09363315B2 Integrated storage and switching for memory systems 有权
标题翻译：存储系统的集成存储和切换
公开(公告)号：US09363315B2
公开(公告)日：2016-06-07
申请号：US13596979
申请日：2012-08-28
申请人： Radoslav Danilak
发明人： Radoslav Danilak
IPC分类号： G06F15/167 , H04L29/08
CPC分类号： H04L67/1097
摘要： An integrated networked storage and switching apparatus comprises one or more flash memory controllers, a system controller, and a network switch integrated within a common chassis. The integration of storage and switching enables the components to share a common power supply and temperature regulation system, achieving efficient use of available space and power, and eliminating added complexity of external cables between the switch a storage devices. Additionally, the architecture enables substantial flexibility and optimization of network traffic policies for both network and storage-related traffic.
摘要翻译：集成网络存储和交换设备包括一个或多个闪存控制器，系统控制器和集成在公共机箱内的网络交换机。存储和交换的集成使得组件能够共享公共电源和温度调节系统，实现有效利用可用空间和功率，并消除存储设备之间的交换机之间的外部电缆的增加的复杂性。此外，该架构可实现网络和存储相关流量的网络流量策略的实质性灵活性和优化。

8. 发明授权

US08694688B2 Disk controller for implementing efficient disk I/O for a computer system 有权
标题翻译：磁盘控制器，用于实现计算机系统的高效磁盘I / O
公开(公告)号：US08694688B2
公开(公告)日：2014-04-08
申请号：US12005816
申请日：2007-12-28
申请人： Radoslav Danilak , Krishnaraj S. Rao
发明人： Radoslav Danilak , Krishnaraj S. Rao
IPC分类号： G06F3/00 , G06F13/24 , G06F13/22
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0676 , G06F13/385
摘要： A hardware support system for implementing accelerated disk I/O for a computer system. The system includes a bus interface for interfacing with a processor and a system memory of the computer system, a disk I/O engine coupled to the bus interface, and a device interface coupled to the disk I/O engine for interfacing the disk I/O engine with a disk drive. The disk I/O engine is configured to cause a start up of the disk drive upon receiving a disk start up command from the processor. The disk I/O engine is further configured to execute a disk transaction by processing the disk transaction information from a bypass register coupled to the disk I/O engine.
摘要翻译：用于实现计算机系统的加速磁盘I / O的硬件支持系统。该系统包括用于与计算机系统的处理器和系统存储器接口的总线接口，耦合到总线接口的盘I / O引擎以及耦合到盘I / O引擎的设备接口，用于将盘I / O引擎与磁盘驱动器。磁盘I / O引擎被配置为在从处理器接收到磁盘启动命令时引起磁盘驱动器的启动。磁盘I / O引擎还被配置为通过从耦合到磁盘I / O引擎的旁路寄存器处理磁盘事务信息来执行磁盘事务。

9. 发明授权

US08347115B2 System and method for transparent disk encryption 有权
公开(公告)号：US08347115B2
公开(公告)日：2013-01-01
申请号：US12005913
申请日：2007-12-27
申请人： Radoslav Danilak
发明人： Radoslav Danilak
IPC分类号： G06F21/00
CPC分类号： G06F21/602 , G06F21/79
摘要： A data storage system providing transparent encryption. The data storage system has a hardware encryption/decryption engine and a register coupled to the hardware encryption/decryption engine. The register is for securely storing a key for encrypting and decrypting data. The key may not be read from outside the data storage system. More specifically, the key may not be read by the operating system. The user does not have access to the encryption key, but may have a password that is passed to a controller coupled to the encryption/decryption engine. The controller verifies the password and causes data received from main memory to be encrypted by the hardware encryption/decryption engine using the key. The controller also transfers the encrypted data to the data storage device.

10. 发明授权

US08230164B2 Techniques for multi-memory device lifetime management 有权
标题翻译：多内存设备终身管理技术
公开(公告)号：US08230164B2
公开(公告)日：2012-07-24
申请号：US12822442
申请日：2010-06-24
申请人： Radoslav Danilak
发明人： Radoslav Danilak
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/1036 , G06F2212/7208 , G06F2212/7211
摘要： Techniques are provided for identifying at least one aspect associated with a lifetime of each of a plurality of memory devices. Further, data is moved between the plurality of memory devices, based on the at least one aspect.
摘要翻译：提供了用于识别与多个存储器设备中的每一个的寿命相关联的至少一个方面的技术。此外，基于至少一个方面，数据在多个存储器件之间移动。

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