专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07935612B1 Layer transfer using boron-doped SiGe layer 有权
标题翻译：使用硼掺杂的SiGe层进行层转移
公开(公告)号：US07935612B1
公开(公告)日：2011-05-03
申请号：US12700801
申请日：2010-02-05
申请人： Stephen Bedell , Keith Fogel , Daniel Inns , Jeehwan Kim , Devendra Sadana , James Vichiconti
发明人： Stephen Bedell , Keith Fogel , Daniel Inns , Jeehwan Kim , Devendra Sadana , James Vichiconti
IPC分类号： H01L21/30 , H01L21/02
CPC分类号： H01L21/187
摘要： A method for layer transfer using a boron-doped silicon germanium (SiGe) layer includes forming a boron-doped SiGe layer on a bulk silicon substrate; forming an upper silicon (Si) layer over the boron-doped SiGe layer; hydrogenating the boron-doped SiGe layer; bonding the upper Si layer to an alternate substrate; and propagating a fracture at an interface between the boron-doped SiGe layer and the bulk silicon substrate. A system for layer transfer using a boron-doped silicon germanium (SiGe) layer includes a bulk silicon substrate; a boron-doped SiGe layer formed on the bulk silicon substrate, such that the boron-doped SiGe layer is located underneath an upper silicon (Si) layer, wherein the boron-doped SiGe layer is configured to propagate a fracture at an interface between the boron-doped SiGe layer and the bulk silicon substrate after hydrogenation of the boron-doped SiGe layer; and an alternate substrate bonded to the upper Si layer.
摘要翻译：使用硼掺杂硅锗（SiGe）层进行层转移的方法包括在体硅衬底上形成硼掺杂的SiGe层; 在掺杂硼的SiGe层上形成上硅（Si）层; 氢化硼掺杂的SiGe层; 将上部Si层结合到替代的基底上; 并在硼掺杂的SiGe层和体硅衬底之间的界面处传播断裂。使用硼掺杂硅锗（SiGe）层的层转移系统包括体硅衬底; 形成在本体硅衬底上的硼掺杂SiGe层，使得掺杂硼的SiGe层位于上硅（Si）层的下方，其中掺硼的SiGe层被配置为在硼掺杂的SiGe层和硼硅掺杂SiGe层氢化后的体硅衬底; 以及与上部Si层接合的替代基板。

2. 发明申请

US20070105350A1 DEFECT REDUCTION BY OXIDATION OF SILICON 失效
标题翻译：通过氧化硅减少缺陷
公开(公告)号：US20070105350A1
公开(公告)日：2007-05-10
申请号：US11619040
申请日：2007-01-02
申请人： Stephen Bedell , Huajie Chen , Anthony Domenicucci , Keith Fogel , Devendra Sadana
发明人： Stephen Bedell , Huajie Chen , Anthony Domenicucci , Keith Fogel , Devendra Sadana
IPC分类号： C30B1/00 , H01L21/20
CPC分类号： H01L21/7624 , Y10S438/933 , Y10T428/12674
摘要： A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate materials which may be used as a template for strained Si is described. A silicon-on-insulator substrate with a very thin top Si layer is used as a template for compressively strained SiGe growth. Upon relaxation of the SiGe layer at a sufficient temperature, the nature of the dislocation motion is such that the strain-relieving defects move downward into the thin Si layer when the buried oxide behaves semi-viscously. The thin Si layer is consumed by oxidation of the buried oxide/thin Si interface. This can be accomplished by using internal oxidation at high temperatures. In this way the role of the original thin Si layer is to act as a sacrificial defect sink during relaxation of the SiGe alloy that can later be consumed using internal oxidation.
摘要翻译：描述了可以用作应变Si的模板的制造高质量，基本上松弛的绝缘体上硅衬底材料的方法。使用具有非常薄的顶部Si层的绝缘体上硅衬底作为压缩应变SiGe生长的模板。当SiGe层在足够的温度下弛豫时，位错运动的性质使得当埋入的氧化物半粘着时，应变消除缺陷向下移动到薄的Si层中。薄Si层被掩埋氧化物/薄Si界面的氧化所消耗。这可以通过在高温下使用内部氧化来实现。以这种方式，原始薄Si层的作用是在SiGe合金的弛豫期间用作牺牲缺陷陷阱，SiGe合金随后可以使用内部氧化来消耗。

3. 发明申请

US20070281439A1 Techniques for Layer Transfer Processing 审中-公开
标题翻译：层传输处理技术
公开(公告)号：US20070281439A1
公开(公告)日：2007-12-06
申请号：US11840389
申请日：2007-08-17
申请人： Stephen Bedell , Keith Fogel , Bruce Furman , Sampath Purushothaman , Devendra Sadana , Anna Topol
发明人： Stephen Bedell , Keith Fogel , Bruce Furman , Sampath Purushothaman , Devendra Sadana , Anna Topol
IPC分类号： H01L21/30 , H01L21/00
CPC分类号： H01L21/76259 , Y10T428/249961
摘要： Techniques for the fabrication of semiconductor devices are provided. In one aspect, a layer transfer structure is provided. The layer transfer structure comprises a carrier substrate having a porous region with a tuned porosity in combination with an implanted species defining a separation plane therein In another aspect, a method of forming a layer transfer structure is provided. In yet another aspect, a method of forming a thee dimensional integrated structure is provided.
摘要翻译：提供了制造半导体器件的技术。一方面，提供了层转移结构。层转移结构包括具有调谐孔隙度的多孔区域的载体衬底以及限定分离平面的注入物质的组合。另一方面，提供了一种形成层转移结构的方法。另一方面，提供了一种形成一维一体结构的方法。

4. 发明申请

US20070164356A1 Strained semiconductor-on-insulator (sSOI) by a simox method 有权
标题翻译：应用绝缘体半导体（sSOI）通过simox方法
公开(公告)号：US20070164356A1
公开(公告)日：2007-07-19
申请号：US11332564
申请日：2006-01-13
申请人： Thomas Adam , Stephen Bedell , Joel de Souza , Keith Fogel , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
发明人： Thomas Adam , Stephen Bedell , Joel de Souza , Keith Fogel , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/76243 , H01L29/66772 , H01L29/7849 , H01L29/78654
摘要： A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.
摘要翻译：提供了一种应变（拉伸或压缩）半导体绝缘体材料，其中使用单个半导体晶片和通过氧气工艺的离子注入分离。通过离子注入氧气工艺的分离，其中包括氧离子注入和退火，产生位于应变半导体层之下的材料内的掩埋氧化物层。在一些实施例中，渐变半导体缓冲层位于掩埋氧化物层的下方，而在其它掺杂半导体层中，包含掺杂有B或C中的至少一个的掺杂半导体层位于掩埋氧化物层的下方。

5. 发明申请

US20060081837A1 Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer 有权
公开(公告)号：US20060081837A1
公开(公告)日：2006-04-20
申请号：US11293774
申请日：2005-12-02
申请人： Stephen Bedell , Anthony Domenicucci , Keith Fogel , Effendi Leobandung , Devendra Sadana
发明人： Stephen Bedell , Anthony Domenicucci , Keith Fogel , Effendi Leobandung , Devendra Sadana
IPC分类号： H01L31/109
CPC分类号： H01L29/78696 , H01L21/0237 , H01L21/02439 , H01L21/02488 , H01L21/02502 , H01L21/02521 , H01L21/02667 , H01L21/02694 , H01L21/76251 , H01L29/7842
摘要： A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 Å) and has a low defect density (stacking faults and threading defects). The method of the present invention begins with forming a stress-providing layer, such a SiGe alloy layer over a structure comprising a first semiconductor layer that is located atop an insulating layer. The stress-providing layer and the first semiconductor layer are then patterned into at least one island and thereafter the structure containing the at least one island is heated to a temperature that causes strain transfer from the stress-providing layer to the first semiconductor layer. After strain transfer, the stress-providing layer is removed from the structure to form a first strained semiconductor island layer directly atop said insulating layer.

6. 发明申请

US20050048778A1 Use of thin SOI to inhibit relaxation of SiGe layers 有权
标题翻译：使用薄SOI抑制SiGe层的弛豫
公开(公告)号：US20050048778A1
公开(公告)日：2005-03-03
申请号：US10654232
申请日：2003-09-03
申请人： Stephen Bedell , Huajie Chen , Keith Fogel , Devendra Sadana
发明人： Stephen Bedell , Huajie Chen , Keith Fogel , Devendra Sadana
IPC分类号： H01L29/161 , C30B29/52 , C30B31/02 , H01L21/02 , H01L21/20 , H01L21/205 , H01L21/762 , H01L21/8238 , H01L27/12 , H01L29/04 , C30B1/00 , C30B3/00 , C30B5/00 , C30B28/02 , H01L21/302 , H01L21/461
CPC分类号： H01L21/7624 , C30B29/52 , C30B31/02 , H01L21/02381 , H01L21/02532 , H01L21/02694 , Y10T428/24917
摘要： High-quality, metastable SiGe alloys are formed on SOI substrates having an SOI layer of about 500 Å or less, the SiGe layers can remain substantially fully strained compared to identical SiGe layers formed on thicker SOI substrates and subsequently annealed and/or oxidized at high temperatures. The present invention thus provides a method of ‘frustrating’ metastable strained SiGe layers by growing them on thin, clean and high-quality SOI substrates.
摘要翻译：在具有大约等于或小于等于或等于SOI层的SOI层的SOI衬底上形成高质量的亚稳态SiGe合金，与形成在较厚SOI衬底上的相同SiGe层相比，SiGe层可以保持基本上完全变形，并随后在高温下退火和/或氧化温度。因此，本发明提供了一种通过在薄的，清洁的和高质量的SOI衬底上生长它们来“挫败”亚稳应变的SiGe层的方法。

7. 发明申请

US20080116483A1 HIGH-QUALITY SGOI BY ANNEALING NEAR THE ALLOY MELTING POINT 失效
标题翻译：高品质SGOI通过靠近合金熔点来退火
公开(公告)号：US20080116483A1
公开(公告)日：2008-05-22
申请号：US12027561
申请日：2008-02-07
申请人： Stephen Bedell , Huajie Chen , Anthony Domenicucci , Keith Fogel , Richard Murphy , Devendra Sadana
发明人： Stephen Bedell , Huajie Chen , Anthony Domenicucci , Keith Fogel , Richard Murphy , Devendra Sadana
IPC分类号： H01L29/165
CPC分类号： H01L21/26506 , H01L21/324 , H01L21/7624 , H01L21/76254 , H01L29/1054
摘要： A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom. In one embodiment, the heating step includes an oxidation process that is performed at a temperature from about 1230° to about 1320° C. for a time period of less than about 2 hours. This embodiment provides SGOI substrate that have minimal surface pitting and reduced crosshatching.
摘要翻译：提供一种形成低缺陷，基本上松弛的绝缘体上硅衬底材料的方法。该方法包括首先在耐Ge扩散的阻挡层上存在的第一单晶Si层的表面上形成含Ge层。然后在接近最终SiGe合金的熔点的温度下进行加热步骤，并且在保留Ge的同时延缓形成堆垛层错缺陷。加热步骤允许Ge遍及第一单晶Si层和含Ge层的相互扩散，从而在阻挡层顶部形成基本松弛的单晶SiGe层。此外，由于加热步骤在接近最终SiGe合金的熔点的温度下进行，所以由于弛豫而在单晶SiGe层中持续存在的缺陷被有效地湮灭。在一个实施方案中，加热步骤包括氧化过程，其在约1230℃至约1320℃的温度下进行约少于约2小时的时间。该实施例提供具有最小表面点蚀和减少的交叉阴影的SGOI衬底。

8. 发明申请

US20060057403A1 Use of thin SOI to inhibit relaxation of SiGe layers 审中-公开
公开(公告)号：US20060057403A1
公开(公告)日：2006-03-16
申请号：US11268096
申请日：2005-11-07
申请人： Stephen Bedell , Huajie Chen , Keith Fogel , Devendra Sadana
发明人： Stephen Bedell , Huajie Chen , Keith Fogel , Devendra Sadana
IPC分类号： B32B13/04 , B32B15/04 , B32B9/00
CPC分类号： H01L21/7624 , C30B29/52 , C30B31/02 , H01L21/02381 , H01L21/02532 , H01L21/02694 , Y10T428/24917
摘要： High-quality, metastable SiGe alloys are formed on SOI substrates having an SOI layer of about 500 Å or less, the SiGe layers can remain substantially fully strained compared to identical SiGe layers formed on thicker SOI substrates and subsequently annealed and/or oxidized at high temperatures. The present invention thus provides a method of ‘frustrating’ metastable strained SiGe layers by growing them on thin, clean and high-quality SOI substrates.

9. 发明申请

US20060042542A1 Method of producing silicon-germanium-on-insulator material using unstrained Ge-containing source layers 有权
公开(公告)号：US20060042542A1
公开(公告)日：2006-03-02
申请号：US10932598
申请日：2004-09-02
申请人： Stephen Bedell , Keith Fogel , Devendra Sadana
发明人： Stephen Bedell , Keith Fogel , Devendra Sadana
IPC分类号： C30B23/00 , C30B25/00 , C30B28/12 , C30B28/14
CPC分类号： H01L21/76254
摘要： A method of fabricating a high-quality relaxed SiGe-on-insulator substrate material is provided in which a prefabricated silicon-on-insulator substrate is first exposed to an unstrained Ge-containing source and then heated (annealed/oxidized) to cause Ge diffusion and thermal mixing of Ge within a single-crystal Si-containing layer of the prefabricated silicon-on-insulator substrate. The unstrained Ge-containing source can comprise a solid Ge-containing source, a gaseous Ge-containing source, or ions of Ge.

10. 发明申请

US20050208780A1 High-quality SGOI by oxidation near the alloy melting temperature 有权
标题翻译：高品质的SGOI通过氧化在合金熔化温度附近
公开(公告)号：US20050208780A1
公开(公告)日：2005-09-22
申请号：US11029921
申请日：2005-01-05
申请人： Stephen Bedell , Anthony Domenicucci , Keith Fogel , Devendra Sadana
发明人： Stephen Bedell , Anthony Domenicucci , Keith Fogel , Devendra Sadana
IPC分类号： C30B1/00 , H01L21/00 , H01L21/20 , H01L21/324 , H01L21/477 , H01L21/762 , H01L27/01
CPC分类号： H01L21/26506 , H01L21/324 , H01L21/7624 , H01L21/76254 , H01L29/1054
摘要： A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom.
摘要翻译：提供一种形成低缺陷，基本上松弛的绝缘体上硅衬底材料的方法。该方法包括首先在耐Ge扩散的阻挡层上存在的第一单晶Si层的表面上形成含Ge层。然后在接近最终SiGe合金的熔点的温度下进行加热步骤，并且在保留Ge的同时延缓层叠缺陷缺陷的形成。加热步骤允许Ge遍及第一单晶Si层和含Ge层的相互扩散，从而在阻挡层顶部形成基本松弛的单晶SiGe层。此外，由于加热步骤在接近最终SiGe合金的熔点的温度下进行，所以由于弛豫而在单晶SiGe层中持续存在的缺陷被有效地湮灭。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式