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1. 发明申请

US20080116483A1 HIGH-QUALITY SGOI BY ANNEALING NEAR THE ALLOY MELTING POINT 失效
标题翻译：高品质SGOI通过靠近合金熔点来退火
公开(公告)号：US20080116483A1
公开(公告)日：2008-05-22
申请号：US12027561
申请日：2008-02-07
申请人： Stephen Bedell , Huajie Chen , Anthony Domenicucci , Keith Fogel , Richard Murphy , Devendra Sadana
发明人： Stephen Bedell , Huajie Chen , Anthony Domenicucci , Keith Fogel , Richard Murphy , Devendra Sadana
IPC分类号： H01L29/165
CPC分类号： H01L21/26506 , H01L21/324 , H01L21/7624 , H01L21/76254 , H01L29/1054
摘要： A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom. In one embodiment, the heating step includes an oxidation process that is performed at a temperature from about 1230° to about 1320° C. for a time period of less than about 2 hours. This embodiment provides SGOI substrate that have minimal surface pitting and reduced crosshatching.
摘要翻译：提供一种形成低缺陷，基本上松弛的绝缘体上硅衬底材料的方法。该方法包括首先在耐Ge扩散的阻挡层上存在的第一单晶Si层的表面上形成含Ge层。然后在接近最终SiGe合金的熔点的温度下进行加热步骤，并且在保留Ge的同时延缓形成堆垛层错缺陷。加热步骤允许Ge遍及第一单晶Si层和含Ge层的相互扩散，从而在阻挡层顶部形成基本松弛的单晶SiGe层。此外，由于加热步骤在接近最终SiGe合金的熔点的温度下进行，所以由于弛豫而在单晶SiGe层中持续存在的缺陷被有效地湮灭。在一个实施方案中，加热步骤包括氧化过程，其在约1230℃至约1320℃的温度下进行约少于约2小时的时间。该实施例提供具有最小表面点蚀和减少的交叉阴影的SGOI衬底。

2. 发明申请

US20070105350A1 DEFECT REDUCTION BY OXIDATION OF SILICON 失效
标题翻译：通过氧化硅减少缺陷
公开(公告)号：US20070105350A1
公开(公告)日：2007-05-10
申请号：US11619040
申请日：2007-01-02
申请人： Stephen Bedell , Huajie Chen , Anthony Domenicucci , Keith Fogel , Devendra Sadana
发明人： Stephen Bedell , Huajie Chen , Anthony Domenicucci , Keith Fogel , Devendra Sadana
IPC分类号： C30B1/00 , H01L21/20
CPC分类号： H01L21/7624 , Y10S438/933 , Y10T428/12674
摘要： A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate materials which may be used as a template for strained Si is described. A silicon-on-insulator substrate with a very thin top Si layer is used as a template for compressively strained SiGe growth. Upon relaxation of the SiGe layer at a sufficient temperature, the nature of the dislocation motion is such that the strain-relieving defects move downward into the thin Si layer when the buried oxide behaves semi-viscously. The thin Si layer is consumed by oxidation of the buried oxide/thin Si interface. This can be accomplished by using internal oxidation at high temperatures. In this way the role of the original thin Si layer is to act as a sacrificial defect sink during relaxation of the SiGe alloy that can later be consumed using internal oxidation.
摘要翻译：描述了可以用作应变Si的模板的制造高质量，基本上松弛的绝缘体上硅衬底材料的方法。使用具有非常薄的顶部Si层的绝缘体上硅衬底作为压缩应变SiGe生长的模板。当SiGe层在足够的温度下弛豫时，位错运动的性质使得当埋入的氧化物半粘着时，应变消除缺陷向下移动到薄的Si层中。薄Si层被掩埋氧化物/薄Si界面的氧化所消耗。这可以通过在高温下使用内部氧化来实现。以这种方式，原始薄Si层的作用是在SiGe合金的弛豫期间用作牺牲缺陷陷阱，SiGe合金随后可以使用内部氧化来消耗。

3. 发明申请

US20050003229A1 Defect reduction by oxidation of silicon 失效
标题翻译：通过氧化硅来减少缺陷
公开(公告)号：US20050003229A1
公开(公告)日：2005-01-06
申请号：US10610612
申请日：2003-07-01
申请人： Stephen Bedell , Huajie Chen , Anthony Domenicucci , Keith Fogel , Devendra Sadana
发明人： Stephen Bedell , Huajie Chen , Anthony Domenicucci , Keith Fogel , Devendra Sadana
IPC分类号： H01L27/12 , H01L21/02 , H01L21/20 , H01L21/762 , H01L21/425 , B32B15/00
CPC分类号： H01L21/7624 , Y10S438/933 , Y10T428/12674
摘要： A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate materials which may be used as a template for strained Si is described. A silicon-on-insulator substrate with a very thin top Si layer is used as a template for compressively strained SiGe growth. Upon relaxation of the SiGe layer at a sufficient temperature, the nature of the dislocation motion is such that the strain-relieving defects move downward into the thin Si layer when the buried oxide behaves semi-viscously. The thin Si layer is consumed by oxidation of the buried oxide/thin Si interface. This can be accomplished by using internal oxidation at high temperatures. In this way the role of the original thin Si layer is to act as a sacrificial defect sink during relaxation of the SiGe alloy that can later be consumed using internal oxidation.
摘要翻译：描述了可以用作应变Si的模板的制造高质量，基本上松弛的绝缘体上硅衬底材料的方法。使用具有非常薄的顶部Si层的绝缘体上硅衬底作为压缩应变SiGe生长的模板。当SiGe层在足够的温度下弛豫时，位错运动的性质使得当埋入的氧化物半粘着时，应变消除缺陷向下移动到薄的Si层中。薄Si层被掩埋氧化物/薄Si界面的氧化所消耗。这可以通过在高温下使用内部氧化来实现。以这种方式，原始薄Si层的作用是在SiGe合金的弛豫期间用作牺牲缺陷陷阱，SiGe合金随后可以使用内部氧化来消耗。

4. 发明申请

US20060081837A1 Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer 有权
公开(公告)号：US20060081837A1
公开(公告)日：2006-04-20
申请号：US11293774
申请日：2005-12-02
申请人： Stephen Bedell , Anthony Domenicucci , Keith Fogel , Effendi Leobandung , Devendra Sadana
发明人： Stephen Bedell , Anthony Domenicucci , Keith Fogel , Effendi Leobandung , Devendra Sadana
IPC分类号： H01L31/109
CPC分类号： H01L29/78696 , H01L21/0237 , H01L21/02439 , H01L21/02488 , H01L21/02502 , H01L21/02521 , H01L21/02667 , H01L21/02694 , H01L21/76251 , H01L29/7842
摘要： A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 Å) and has a low defect density (stacking faults and threading defects). The method of the present invention begins with forming a stress-providing layer, such a SiGe alloy layer over a structure comprising a first semiconductor layer that is located atop an insulating layer. The stress-providing layer and the first semiconductor layer are then patterned into at least one island and thereafter the structure containing the at least one island is heated to a temperature that causes strain transfer from the stress-providing layer to the first semiconductor layer. After strain transfer, the stress-providing layer is removed from the structure to form a first strained semiconductor island layer directly atop said insulating layer.

5. 发明申请

US20050208780A1 High-quality SGOI by oxidation near the alloy melting temperature 有权
标题翻译：高品质的SGOI通过氧化在合金熔化温度附近
公开(公告)号：US20050208780A1
公开(公告)日：2005-09-22
申请号：US11029921
申请日：2005-01-05
申请人： Stephen Bedell , Anthony Domenicucci , Keith Fogel , Devendra Sadana
发明人： Stephen Bedell , Anthony Domenicucci , Keith Fogel , Devendra Sadana
IPC分类号： C30B1/00 , H01L21/00 , H01L21/20 , H01L21/324 , H01L21/477 , H01L21/762 , H01L27/01
CPC分类号： H01L21/26506 , H01L21/324 , H01L21/7624 , H01L21/76254 , H01L29/1054
摘要： A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom.
摘要翻译：提供一种形成低缺陷，基本上松弛的绝缘体上硅衬底材料的方法。该方法包括首先在耐Ge扩散的阻挡层上存在的第一单晶Si层的表面上形成含Ge层。然后在接近最终SiGe合金的熔点的温度下进行加热步骤，并且在保留Ge的同时延缓层叠缺陷缺陷的形成。加热步骤允许Ge遍及第一单晶Si层和含Ge层的相互扩散，从而在阻挡层顶部形成基本松弛的单晶SiGe层。此外，由于加热步骤在接近最终SiGe合金的熔点的温度下进行，所以由于弛豫而在单晶SiGe层中持续存在的缺陷被有效地湮灭。

6. 发明申请

US20060030133A1 Relaxed, low-defect SGOI for strained Si CMOS applications 有权
标题翻译：用于应变Si CMOS应用的轻松，低缺陷SGOI
公开(公告)号：US20060030133A1
公开(公告)日：2006-02-09
申请号：US11208359
申请日：2005-08-19
申请人： Paul Agnello , Stephen Bedell , Robert Dennard , Anthony Domenicucci , Keith Fogel , Devendra Sadana
发明人： Paul Agnello , Stephen Bedell , Robert Dennard , Anthony Domenicucci , Keith Fogel , Devendra Sadana
IPC分类号： H01L21/20 , H01L33/00 , H01L21/36
CPC分类号： H01L21/324 , C30B25/02 , C30B29/52 , H01L21/02378 , H01L21/02381 , H01L21/02532 , H01L21/02664 , H01L21/7624 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/66893 , H01L29/78603
摘要： Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.
摘要翻译：提供形成基本上松弛和低缺陷的SGOI基底材料的热混合方法。所述方法包括图形化步骤，其用于形成至少包含形成在Ge抗蚀扩散阻挡层顶上的SiGe岛的结构。将SiGe层图案化成岛以这样的方式改变作用在每个岛边缘处的局部力，使得松弛力大于抵抗放松的力。在图案化层的边缘处没有恢复力允许最终的SiGe膜比如果膜是连续的那样进一步松弛。

7. 发明申请

US20060001089A1 ULTRA-THIN, HIGH QUALITY STRAINED SILICON-ON-INSULATOR FORMED BY ELASTIC STRAIN TRANSFER 失效
标题翻译：超薄薄膜，高品质应变硅橡胶绝缘子，由弹性应变转移
公开(公告)号：US20060001089A1
公开(公告)日：2006-01-05
申请号：US10883883
申请日：2004-07-02
申请人： Stephen Bedell , Anthony Domenicucci , Keith Fogel , Effendi Leobandung , Devendra Sadana
发明人： Stephen Bedell , Anthony Domenicucci , Keith Fogel , Effendi Leobandung , Devendra Sadana
IPC分类号： H01L31/0392 , H01L21/84
CPC分类号： H01L29/78696 , H01L21/0237 , H01L21/02439 , H01L21/02488 , H01L21/02502 , H01L21/02521 , H01L21/02667 , H01L21/02694 , H01L21/76251 , H01L29/7842
摘要： A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 Å) and has a low defect density (stacking faults and threading defects). The method of the present invention begins with forming a stress-providing layer, such a SiGe alloy layer over a structure comprising a first semiconductor layer that is located atop an insulating layer. The stress-providing layer and the first semiconductor layer are then patterned into at least one island and thereafter the structure containing the at least one island is heated to a temperature that causes strain transfer from the stress-providing layer to the first semiconductor layer. After strain transfer, the stress-providing layer is removed from the structure to form a first strained semiconductor island layer directly atop said insulating layer.
摘要翻译：提供了一种在绝缘层上形成包括第一应变半导体层的半导体结构的方法，其中第一应变半导体层相对较薄（小于约）并且具有低缺陷密度（堆垛层错和穿线缺陷）。本发明的方法开始于在包括位于绝缘层顶部的第一半导体层的结构上形成应力提供层，例如SiGe合金层。然后将应力提供层和第一半导体层图案化成至少一个岛，然后将含有至少一个岛的结构加热到使得应力转移从应力提供层到第一半导体层的温度。在应变转移之后，将应力提供层从结构上去除，以形成直接位于所述绝缘层顶部的第一应变半导体岛层。

8. 发明申请

US20050048778A1 Use of thin SOI to inhibit relaxation of SiGe layers 有权
标题翻译：使用薄SOI抑制SiGe层的弛豫
公开(公告)号：US20050048778A1
公开(公告)日：2005-03-03
申请号：US10654232
申请日：2003-09-03
申请人： Stephen Bedell , Huajie Chen , Keith Fogel , Devendra Sadana
发明人： Stephen Bedell , Huajie Chen , Keith Fogel , Devendra Sadana
IPC分类号： H01L29/161 , C30B29/52 , C30B31/02 , H01L21/02 , H01L21/20 , H01L21/205 , H01L21/762 , H01L21/8238 , H01L27/12 , H01L29/04 , C30B1/00 , C30B3/00 , C30B5/00 , C30B28/02 , H01L21/302 , H01L21/461
CPC分类号： H01L21/7624 , C30B29/52 , C30B31/02 , H01L21/02381 , H01L21/02532 , H01L21/02694 , Y10T428/24917
摘要： High-quality, metastable SiGe alloys are formed on SOI substrates having an SOI layer of about 500 Å or less, the SiGe layers can remain substantially fully strained compared to identical SiGe layers formed on thicker SOI substrates and subsequently annealed and/or oxidized at high temperatures. The present invention thus provides a method of ‘frustrating’ metastable strained SiGe layers by growing them on thin, clean and high-quality SOI substrates.
摘要翻译：在具有大约等于或小于等于或等于SOI层的SOI层的SOI衬底上形成高质量的亚稳态SiGe合金，与形成在较厚SOI衬底上的相同SiGe层相比，SiGe层可以保持基本上完全变形，并随后在高温下退火和/或氧化温度。因此，本发明提供了一种通过在薄的，清洁的和高质量的SOI衬底上生长它们来“挫败”亚稳应变的SiGe层的方法。

9. 发明申请

US20060057403A1 Use of thin SOI to inhibit relaxation of SiGe layers 审中-公开
公开(公告)号：US20060057403A1
公开(公告)日：2006-03-16
申请号：US11268096
申请日：2005-11-07
申请人： Stephen Bedell , Huajie Chen , Keith Fogel , Devendra Sadana
发明人： Stephen Bedell , Huajie Chen , Keith Fogel , Devendra Sadana
IPC分类号： B32B13/04 , B32B15/04 , B32B9/00
CPC分类号： H01L21/7624 , C30B29/52 , C30B31/02 , H01L21/02381 , H01L21/02532 , H01L21/02694 , Y10T428/24917
摘要： High-quality, metastable SiGe alloys are formed on SOI substrates having an SOI layer of about 500 Å or less, the SiGe layers can remain substantially fully strained compared to identical SiGe layers formed on thicker SOI substrates and subsequently annealed and/or oxidized at high temperatures. The present invention thus provides a method of ‘frustrating’ metastable strained SiGe layers by growing them on thin, clean and high-quality SOI substrates.

10. 发明申请

US20060027808A1 METHOD OF FORMING STRAINED SILICON MATERIALS WITH IMPROVED THERMAL CONDUCTIVITY 有权
标题翻译：形成具有改善的导热性的应变硅材料的方法
公开(公告)号：US20060027808A1
公开(公告)日：2006-02-09
申请号：US10710826
申请日：2004-08-05
申请人： Stephen Bedell , Huajie Chen , Keith Fogel , Ryan Mitchell , Devendra Sadana
发明人： Stephen Bedell , Huajie Chen , Keith Fogel , Ryan Mitchell , Devendra Sadana
IPC分类号： H01L29/12 , H01L21/20
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02507 , H01L21/02532
摘要： A method is disclosed for forming a strained Si layer on SiGe, where the SiGe layer has improved thermal conductivity. A first layer of Si or Ge is deposited on a substrate in a first depositing step; a second layer of the other element is deposited on the first layer in a second depositing step; and the first and second depositing steps are repeated so as to form a combined SiGe layer having a plurality of Si layers and a plurality of Ge layers. The respective thicknesses of the Si layers and Ge layers are in accordance with a desired composition ratio of the combined SiGe layer (so that a 1:1 ratio typically is realized with Si and Ge layers each about 10 Å thick). The combined SiGe layer is characterized as a digital alloy of Si and Ge having a thermal conductivity greater than that of a random alloy of Si and Ge. This method may further include the step of depositing a Si layer on the combined SiGe layer; the combined SiGe layer is characterized as a relaxed SiGe layer, and the Si layer is a strained Si layer. For still greater thermal conductivity in the SiGe layer, the first layer and second layer may be deposited so that each layer consists essentially of a single isotope.
摘要翻译：公开了一种在SiGe上形成应变Si层的方法，其中SiGe层具有改善的导热性。在第一沉积步骤中将第一层Si或Ge沉积在衬底上; 另一个元件的第二层在第二沉积步骤中沉积在第一层上; 并且重复第一和第二沉积步骤以形成具有多个Si层和多个Ge层的组合SiGe层。 Si层和Ge层的各自的厚度根据组合的SiGe层的期望组成比（使得Si和Ge层的厚度通常为1：1，每个厚度大约为10埃）。组合的SiGe层的特征在于具有大于Si和Ge的随机合金的热导率的Si和Ge的数字合金。该方法还可以包括在组合的SiGe层上沉积Si层的步骤; 组合的SiGe层被表征为弛豫的SiGe层，并且Si层是应变的Si层。对于SiGe层中更高的热导率，可以沉积第一层和第二层，使得每层基本上由单一同位素组成。

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