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1. 发明申请

US20120118383A1 Autonomous Integrated Circuit 审中-公开
标题翻译：自主集成电路
公开(公告)号：US20120118383A1
公开(公告)日：2012-05-17
申请号：US12946216
申请日：2010-11-15
申请人： Stephen W. Bedell , Norma E. Sosa Cortes , Wilfried E. Haensch , Steven J. Koester , Devendra K. Sadana , Katherine L. Saenger , Ghavam Shahidi , Davood Shahrjerdi
发明人： Stephen W. Bedell , Norma E. Sosa Cortes , Wilfried E. Haensch , Steven J. Koester , Devendra K. Sadana , Katherine L. Saenger , Ghavam Shahidi , Davood Shahrjerdi
IPC分类号： H01L31/0264 , H01L31/18
CPC分类号： H01L27/142 , H01L31/02008 , H01L31/0747 , H01L31/075 , H01L31/076 , H01L31/078 , H01L31/1804 , H01L31/202 , Y02E10/547 , Y02E10/548 , Y02P70/521
摘要： An autonomous integrated circuit (IC) includes a solar cell formed on a bottom substrate of a silicon-on-insulator (SOI) substrate as a handle substrate; an insulating layer of the SOI substrate located on top of the solar cell; and a device layer formed on a top semiconductor layer of the SOI substrate located on top of the insulating layer, wherein a top contact of the device layer is electrically connected to a bottom contact of the solar cell such that the solar cell is enabled to power the device layer.
摘要翻译：自主集成电路（IC）包括形成在作为处理衬底的绝缘体上硅（SOI）衬底的底部衬底上的太阳能电池; 位于太阳能电池顶部的SOI衬底的绝缘层; 以及形成在位于绝缘层顶部的SOI衬底的顶部半导体层上的器件层，其中器件层的顶部接触电连接到太阳能电池的底部接触，使得太阳能电池能够通电设备层。

2. 发明授权

US08169024B2 Method of forming extremely thin semiconductor on insulator (ETSOI) device without ion implantation 有权
标题翻译：无离子注入形成非常薄的绝缘体上半导体（ETSOI）器件的方法
公开(公告)号：US08169024B2
公开(公告)日：2012-05-01
申请号：US12542771
申请日：2009-08-18
申请人： Kangguo Cheng , Bruce B. Doris , Pranita Kulkarni , Ghavam Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Pranita Kulkarni , Ghavam Shahidi
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method of fabricating a semiconductor device is provided in which the channel of the device is present in an extremely thin silicon on insulator (ETSOI) layer, i.e., a silicon containing layer having a thickness of less than 10.0 nm. In one embodiment, the method may begin with providing a substrate having at least a first semiconductor layer overlying a dielectric layer, wherein the first semiconductor layer has a thickness of less than 10.0 nm. A gate structure is formed directly on the first semiconductor layer. A in-situ doped semiconductor material is formed on the first semiconductor layer adjacent to the gate structure. The dopant from the in-situ doped semiconductor material is then diffused into the first semiconductor layer to form extension regions. The method is also applicable to finFET structures.
摘要翻译：提供一种制造半导体器件的方法，其中器件的沟道存在于极薄的绝缘体上（ETSOI）层，即厚度小于10.0nm的含硅层中。在一个实施例中，该方法可以从提供具有覆盖介电层的至少第一半导体层的衬底开始，其中第一半导体层具有小于10.0nm的厚度。栅极结构直接形成在第一半导体层上。在与栅极结构相邻的第一半导体层上形成原位掺杂的半导体材料。然后将来自原位掺杂半导体材料的掺杂剂扩散到第一半导体层中以形成延伸区域。该方法也适用于finFET结构。

3. 发明申请

US20120068264A1 FORMING NARROW FINS FOR FINFET DEVICES USING ASYMMETRICALLY SPACED MANDRELS 有权
标题翻译：使用非对称间距管道形成FINFET器件的NARROW FINS
公开(公告)号：US20120068264A1
公开(公告)日：2012-03-22
申请号：US12886850
申请日：2010-09-21
申请人： KANGGUO CHENG , Bruce B. Doris , Ali Khakifirooz , Ghavam Shahidi
发明人： KANGGUO CHENG , Bruce B. Doris , Ali Khakifirooz , Ghavam Shahidi
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/66795 , H01L21/845
摘要： A method of forming fins for fin-shaped field effect transistor (finFET) devices includes forming a plurality of sacrificial mandrels over a semiconductor substrate. The plurality of sacrificial mandrels are spaced apart from one another by a first distance along a first direction, and by a second distance along a second direction. Spacer layers are formed on sidewalls of the sacrificial mandrels such that portions of the spacer layers between sacrificial mandrels along the first direction are merged together. Portions of the spacer layers between sacrificial mandrels along the second direction remain spaced apart. The sacrificial mandrels are removed. A pattern corresponding to the spacer layers is transferred into the semiconductor layers to form a plurality of semiconductor fins. Adjacent pairs of fins are merged with one another at locations corresponding to the merged spacer layers.
摘要翻译：形成鳍状场效应晶体管（finFET）器件的鳍片的方法包括在半导体衬底上形成多个牺牲心轴。多个牺牲心轴沿着第一方向彼此间隔开第一距离，并且沿第二方向间隔开第二距离。间隔层形成在牺牲心轴的侧壁上，使得沿着第一方向的牺牲心轴之间的间隔层的部分被合并在一起。沿着第二方向的牺牲心轴之间的间隔层的部分保持间隔开。牺牲心轴被去除。对应于间隔层的图案被转移到半导体层中以形成多个半导体鳍片。相邻的翅片对在与合并的间隔层相对应的位置处彼此合并。

4. 发明申请

US20110254090A1 RAISED SOURCE/DRAIN STRUCTURE FOR ENHANCED STRAIN COUPLING FROM STRESS LINER 有权
标题翻译：从应力衬里增强应变耦合的提高源/排水结构
公开(公告)号：US20110254090A1
公开(公告)日：2011-10-20
申请号：US12760250
申请日：2010-04-14
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam Shahidi
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam Shahidi
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L29/78654 , H01L21/76283 , H01L29/66772 , H01L29/78618
摘要： A transistor is provided that includes a buried oxide layer above a substrate. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer, the gate stack including a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A nitride liner is adjacent to the gate stack. An oxide liner is adjacent to the nitride liner. A set of faceted raised source/drain regions having a part including a portion of the silicon layer. The set of faceted raised source/drain regions also include a first faceted side portion and a second faceted side portion.
摘要翻译：提供一种晶体管，其包括衬底上方的掩埋氧化物层。硅层在掩埋氧化物层之上。栅极堆叠在硅层上，栅极堆叠包括硅层上的高k氧化物层和高k氧化物层上的金属栅极。氮化物衬垫与栅堆叠相邻。氧化物衬垫与氮化物衬垫相邻。一组具有包括硅层的一部分的部分的凸起的源/漏区。所述一组切面隆起的源极/漏极区域还包括第一分面侧部分和第二分面侧部分。

5. 发明授权

US07964896B2 Buried channel MOSFET using III-V compound semiconductors and high k gate dielectrics 有权
标题翻译：使用III-V复合半导体和高k栅极电介质的掩埋沟道MOSFET
公开(公告)号：US07964896B2
公开(公告)日：2011-06-21
申请号：US12180927
申请日：2008-07-28
申请人： Edward W. Kiewra , Steven J. Koester , Devendra K. Sadana , Ghavam Shahidi , Yanning Sun
发明人： Edward W. Kiewra , Steven J. Koester , Devendra K. Sadana , Ghavam Shahidi , Yanning Sun
IPC分类号： H01L29/66
CPC分类号： H01L29/7787 , H01L29/66462
摘要： A semiconductor-containing heterostructure including, from bottom to top, a III-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a III-V compound semiconductor barrier layer, and an optional, yet preferred, III-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The III-V compound semiconductor buffer layer and the III-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the III-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor.
摘要翻译：一种含半导体的异质结构，包括III-V族化合物半导体缓冲层，III-V族化合物半导体沟道层，III-V族化合物半导体阻挡层和任选的，但优选的III-V族化合物提供半导体盖层。阻挡层可以是掺杂的，或者优选地是未掺杂的。 III-V族化合物半导体缓冲层和III-V族化合物半导体阻挡层由具有比III-V化合物半导体沟道层宽的带隙的材料构成。由于宽带隙材料用于缓冲层和阻挡层，并且窄带隙材料用于沟道层，所以载流子在特定栅极偏置范围内被限制在沟道层。本发明的异质结构可以用作场效应晶体管中的掩埋沟道结构。

6. 发明授权

US07759772B2 Method to form Si-containing SOI and underlying substrate with different orientations 失效
标题翻译：形成含Si的SOI和具有不同取向的下层衬底的方法
公开(公告)号：US07759772B2
公开(公告)日：2010-07-20
申请号：US11550681
申请日：2006-10-18
申请人： Meikei Ieong , Devendra K. Sadana , Ghavam Shahidi
发明人： Meikei Ieong , Devendra K. Sadana , Ghavam Shahidi
IPC分类号： H01L29/04 , H01L31/036
CPC分类号： H01L21/76251 , H01L21/2007
摘要： A method of forming a hybrid SOI substrate comprising an upper Si-containing layer and a lower Si-containing layer, wherein the upper Si-containing layer and the lower Si-containing layer have different crystallographic orientations. In accordance with the present invention, the buried insulating region may be located within one of the Si-containing layers or through an interface located between the two Si-containing layers.
摘要翻译：一种形成包含上层含Si层和下层含Si层的混合SOI衬底的方法，其中上层含Si层和下层含Si层具有不同的结晶取向。根据本发明，掩埋绝缘区域可以位于一个含硅层内或通过位于两个含Si层之间的界面。

7. 发明申请

US20090305471A1 THIN SILICON SINGLE DIFFUSION FIELD EFFECT TRANSISTOR FOR ENHANCED DRIVE PERFORMANCE WITH STRESS FILM LINERS 审中-公开
标题翻译：薄硅单晶扩散场效应晶体管，用于增强驱动器性能与应力膜线
公开(公告)号：US20090305471A1
公开(公告)日：2009-12-10
申请号：US12541605
申请日：2009-08-14
申请人： Leland Chang , David M. Fried , John M. Hergenrother , Ghavam Shahidi , Jeffrey W. Sleight
发明人： Leland Chang , David M. Fried , John M. Hergenrother , Ghavam Shahidi , Jeffrey W. Sleight
IPC分类号： H01L21/762 , H01L21/8238 , H01L21/336
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/458 , H01L29/66772 , H01L29/7843
摘要： The present invention provides a semiconducting device structure including a thin SOI region, wherein the SOI device is formed with an optional single thin diffusion, i.e., offset, spacer and a single diffusion implant. The device silicon thickness is thin enough to permit the diffusion implants to abut the buried insulator but thick enough to form a contacting silicide. Stress layer liner films are used both over nFET and pFET device regions to enhance performance.
摘要翻译：本发明提供了一种包括薄SOI区域的半导体器件结构，其中SOI器件形成有可选的单个薄扩散，即偏移，间隔物和单个扩散注入。器件硅厚度足够薄以允许扩散植入物邻接埋入的绝缘体，但是足够厚以形成接触硅化物。应力层衬垫膜都用于nFET和pFET器件区域，以提高性能。

8. 发明申请

US20090186455A1 DISPOSABLE METALLIC OR SEMICONDUCTOR GATE SPACER 失效
标题翻译：可拆卸金属或半导体门间隔
公开(公告)号：US20090186455A1
公开(公告)日：2009-07-23
申请号：US12016326
申请日：2008-01-18
申请人： Stephen W. Bedell , Michael Chudzik , William K. Henson , Naim Moumen , Vijay Narayanan , Devendra K. Sadana , Kathryn T. Schonenberg , Ghavam Shahidi
发明人： Stephen W. Bedell , Michael Chudzik , William K. Henson , Naim Moumen , Vijay Narayanan , Devendra K. Sadana , Kathryn T. Schonenberg , Ghavam Shahidi
IPC分类号： H01L21/8238
CPC分类号： H01L29/7847 , H01L21/324 , H01L21/823807 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： A disposable spacer is formed directly on or in close proximity to the sidewalls of a gate electrode and a gate dielectric. The disposable spacer comprises a material that scavenges oxygen such as a metal, a metal nitride, or a semiconductor material having high reactivity with oxygen. The disposable gate spacer absorbs any oxygen during subsequent high temperature processing such as a stress memorization anneal. A metal is deposited over, and reacted with, the gate electrode and source and drain regions to form metal semiconductor alloy regions. The disposable gate spacer is subsequently removed selective to the metal semiconductor alloy regions. A porous or non-porous low-k dielectric material is deposited to provide a low parasitic capacitance between the gate electrode and the source and drain regions. The gate dielectric maintains the original dielectric constant since the disposable gate spacer prevents absorption of additional oxygen during high temperature processes.
摘要翻译：一次性间隔物直接形成在栅极电极和栅极电介质的侧壁上或紧邻栅电极的侧壁上。一次性间隔物包括清除氧的材料，例如金属，金属氮化物或具有高氧反应性的半导体材料。一次性栅极间隔件在随后的高温处理例如应力记忆退火期间吸收任何氧气。将金属沉积在栅电极和源极和漏极区上并与其反应以形成金属半导体合金区域。一次性栅极间隔物随后被选择性地移除到金属半导体合金区域。沉积多孔或非多孔低k电介质材料以在栅极电极和源极和漏极区域之间提供低的寄生电容。栅极电介质保持原始介电常数，因为一次性栅极间隔物可防止在高温过程中吸收额外的氧。

9. 发明申请

US20090045462A1 ULTRATHIN SOI CMOS DEVICES EMPLOYING DIFFERENTIAL STI LINERS 失效
标题翻译： ULTRATHIN SOI CMOS器件采用差分STI衬线
公开(公告)号：US20090045462A1
公开(公告)日：2009-02-19
申请号：US11839272
申请日：2007-08-15
申请人： Zhibin Ren , Ghavam Shahidi , Dinkar V. Singh , Jeffrey W. Sleight , Xinhui Wang
发明人： Zhibin Ren , Ghavam Shahidi , Dinkar V. Singh , Jeffrey W. Sleight , Xinhui Wang
IPC分类号： H01L21/8238 , H01L27/12
CPC分类号： H01L21/84 , H01L21/76229 , H01L21/76283 , H01L27/1203 , H01L29/7846
摘要： An oxynitride pad layer and a masking layer are formed on an ultrathin semiconductor-on-insulator substrate containing a top semiconductor layer comprising silicon. A first portion of a shallow trench is patterned in a top semiconductor layer by lithographic masking of an NFET region and an etch, in which exposed portions of the buried insulator layer is recessed and the top semiconductor layer is undercut. A thick thermal silicon oxide liner is formed on the exposed sidewalls and bottom peripheral surfaces of a PFET active area to apply a high laterally compressive stress. A second portion of the shallow trench is formed by lithographic masking of a PFET region including the PFET active area. A thin thermal silicon oxide or no thermal silicon oxide is formed on exposed sidewalls of the NFET active area, which is subjected to a low lateral compressive stress or no lateral compressive stress.
摘要翻译：在包含硅的顶部半导体层的超薄绝缘体上的基板上形成氧氮化物衬垫层和掩模层。浅沟槽的第一部分通过NFET区域和蚀刻的光刻掩模在顶部半导体层中图案化，其中埋入绝缘体层的暴露部分凹陷并且顶部半导体层被切割。在PFET有源区的暴露的侧壁和底部周边表面上形成厚的热氧化硅衬垫以施加高横向压应力。浅沟槽的第二部分通过包括PFET有源区的PFET区域的光刻掩模形成。在NFET有源区的暴露的侧壁上形成薄的热氧化硅或不存在热氧化硅，其经受低的侧向压应力或没有横向压应力。

10. 发明申请

US20080050887A1 METHOD FOR FABRICATING SiGe-ON-INSULATOR (SGOI) AND Ge-ON-INSULATOR (GOI) SUBSTRATES 有权
标题翻译：用于制造SiGe-ON绝缘体（SGOI）和Ge-ON-Insulator（GOI）衬底的方法
公开(公告)号：US20080050887A1
公开(公告)日：2008-02-28
申请号：US11924207
申请日：2007-10-25
申请人： Tze-chiang Chen , Guy Cohen , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
发明人： Tze-chiang Chen , Guy Cohen , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
IPC分类号： H01L21/30
CPC分类号： H01L21/76254 , H01L31/02327 , H01L31/028 , H01L31/1812 , Y02E10/547
摘要： A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.
摘要翻译：提供了绝缘体上（锗）绝缘体（GOI）衬底材料的方法，通过该方法生产的GOI衬底材料和至少可以包括本发明的GOI衬底材料的各种结构。 GOI衬底材料至少包括衬底，位于衬底顶部的掩埋绝缘体层，以及位于掩埋绝缘体层顶部的优选纯Ge的Ge含有层。在本发明的GOI基板材料中，Ge含有层也可以称为GOI膜。 GOI膜是可以形成器件的本发明的基底材料的层。

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