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1. 发明申请

US20050048778A1 Use of thin SOI to inhibit relaxation of SiGe layers 有权
标题翻译：使用薄SOI抑制SiGe层的弛豫
公开(公告)号：US20050048778A1
公开(公告)日：2005-03-03
申请号：US10654232
申请日：2003-09-03
申请人： Stephen Bedell , Huajie Chen , Keith Fogel , Devendra Sadana
发明人： Stephen Bedell , Huajie Chen , Keith Fogel , Devendra Sadana
IPC分类号： H01L29/161 , C30B29/52 , C30B31/02 , H01L21/02 , H01L21/20 , H01L21/205 , H01L21/762 , H01L21/8238 , H01L27/12 , H01L29/04 , C30B1/00 , C30B3/00 , C30B5/00 , C30B28/02 , H01L21/302 , H01L21/461
CPC分类号： H01L21/7624 , C30B29/52 , C30B31/02 , H01L21/02381 , H01L21/02532 , H01L21/02694 , Y10T428/24917
摘要： High-quality, metastable SiGe alloys are formed on SOI substrates having an SOI layer of about 500 Å or less, the SiGe layers can remain substantially fully strained compared to identical SiGe layers formed on thicker SOI substrates and subsequently annealed and/or oxidized at high temperatures. The present invention thus provides a method of ‘frustrating’ metastable strained SiGe layers by growing them on thin, clean and high-quality SOI substrates.
摘要翻译：在具有大约等于或小于等于或等于SOI层的SOI层的SOI衬底上形成高质量的亚稳态SiGe合金，与形成在较厚SOI衬底上的相同SiGe层相比，SiGe层可以保持基本上完全变形，并随后在高温下退火和/或氧化温度。因此，本发明提供了一种通过在薄的，清洁的和高质量的SOI衬底上生长它们来“挫败”亚稳应变的SiGe层的方法。

2. 发明申请

US20070105350A1 DEFECT REDUCTION BY OXIDATION OF SILICON 失效
标题翻译：通过氧化硅减少缺陷
公开(公告)号：US20070105350A1
公开(公告)日：2007-05-10
申请号：US11619040
申请日：2007-01-02
申请人： Stephen Bedell , Huajie Chen , Anthony Domenicucci , Keith Fogel , Devendra Sadana
发明人： Stephen Bedell , Huajie Chen , Anthony Domenicucci , Keith Fogel , Devendra Sadana
IPC分类号： C30B1/00 , H01L21/20
CPC分类号： H01L21/7624 , Y10S438/933 , Y10T428/12674
摘要： A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate materials which may be used as a template for strained Si is described. A silicon-on-insulator substrate with a very thin top Si layer is used as a template for compressively strained SiGe growth. Upon relaxation of the SiGe layer at a sufficient temperature, the nature of the dislocation motion is such that the strain-relieving defects move downward into the thin Si layer when the buried oxide behaves semi-viscously. The thin Si layer is consumed by oxidation of the buried oxide/thin Si interface. This can be accomplished by using internal oxidation at high temperatures. In this way the role of the original thin Si layer is to act as a sacrificial defect sink during relaxation of the SiGe alloy that can later be consumed using internal oxidation.
摘要翻译：描述了可以用作应变Si的模板的制造高质量，基本上松弛的绝缘体上硅衬底材料的方法。使用具有非常薄的顶部Si层的绝缘体上硅衬底作为压缩应变SiGe生长的模板。当SiGe层在足够的温度下弛豫时，位错运动的性质使得当埋入的氧化物半粘着时，应变消除缺陷向下移动到薄的Si层中。薄Si层被掩埋氧化物/薄Si界面的氧化所消耗。这可以通过在高温下使用内部氧化来实现。以这种方式，原始薄Si层的作用是在SiGe合金的弛豫期间用作牺牲缺陷陷阱，SiGe合金随后可以使用内部氧化来消耗。

3. 发明申请

US20080116483A1 HIGH-QUALITY SGOI BY ANNEALING NEAR THE ALLOY MELTING POINT 失效
标题翻译：高品质SGOI通过靠近合金熔点来退火
公开(公告)号：US20080116483A1
公开(公告)日：2008-05-22
申请号：US12027561
申请日：2008-02-07
申请人： Stephen Bedell , Huajie Chen , Anthony Domenicucci , Keith Fogel , Richard Murphy , Devendra Sadana
发明人： Stephen Bedell , Huajie Chen , Anthony Domenicucci , Keith Fogel , Richard Murphy , Devendra Sadana
IPC分类号： H01L29/165
CPC分类号： H01L21/26506 , H01L21/324 , H01L21/7624 , H01L21/76254 , H01L29/1054
摘要： A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom. In one embodiment, the heating step includes an oxidation process that is performed at a temperature from about 1230° to about 1320° C. for a time period of less than about 2 hours. This embodiment provides SGOI substrate that have minimal surface pitting and reduced crosshatching.
摘要翻译：提供一种形成低缺陷，基本上松弛的绝缘体上硅衬底材料的方法。该方法包括首先在耐Ge扩散的阻挡层上存在的第一单晶Si层的表面上形成含Ge层。然后在接近最终SiGe合金的熔点的温度下进行加热步骤，并且在保留Ge的同时延缓形成堆垛层错缺陷。加热步骤允许Ge遍及第一单晶Si层和含Ge层的相互扩散，从而在阻挡层顶部形成基本松弛的单晶SiGe层。此外，由于加热步骤在接近最终SiGe合金的熔点的温度下进行，所以由于弛豫而在单晶SiGe层中持续存在的缺陷被有效地湮灭。在一个实施方案中，加热步骤包括氧化过程，其在约1230℃至约1320℃的温度下进行约少于约2小时的时间。该实施例提供具有最小表面点蚀和减少的交叉阴影的SGOI衬底。

4. 发明申请

US20060057403A1 Use of thin SOI to inhibit relaxation of SiGe layers 审中-公开
公开(公告)号：US20060057403A1
公开(公告)日：2006-03-16
申请号：US11268096
申请日：2005-11-07
申请人： Stephen Bedell , Huajie Chen , Keith Fogel , Devendra Sadana
发明人： Stephen Bedell , Huajie Chen , Keith Fogel , Devendra Sadana
IPC分类号： B32B13/04 , B32B15/04 , B32B9/00
CPC分类号： H01L21/7624 , C30B29/52 , C30B31/02 , H01L21/02381 , H01L21/02532 , H01L21/02694 , Y10T428/24917
摘要： High-quality, metastable SiGe alloys are formed on SOI substrates having an SOI layer of about 500 Å or less, the SiGe layers can remain substantially fully strained compared to identical SiGe layers formed on thicker SOI substrates and subsequently annealed and/or oxidized at high temperatures. The present invention thus provides a method of ‘frustrating’ metastable strained SiGe layers by growing them on thin, clean and high-quality SOI substrates.

5. 发明申请

US20060027808A1 METHOD OF FORMING STRAINED SILICON MATERIALS WITH IMPROVED THERMAL CONDUCTIVITY 有权
标题翻译：形成具有改善的导热性的应变硅材料的方法
公开(公告)号：US20060027808A1
公开(公告)日：2006-02-09
申请号：US10710826
申请日：2004-08-05
申请人： Stephen Bedell , Huajie Chen , Keith Fogel , Ryan Mitchell , Devendra Sadana
发明人： Stephen Bedell , Huajie Chen , Keith Fogel , Ryan Mitchell , Devendra Sadana
IPC分类号： H01L29/12 , H01L21/20
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02507 , H01L21/02532
摘要： A method is disclosed for forming a strained Si layer on SiGe, where the SiGe layer has improved thermal conductivity. A first layer of Si or Ge is deposited on a substrate in a first depositing step; a second layer of the other element is deposited on the first layer in a second depositing step; and the first and second depositing steps are repeated so as to form a combined SiGe layer having a plurality of Si layers and a plurality of Ge layers. The respective thicknesses of the Si layers and Ge layers are in accordance with a desired composition ratio of the combined SiGe layer (so that a 1:1 ratio typically is realized with Si and Ge layers each about 10 Å thick). The combined SiGe layer is characterized as a digital alloy of Si and Ge having a thermal conductivity greater than that of a random alloy of Si and Ge. This method may further include the step of depositing a Si layer on the combined SiGe layer; the combined SiGe layer is characterized as a relaxed SiGe layer, and the Si layer is a strained Si layer. For still greater thermal conductivity in the SiGe layer, the first layer and second layer may be deposited so that each layer consists essentially of a single isotope.
摘要翻译：公开了一种在SiGe上形成应变Si层的方法，其中SiGe层具有改善的导热性。在第一沉积步骤中将第一层Si或Ge沉积在衬底上; 另一个元件的第二层在第二沉积步骤中沉积在第一层上; 并且重复第一和第二沉积步骤以形成具有多个Si层和多个Ge层的组合SiGe层。 Si层和Ge层的各自的厚度根据组合的SiGe层的期望组成比（使得Si和Ge层的厚度通常为1：1，每个厚度大约为10埃）。组合的SiGe层的特征在于具有大于Si和Ge的随机合金的热导率的Si和Ge的数字合金。该方法还可以包括在组合的SiGe层上沉积Si层的步骤; 组合的SiGe层被表征为弛豫的SiGe层，并且Si层是应变的Si层。对于SiGe层中更高的热导率，可以沉积第一层和第二层，使得每层基本上由单一同位素组成。

6. 发明申请

US20060011906A1 Ion implantation for suppression of defects in annealed SiGe layers 审中-公开
标题翻译：用于抑制退火SiGe层缺陷的离子注入
公开(公告)号：US20060011906A1
公开(公告)日：2006-01-19
申请号：US10890765
申请日：2004-07-14
申请人： Stephen Bedell , Huajie Chen , Keith Fogel , Devendra Sadana , Ghavam Shahidi
发明人： Stephen Bedell , Huajie Chen , Keith Fogel , Devendra Sadana , Ghavam Shahidi
IPC分类号： H01L29/06
CPC分类号： H01L21/26506 , H01L21/02381 , H01L21/02532 , H01L21/02694 , H01L21/2658
摘要： A method for fabricating substantially relaxed SiGe alloy layers with a reduced planar defect density is disclosed. The method of the present invention includes forming a strained Ge-containing layer on a surface of a Si-containing substrate; implanting ions at or below the Ge-containing layer/Si-containing substrate interface and heating to form a substantially relaxed SiGe alloy layer that has a reduced planar defect density. A substantially relaxed SiGe-on-insulator substrate material having a SiGe layer with a reduced planar defect density as well as heterostructures containing the same are also provided.
摘要翻译：公开了一种用于制造具有减小的平面缺陷密度的基本上松弛的SiGe合金层的方法。本发明的方法包括在含Si基材的表面上形成应变的含Ge层; 在含锗层/含Si衬底界面处或下方注入离子，并加热以形成具有减小的平面缺陷密度的基本上松弛的SiGe合金层。还提供了具有具有减小的平面缺陷密度的SiGe层以及含有该SiGe层的异质结构的基本上松弛的绝缘体上硅衬底材料。

7. 发明申请

US20050221591A1 Method of forming high-quality relaxed SiGe alloy layers on bulk Si substrates 审中-公开
标题翻译：在大量Si衬底上形成高品质的松弛SiGe合金层的方法
公开(公告)号：US20050221591A1
公开(公告)日：2005-10-06
申请号：US10818572
申请日：2004-04-06
申请人： Stephen Bedell , Huajie Chen , Joel de Souza , Keith Fogel , Devendra Sadana , Ghavam Shahidi
发明人： Stephen Bedell , Huajie Chen , Joel de Souza , Keith Fogel , Devendra Sadana , Ghavam Shahidi
IPC分类号： C30B1/00 , H01L21/20 , H01L21/3063 , H01L21/36 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L21/3063 , H01L21/02381 , H01L21/0245 , H01L21/02513 , H01L21/02532 , H01L21/02658
摘要： A method of forming a high-quality relaxed SiGe alloy layer on a bulk Si-containing substrate is provided. The method of the present invention includes growing a strained SiGe alloy layer on a Si-containing substrate that has a porous Si-containing layer at or near the surface of the Si-containing substrate. The porous layer is formed by an electrolytic anodization process. The pores create free volume below the strained SiGe layer which can serve to accommodate strain relaxation during SiGe deposition or a subsequent heating step. The subsequent heating step is optional and is performed to further increase the relaxation of the SiGe alloy layer. The buried porous structure allows for a unique relaxation mechanism compared to prior art methods.
摘要翻译：提供了在体积含Si衬底上形成高品质的弛豫SiGe合金层的方法。本发明的方法包括在含Si衬底上生长应变SiGe合金层，该Si基合金层在含Si衬底的表面处或附近具有多孔含Si层。多孔层通过电解阳极氧化处理形成。孔隙在应变SiGe层之下产生自由体积，其可用于在SiGe沉积或随后的加热步骤期间适应应变松弛。随后的加热步骤是可选的并且进行以进一步增加SiGe合金层的松弛。与现有技术方法相比，埋入的多孔结构允许独特的松弛机制。

8. 发明申请

US20050003229A1 Defect reduction by oxidation of silicon 失效
标题翻译：通过氧化硅来减少缺陷
公开(公告)号：US20050003229A1
公开(公告)日：2005-01-06
申请号：US10610612
申请日：2003-07-01
申请人： Stephen Bedell , Huajie Chen , Anthony Domenicucci , Keith Fogel , Devendra Sadana
发明人： Stephen Bedell , Huajie Chen , Anthony Domenicucci , Keith Fogel , Devendra Sadana
IPC分类号： H01L27/12 , H01L21/02 , H01L21/20 , H01L21/762 , H01L21/425 , B32B15/00
CPC分类号： H01L21/7624 , Y10S438/933 , Y10T428/12674
摘要： A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate materials which may be used as a template for strained Si is described. A silicon-on-insulator substrate with a very thin top Si layer is used as a template for compressively strained SiGe growth. Upon relaxation of the SiGe layer at a sufficient temperature, the nature of the dislocation motion is such that the strain-relieving defects move downward into the thin Si layer when the buried oxide behaves semi-viscously. The thin Si layer is consumed by oxidation of the buried oxide/thin Si interface. This can be accomplished by using internal oxidation at high temperatures. In this way the role of the original thin Si layer is to act as a sacrificial defect sink during relaxation of the SiGe alloy that can later be consumed using internal oxidation.
摘要翻译：描述了可以用作应变Si的模板的制造高质量，基本上松弛的绝缘体上硅衬底材料的方法。使用具有非常薄的顶部Si层的绝缘体上硅衬底作为压缩应变SiGe生长的模板。当SiGe层在足够的温度下弛豫时，位错运动的性质使得当埋入的氧化物半粘着时，应变消除缺陷向下移动到薄的Si层中。薄Si层被掩埋氧化物/薄Si界面的氧化所消耗。这可以通过在高温下使用内部氧化来实现。以这种方式，原始薄Si层的作用是在SiGe合金的弛豫期间用作牺牲缺陷陷阱，SiGe合金随后可以使用内部氧化来消耗。

9. 发明申请

US20050148162A1 Method of preventing surface roughening during hydrogen pre-bake of SiGe substrates using chlorine containing gases 审中-公开
标题翻译：在使用含氯气体的SiGe衬底的氢预烘烤期间防止表面粗糙化的方法
公开(公告)号：US20050148162A1
公开(公告)日：2005-07-07
申请号：US10751207
申请日：2004-01-02
申请人： Huajie Chen , Dan Mocuta , Richard Murphy , Stephen Bedell , Devendra Sadana
发明人： Huajie Chen , Dan Mocuta , Richard Murphy , Stephen Bedell , Devendra Sadana
IPC分类号： C30B25/02 , C30B29/52 , H01L21/20 , H01L21/205 , H01L21/306 , H01L21/36 , H01L21/44
CPC分类号： H01L21/02046 , C30B25/02 , C30B29/52 , H01L21/02052 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/02658 , H01L21/02661
摘要： The invention forms an epitaxial silicon-containing layer on a silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface and avoids creating a rough surface upon which the epitaxial silicon-containing layer is grown. In order to avoid creating the rough surface, the invention first performs a hydrofluoric acid etching process on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. This etching process removes most of oxide from the surface, and leaves only a sub-monolayer of oxygen (typically 1×1013-1×1015/cm2 of oxygen) at the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. The invention then performs a hydrogen pre-bake process in a chlorine containing environment which heats the silicon germanium, strained silicon, or thin silicon-on-insulator surface sufficiently to remove the remaining oxygen from the surface. By introducing a small amount of chlorine containing gases, the heating processes avoid changing the roughness of the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. Then the process of epitaxially growing the epitaxial silicon-containing layer on the silicon germanium, patterned strained silicon, or patterned silicon-on-insulator surface is performed.
摘要翻译：本发明在硅锗，图案化的应变硅或图案化的绝缘体上硅表面上形成外延含硅层，并避免产生外延含硅层生长的粗糙表面。为了避免产生粗糙表面，本发明首先对硅锗，图案化应变硅或图案化的绝缘体上硅表面进行氢氟酸蚀刻工艺。该蚀刻工艺从表面除去大部分氧化物，并且仅留下氧气的亚单层（通常为1×10 13/1×10 15 / cm 2以上）的氧），图案化的应变硅或图案化的绝缘体上硅表面。然后，本发明在含氯环境中进行氢预烘烤过程，其中充分加热硅锗，应变硅或薄的绝缘体上硅表面以从表面除去剩余的氧。通过引入少量的含氯气体，加热过程避免改变硅锗，图案化的应变硅或图案化的绝缘体上硅表面的粗糙度。然后进行外延生长硅锗，图案化应变硅或图案化硅绝缘体表面上的外延硅含量层的工艺。

10. 发明申请

US20070128840A1 Method of forming thin sgoi wafers with high relaxation and low stacking fault defect density 失效
标题翻译：形成具有高松弛和低堆垛缺陷缺陷密度的薄sgoi晶片的方法
公开(公告)号：US20070128840A1
公开(公告)日：2007-06-07
申请号：US10597066
申请日：2004-01-16
申请人： Huajie Chen , Stephen Bedell , Devendra Sadana , Dan Mocuta
发明人： Huajie Chen , Stephen Bedell , Devendra Sadana , Dan Mocuta
IPC分类号： H01L21/20
CPC分类号： H01L21/76256 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02664 , H01L21/31658 , H01L21/84 , H01L29/1054 , H01L29/78687
摘要： A method of forming a silicon germanium on insulator (SGOI) structure. A SiGe layer is deposited on an SOI wafer. Thermal mixing of the SiGe and Si layers is performed to form a thick SGOI with high relaxation and low stacking fault defect density. The SiGe layer is then thinned to a desired final thickness. The Ge concentration, the amount of relaxation, and stacking fault defect density are unchanged by the thinning process. A thin SGOI film is thus obtained with high relaxation and low stacking fault defect density. A layer of Si is then deposited on the thin SGOI wafer. The method of thinning includes low temperature (550° C.-700° C.) HIPOX or steam oxidation, in-situ HCl etching in an epitaxy chamber, or CMP. A rough SiGe surface resulting from HIPOX or steam oxidation thinning is smoothed with a touch-up CMP, in-situ hydrogen bake and SiGe buffer layer during strained Si deposition, or heating the wafer in a hydrogen environment with a mixture of gases HCl, DCS and GeH4.
摘要翻译：一种形成绝缘体上硅锗（SGOI）结构的方法。 SiGe层沉积在SOI晶片上。进行SiGe和Si层的热混合以形成具有高松弛和低堆垛层错缺陷密度的厚SGOI。然后将SiGe层变薄至所需的最终厚度。稀释过程，Ge浓度，松弛量和堆垛层错缺陷密度均不变。因此获得了具有高松弛和低堆垛层错缺陷密度的薄SGOI膜。然后在薄SGOI晶片上沉积一层Si。稀释方法包括低温（550℃-700℃）HIPOX或蒸汽氧化，在外延室中进行原位HCl蚀刻或CMP。由HIPOX或蒸汽氧化稀化产生的粗糙SiGe表面在应变Si沉积期间用接触式CMP，原位氢气烘烤和SiGe缓冲层进行平滑，或者在氢气环境中用HCl，DCS混合气体加热晶片和GeH 4。

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