专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08440494B2 Single-crystalline silicon alkaline texturing with glycerol or ethylene glycol additives 有权
标题翻译：甘油或乙二醇添加剂的单晶硅碱性织构
公开(公告)号：US08440494B2
公开(公告)日：2013-05-14
申请号：US13112465
申请日：2011-05-20
申请人： Kathryn C. Fisher , Jun Liu , Satyavolu S. Papa Rao , George G. Totir , James Vichiconti
发明人： Kathryn C. Fisher , Jun Liu , Satyavolu S. Papa Rao , George G. Totir , James Vichiconti
IPC分类号： H01L21/00
CPC分类号： C09K13/02 , H01L31/02363 , Y02E10/50
摘要： Alternative additives that can be used in place of isopropyl alcohol in aqueous alkaline etchant solutions for texturing a surface of a single-crystalline silicon substrate are provided. The alternative additives do not have volatile constituents, yet can be used in an aqueous alkaline etchant solution to provide a pyramidal shaped texture surface to the single-crystalline silicon substrate that is exposed to such an etchant solution. Also provided is a method of forming a textured silicon surface. The method includes immersing a single-crystalline silicon substrate into an etchant solution to form a pyramid shaped textured surface on the single-crystalline silicon substrate. The etchant solution includes an alkaline component, silicon (etched into the solution as a bath conditioner) and glycerol or ethylene glycol as an additive. The textured surface of the single-crystalline silicon substrate has (111) faces that are now exposed.
摘要翻译：提供了可用于代替异丙醇的水性碱性蚀刻剂溶液中用于织构单晶硅衬底的表面的替代添加剂。替代的添加剂不具有挥发性成分，但也可用于碱性蚀刻剂水溶液中以向暴露于这种蚀刻剂溶液的单晶硅衬底提供金字塔形的纹理表面。还提供了形成纹理硅表面的方法。该方法包括将单晶硅衬底浸入蚀刻剂溶液中以在单晶硅衬底上形成棱锥形织构表面。蚀刻剂溶液包括碱性组分，硅（作为浴调节剂蚀刻到溶液中）和甘油或乙二醇作为添加剂。单晶硅衬底的纹理表面具有现在暴露的（111）面。

2. 发明申请

US20120286236A1 SUPER LATTICE/QUANTUM WELL NANOWIRES 有权
标题翻译：超级尺寸/质量好的纳米尺寸
公开(公告)号：US20120286236A1
公开(公告)日：2012-11-15
申请号：US13555383
申请日：2012-07-23
申请人： Harold J. HOVEL , Qiang Huang , Xiaoyan Shao , James Vichiconti , George F. Walker
发明人： Harold J. HOVEL , Qiang Huang , Xiaoyan Shao , James Vichiconti , George F. Walker
IPC分类号： H01L29/06 , B82Y99/00
CPC分类号： H01L31/18 , B82Y10/00 , B82Y30/00 , C30B29/02 , C30B29/06 , C30B29/40 , C30B29/52 , C30B29/60 , C30B29/605 , C30B33/10 , H01L21/30604 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/125 , H01L31/0352 , H01L33/20
摘要： Segmented semiconductor nanowires are manufactured by removal of material from a layered structure of two or more semiconductor materials in the absence of a template. The removal takes place at some locations on the surface of the layered structure and continues preferentially along the direction of a crystallographic axis, such that nanowires with a segmented structure remain at locations where little or no removal occurs. The interface between different segments can be perpendicular to or at angle with the longitudinal direction of the nanowire.
摘要翻译：在没有模板的情况下通过从两种或更多种半导体材料的层状结构中去除材料来制造分段半导体纳米线。去除在层状结构的表面上的某些位置处发生，并且优选地沿着结晶轴的方向延伸，使得具有分段结构的纳米线保持在很少或不发生去除的位置。不同片段之间的界面可以垂直于纳米线的纵向方向或与之相垂直。

3. 发明授权

US07528056B2 Low-cost strained SOI substrate for high-performance CMOS technology 有权
标题翻译：低成本应变SOI衬底，用于高性能CMOS技术
公开(公告)号：US07528056B2
公开(公告)日：2009-05-05
申请号：US11622543
申请日：2007-01-12
申请人： Meikei Ieong , Douglas C. La Tulipe, Jr. , Leathen Shi , Anna W. Topol , James Vichiconti , Albert M. Young
发明人： Meikei Ieong , Douglas C. La Tulipe, Jr. , Leathen Shi , Anna W. Topol , James Vichiconti , Albert M. Young
IPC分类号： H01L21/36 , H01L21/20
CPC分类号： H01L21/02658 , H01L21/02667 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/78 , H01L29/7843
摘要： A cost-effective and simple method of fabricating strained semiconductor-on-insulator (SSOI) structures which avoids epitaxial growth and subsequent wafer bonding processing steps is provided. In accordance with the present invention, a strain-memorization technique is used to create strained semiconductor regions on a SOI substrate. The transistors formed on the strained semiconductor regions have higher carrier mobility because the Si regions have been strained. The inventive method includes (i) ion implantation to create a thin amorphization layer, (ii) deposition of a high stress film on the amorphization layer, (iii) a thermal anneal to recrystallize the amorphization layer, and (iv) removal of the stress film. Because the SOI substrate was under stress during the recrystallization process, the final semiconductor layer will be under stress as well. The amount of stress and the polaity (tensile or compressive) of the stress can be controlled by the type and thickness of the stress films.
摘要翻译：提供了一种制造应变绝缘体上半导体（SSOI）结构的成本有效和简单的方法，其避免了外延生长和随后的晶片接合处理步骤。根据本发明，使用应变记忆技术在SOI衬底上产生应变半导体区域。形成在应变半导体区域上的晶体管具有更高的载流子迁移率，因为Si区域已经变形。本发明的方法包括（i）离子注入以产生薄的非晶化层，（ii）在非晶化层上沉积高应力膜，（iii）热退火以使非晶化层重结晶，和（iv）去除应力电影。由于在再结晶过程中SOI衬底处于应力状态，所以最终的半导体层也将受到应力。应力的量和应力的极性（拉伸或压缩）可以通过应力膜的类型和厚度来控制。

4. 发明授权

US08878259B2 Super lattice/quantum well nanowires 有权
标题翻译：超晶格/量子阱纳米线
公开(公告)号：US08878259B2
公开(公告)日：2014-11-04
申请号：US13555383
申请日：2012-07-23
申请人： Harold J. Hovel , Qiang Huang , Xiaoyan Shao , James Vichiconti , George F. Walker
发明人： Harold J. Hovel , Qiang Huang , Xiaoyan Shao , James Vichiconti , George F. Walker
IPC分类号： H01L29/94 , H01L29/76 , H01L31/119 , H01L31/113 , H01L31/062 , H01L31/18 , B82Y10/00 , B82Y30/00 , C30B29/02 , C30B29/06 , C30B29/40 , C30B29/52 , C30B29/60 , C30B33/10 , H01L21/306 , H01L29/06 , H01L29/12 , H01L31/0352 , H01L33/20
CPC分类号： H01L31/18 , B82Y10/00 , B82Y30/00 , C30B29/02 , C30B29/06 , C30B29/40 , C30B29/52 , C30B29/60 , C30B29/605 , C30B33/10 , H01L21/30604 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/125 , H01L31/0352 , H01L33/20
摘要： Segmented semiconductor nanowires are manufactured by removal of material from a layered structure of two or more semiconductor materials in the absence of a template. The removal takes place at some locations on the surface of the layered structure and continues preferentially along the direction of a crystallographic axis, such that nanowires with a segmented structure remain at locations where little or no removal occurs. The interface between different segments can be perpendicular to or at angle with the longitudinal direction of the nanowire.
摘要翻译：在没有模板的情况下通过从两种或更多种半导体材料的层状结构中去除材料来制造分段半导体纳米线。去除在层状结构的表面上的某些位置处发生，并且优选地沿着结晶轴的方向延伸，使得具有分段结构的纳米线保持在很少或不发生去除的位置。不同片段之间的界面可以垂直于纳米线的纵向方向或与之相垂直。

5. 发明申请

US20110062494A1 STRUCTURE WITH ISOTROPIC SILICON RECESS PROFILE IN NANOSCALE DIMENSIONS 有权
标题翻译：结构与纳米尺度尺寸上的等温硅吸收型材
公开(公告)号：US20110062494A1
公开(公告)日：2011-03-17
申请号：US12561704
申请日：2009-09-17
申请人： Sebastian Ulrich Engelmann , Nicholas C.M. Fuller , Eric Andrew Joseph , Isaac Lauer , Ryan M. Martin , James Vichiconti , Ying Zhang
发明人： Sebastian Ulrich Engelmann , Nicholas C.M. Fuller , Eric Andrew Joseph , Isaac Lauer , Ryan M. Martin , James Vichiconti , Ying Zhang
IPC分类号： H01L29/78 , H01L21/20 , H01L29/06 , H01L21/302
CPC分类号： H01L29/7848 , H01L21/0237 , H01L21/02639 , H01L21/3065 , H01L21/3083 , H01L29/165 , H01L29/66636 , H01L29/78 , Y10S438/938
摘要： A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.
摘要翻译：通过使用可以是栅极间隔物的掩模层的半导体材料层中的各向异性蚀刻形成沟槽。在一个实施例中，仅在包括沟槽的侧壁的半导体结构的垂直侧壁处在低温温度下提供吸附的氟层。一旦温度升高到低于低温的温度，吸附的氟层就可去除受控量的底层半导体材料。沟槽可以用另一种半导体材料填充以在半导体材料层中产生应力。在另一个实施例中，通过基于等离子体的蚀刻以受控的速率横向蚀刻半导体材料，而邻接氧化物衬垫的水平部分防止半导体材料从沟槽的底表面蚀刻。

6. 发明申请

US20080266502A1 METHOD OF PRODUCING UV STABLE LIQUID CRYSTAL ALIGNMENT 有权
标题翻译：生产紫外线稳定液晶对准的方法
公开(公告)号：US20080266502A1
公开(公告)日：2008-10-30
申请号：US11742474
申请日：2007-04-30
申请人： George Liang-Tai Chiu , Steven Alan Cordes , James Prtrick Doyle , Matthew J. Farinelli , Minhua Lu , Hiroki Nakano , Ronald Nunes , James Vichiconti
发明人： George Liang-Tai Chiu , Steven Alan Cordes , James Prtrick Doyle , Matthew J. Farinelli , Minhua Lu , Hiroki Nakano , Ronald Nunes , James Vichiconti
IPC分类号： G02F1/1337 , B05D5/06 , G03F7/00 , C30B33/00
CPC分类号： C30B25/18 , G02F1/13378
摘要： In a liquid crystal display device, a method for creating desirable pretilt angle by means of topography of the substrates, such as a surface that is sloped with respect to the surface of the electrodes. In combination with a low pretilt but highly photo-stable alignment layer, which may be very resistant to high levels of ultraviolet radiation, a high pretilt and photo-stable alignment structure is generated, by essentially combining two incompatible technical approaches. The ever more stringent requirements for projection displays are met. The methods for producing such sloped surfaces and the considerations related to design of the sloped surfaces are disclosed.
摘要翻译：在液晶显示装置中，通过诸如相对于电极表面倾斜的表面的基板的形貌来产生理想的预倾斜角的方法。结合一个低预倾斜但高度光稳定的取向层，其可以非常耐高水平的紫外线辐射，通过基本上组合两种不相容的技术方法，产生高预倾斜和光稳定对准结构。对投影显示器的要求越来越严格。公开了用于制造这种倾斜表面的方法以及与倾斜表面的设计有关的考虑。

7. 发明申请

US20050114068A1 THERMAL MEASURMENTS OF ELECTRONIC DEVICES DURING OPERATION 失效
标题翻译：电子设备在运行期间的热量测量
公开(公告)号：US20050114068A1
公开(公告)日：2005-05-26
申请号：US10699123
申请日：2003-10-30
申请人： S. Chey , Hendrik Hamann , James Lacey , James Vichiconti , Robert von Gutfeld
发明人： S. Chey , Hendrik Hamann , James Lacey , James Vichiconti , Robert von Gutfeld
IPC分类号： G01K1/02 , G01K1/00
CPC分类号： G01K1/026
摘要： A system and method for measuring thermal distributions of an electronic device during operation is disclosed. The system includes an electronic device, a heat sink adjacent to the electronic device and an electrical-insulating layer disposed on the electronic device so as to separate the electronic device and the heat sink. The system further includes a plurality of thermal sensors located on the electrical-insulating layer, each of the plurality of thermal sensors in a different location. The plurality of thermal sensors is located within one or more thin film circuit layers disposed adjacent to the electrical insulating layer. The system further includes a module for receiving thermal information from the plurality of thermal sensors during operation of the electronic device. The system further includes a processor coupled to the module for generating a thermal distribution of the electronic device based on the thermal information received from the plurality of thermal sensors.
摘要翻译：公开了一种用于测量操作期间电子设备的热分布的系统和方法。该系统包括电子设备，与电子设备相邻的散热器以及设置在电子设备上以分离电子设备和散热器的电绝缘层。该系统还包括位于电绝缘层上的多个热传感器，多个热传感器中的每一个处于不同的位置。多个热传感器位于邻近电绝缘层设置的一个或多个薄膜电路层内。该系统还包括用于在电子设备的操作期间从多个热传感器接收热信息的模块。该系统还包括耦合到模块的处理器，用于基于从多个热传感器接收的热信息产生电子设备的热分布。

8. 发明申请

US20120193680A1 STRUCTURE WITH ISOTROPIC SILICON RECESS PROFILE IN NANOSCALE DIMENSIONS 审中-公开
公开(公告)号：US20120193680A1
公开(公告)日：2012-08-02
申请号：US13442011
申请日：2012-04-09
申请人： Sebastian Ulrich Engelmann , Nicholas C.M. Fuller , Eric Andrew Joseph , Isaac Lauer , Ryan M. Martin , James Vichiconti , Ying Zhang
发明人： Sebastian Ulrich Engelmann , Nicholas C.M. Fuller , Eric Andrew Joseph , Isaac Lauer , Ryan M. Martin , James Vichiconti , Ying Zhang
IPC分类号： H01L29/78 , H01L21/306 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/0237 , H01L21/02639 , H01L21/3065 , H01L21/3083 , H01L29/165 , H01L29/66636 , H01L29/78 , Y10S438/938
摘要： A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.

9. 发明授权

US08232171B2 Structure with isotropic silicon recess profile in nanoscale dimensions 有权
标题翻译：具有纳米级尺寸的各向同性硅凹槽轮廓的结构
公开(公告)号：US08232171B2
公开(公告)日：2012-07-31
申请号：US12561704
申请日：2009-09-17
申请人： Sebastian Ulrich Engelmann , Nicholas C. M. Fuller , Eric Andrew Joseph , Isaac Lauer , Ryan M. Martin , James Vichiconti , Ying Zhang
发明人： Sebastian Ulrich Engelmann , Nicholas C. M. Fuller , Eric Andrew Joseph , Isaac Lauer , Ryan M. Martin , James Vichiconti , Ying Zhang
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/0237 , H01L21/02639 , H01L21/3065 , H01L21/3083 , H01L29/165 , H01L29/66636 , H01L29/78 , Y10S438/938
摘要： A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.
摘要翻译：通过使用可以是栅极间隔物的掩模层的半导体材料层中的各向异性蚀刻形成沟槽。在一个实施例中，仅在包括沟槽的侧壁的半导体结构的垂直侧壁处在低温温度下提供吸附的氟层。一旦温度升高到低于低温的温度，吸附的氟层就可去除受控量的底层半导体材料。沟槽可以用另一种半导体材料填充以在半导体材料层中产生应力。在另一个实施例中，通过基于等离子体的蚀刻以受控的速率横向蚀刻半导体材料，而邻接氧化物衬垫的水平部分防止半导体材料从沟槽的底表面蚀刻。

10. 发明申请

US20110272287A1 METHOD FOR PATTERNING MAGNETIC FILMS 审中-公开
标题翻译：用于绘制磁片的方法
公开(公告)号：US20110272287A1
公开(公告)日：2011-11-10
申请号：US12776010
申请日：2010-05-07
申请人： Elizabeth A. Duch , Ronald Goldblatt , David L. Rath , Lubomyr T. Romankiw , Xiaoyan Shao , Steven E. Steen , James Vichiconti
发明人： Elizabeth A. Duch , Ronald Goldblatt , David L. Rath , Lubomyr T. Romankiw , Xiaoyan Shao , Steven E. Steen , James Vichiconti
IPC分类号： C25D5/34
CPC分类号： C25D5/48 , C25D5/02 , G11B5/855 , G11B5/858
摘要： A method of patterning magnetic devices and sensors by double etching, which includes forming a layer of dielectric on a substrate; depositing a thin adhesion layer and a thin seed layer; applying a thin resist frame to pattern a structure; cleaning the metal surface to prepare for plating; electroplating to fill up the structure and the uncovered field area, which uses a paddle cell with a permanent magnet providing magnetic field to induce magnetic orientation; stripping the resist frame; etching the seed layer/adhesion layer exposed below the resist frame down to the dielectric surface; etching the rest of magnetic materials and the seed layer using electrolytic etching in the field; etching the adhesion layer in the field, and repeating the steps for building structures with multiple levels.
摘要翻译：一种通过双蚀刻图案化磁性器件和传感器的方法，包括在衬底上形成电介质层; 沉积薄的粘合层和薄的种子层; 施加薄的抗蚀剂框架以构图结构; 清洗金属表面进行电镀准备; 电镀以填充结构和未覆盖的场区域，其使用具有提供磁场的永磁体的桨电池来诱导磁取向; 剥离抗蚀框架; 将暴露在抗蚀剂框架下方的种子层/粘合层蚀刻到电介质表面; 在现场使用电解蚀刻蚀刻其余的磁性材料和种子层; 在现场蚀刻粘合层，并重复用于建造具有多层结构的步骤。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式