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1. 发明申请

US20120187475A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120187475A1
公开(公告)日：2012-07-26
申请号：US13354599
申请日：2012-01-20
申请人： Shunpei YAMAZAKI , Hiromichi GODO
发明人： Shunpei YAMAZAKI , Hiromichi GODO
IPC分类号： H01L29/78
CPC分类号： H01L27/108 , H01L21/84 , H01L27/0688 , H01L27/1156 , H01L27/1207 , H01L27/1225 , H01L28/40 , H01L29/045 , H01L29/0653 , H01L29/0688 , H01L29/2003 , H01L29/24 , H01L29/36 , H01L29/4236 , H01L29/42364 , H01L29/66621 , H01L29/78 , H01L29/7833 , H01L29/785 , H01L29/7853 , H01L29/7854 , H01L29/7869
摘要： A conventional DRAM needs to be refreshed at an interval of several tens of milliseconds to hold data, which results in large power consumption. In addition, a transistor therein is frequently turned on and off; thus, deterioration of the transistor is also a problem. These problems become significant as the memory capacity increases and transistor miniaturization advances. A transistor is provided which includes a wide-gap semiconductor and has a trench structure including a trench for a gate electrode and a trench for element isolation. Even when the distance between a source electrode and a drain electrode is decreased, the occurrence of a short-channel effect can be suppressed by setting the depth of the trench for the gate electrode as appropriate.
摘要翻译：需要以几十毫秒的间隔刷新常规DRAM以保存数据，这导致大的功耗。此外，其中的晶体管经常被打开和关闭; 因此，晶体管的劣化也是一个问题。随着存储容量的增加和晶体管小型化的发展，这些问题变得越来越重要。提供了一种晶体管，其包括宽间隙半导体，并且具有包括用于栅电极的沟槽和用于元件隔离的沟槽的沟槽结构。即使当源电极和漏电极之间的距离减小时，通过适当地设置栅电极的沟槽的深度，可以抑制短沟道效应的发生。

2. 发明申请

US20120032236A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120032236A1
公开(公告)日：2012-02-09
申请号：US13277489
申请日：2011-10-20
申请人： Shunpei YAMAZAKI , Atsuo ISOBE , Hiromichi GODO , Yutaka OKAZAKI
发明人： Shunpei YAMAZAKI , Atsuo ISOBE , Hiromichi GODO , Yutaka OKAZAKI
IPC分类号： H01L27/092
CPC分类号： H01L27/1266 , H01L21/823807 , H01L21/823871 , H01L23/433 , H01L23/481 , H01L23/552 , H01L27/0688 , H01L27/1214 , H01L27/1229 , H01L29/7843 , H01L2224/16 , H01L2224/73253 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/12044 , H01L2924/16152 , H01L2924/16195
摘要： An object is to realize high performance and low power consumption in a semiconductor device having an SOI structure. In addition, another object is to provide a semiconductor device having a high performance semiconductor element which is more highly integrated. A semiconductor device is such that a plurality of n-channel field-effect transistors and p-channel field-effect transistors are stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. By controlling a distortion caused to a semiconductor layer due to an insulating film having a stress, a plane orientation of the semiconductor layer, and a crystal axis in a channel length direction, difference in mobility between the n-channel field-effect transistor and the p-channel field-effect transistor can be reduced, whereby current driving capabilities and response speeds of the n-channel field-effect transistor and the p-channel field-effect can be comparable.
摘要翻译：目的是在具有SOI结构的半导体器件中实现高性能和低功耗。此外，另一个目的是提供一种具有更高集成度的高性能半导体元件的半导体器件。半导体器件使得多个n沟道场效应晶体管和p沟道场效应晶体管层叠在其间具有绝缘表面的衬底之间的层间绝缘层。通过控制由于具有应力的绝缘膜，半导体层的平面取向和沟道长度方向的晶轴引起的半导体层的失真，n沟道场效应晶体管和可以减小p沟道场效应晶体管，由此n沟道场效应晶体管的电流驱动能力和响应速度与p沟道场效应相当。

3. 发明申请

US20110180796A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110180796A1
公开(公告)日：2011-07-28
申请号：US13008285
申请日：2011-01-18
申请人： Shunpei YAMAZAKI , Hiromichi GODO , Hideomi SUZAWA , Shinya SASAGAWA , Motomu KURATA , Mayumi MIKAMI
发明人： Shunpei YAMAZAKI , Hiromichi GODO , Hideomi SUZAWA , Shinya SASAGAWA , Motomu KURATA , Mayumi MIKAMI
IPC分类号： H01L29/24
CPC分类号： H01L29/7869
摘要： An object is to provide a semiconductor device including an oxide semiconductor, which maintains favorable characteristics and achieves miniaturization. The semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode in contact with the oxide semiconductor layer, a gate electrode overlapping with the oxide semiconductor layer, and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode, in which the source electrode and the drain electrode each include a first conductive layer, and a second conductive layer having a region which extends in a channel length direction from an end portion of the first conductive layer.
摘要翻译：本发明的目的是提供一种包含氧化物半导体的半导体器件，其保持有利的特性并实现小型化。半导体器件包括与氧化物半导体层接触的氧化物半导体层，源极和漏电极，与氧化物半导体层重叠的栅电极，以及设置在氧化物半导体层和栅电极之间的栅极绝缘层，其中源电极和漏极各自包括第一导电层，以及具有从第一导电层的端部在沟道长度方向上延伸的区域的第二导电层。

4. 发明申请

US20110133178A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110133178A1
公开(公告)日：2011-06-09
申请号：US12957434
申请日：2010-12-01
申请人： Shunpei YAMAZAKI , Daisuke KAWAE , Hiromichi GODO
发明人： Shunpei YAMAZAKI , Daisuke KAWAE , Hiromichi GODO
IPC分类号： H01L27/092 , H01L29/12
CPC分类号： H01L29/45 , H01L27/1225 , H01L29/7869
摘要： One object is to provide a p-channel transistor including an oxide semiconductor. Another object is to provide a complementary metal oxide semiconductor (CMOS) structure of an n-channel transistor including an oxide semiconductor and a p-channel transistor including an oxide semiconductor. A p-channel transistor including an oxide semiconductor includes a gate electrode layer, a gate insulating layer, an oxide semiconductor layer, and a source and drain electrode layers in contact with the oxide semiconductor layer. When the electron affinity and the band gap of an oxide semiconductor used for the oxide semiconductor layer in the semiconductor device, respectively, are χ (eV) and Eg (eV), the work function (φm) of the conductor used for the source electrode layer and the drain electrode layer satisfies φm>χ+Eg/2 and the barrier for holes (φBp) represented by (χ+Eg−φm) is less than 0.25 eV.
摘要翻译：一个目的是提供一种包括氧化物半导体的p沟道晶体管。另一个目的是提供包括氧化物半导体的n沟道晶体管和包括氧化物半导体的p沟道晶体管的互补金属氧化物半导体（CMOS）结构。包括氧化物半导体的p沟道晶体管包括与氧化物半导体层接触的栅极电极层，栅极绝缘层，氧化物半导体层以及源极和漏极电极层。当半导体器件中用于氧化物半导体层的氧化物半导体的电子亲和力和带隙分别为χ（eV）和Eg（eV）时，用于该半导体器件的导体的功函数（＆phgr; m）源电极层和漏电极层满足＆lt; m +χ+ Eg / 2，并且由（χ+ Eg-＆phgr; m）表示的空穴屏障（＆phgr; Bp）小于0.25eV。

5. 发明申请

US20100148175A1 THIN FILM TRANSISTOR AND DISPLAY DEVICE 有权
标题翻译：薄膜晶体管和显示器件
公开(公告)号：US20100148175A1
公开(公告)日：2010-06-17
申请号：US12633067
申请日：2009-12-08
申请人： Hiromichi GODO , Satoshi KOBAYASHI , Hidekazu MIYAIRI , Toshiyuki ISA , Shunpei YAMAZAKI
发明人： Hiromichi GODO , Satoshi KOBAYASHI , Hidekazu MIYAIRI , Toshiyuki ISA , Shunpei YAMAZAKI
IPC分类号： H01L29/786
CPC分类号： H01L29/78696 , H01L27/12 , H01L29/04
摘要： Off current of a bottom gate thin film transistor in which a semiconductor layer is shielded from light by a gate electrode is reduced. A thin film transistor includes a gate electrode layer; a first semiconductor layer; a second semiconductor layer, provided on and in contact with the first semiconductor layer; a gate insulating layer between and in contact with the gate electrode layer and the first semiconductor layer; impurity semiconductor layers in contact with the second semiconductor layer; and source and drain electrode layers partially in contact with the impurity semiconductor layers and the first and second semiconductor layers. The entire surface of the first semiconductor layer on the gate electrode layer side is covered by the gate electrode layer; and a potential barrier at a portion where the first semiconductor layer is in contact with the source or drain electrode layer is 0.5 eV or more.
摘要翻译：其中半导体层被栅极电极遮挡光的底栅薄膜晶体管的截止电流减小。薄膜晶体管包括栅电极层; 第一半导体层; 第二半导体层，设置在第一半导体层上并与第一半导体层接触; 在栅极电极层和第一半导体层之间并与之接触的栅极绝缘层; 与第二半导体层接触的杂质半导体层; 以及与杂质半导体层和第一和第二半导体层部分接触的源极和漏极电极层。栅极电极层侧的第一半导体层的整个表面被栅电极层覆盖; 并且在第一半导体层与源极或漏极电极层接触的部分处的势垒为0.5eV以上。

6. 发明申请

US20120214276A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20120214276A1
公开(公告)日：2012-08-23
申请号：US13455425
申请日：2012-04-25
申请人： Yoshiaki OIKAWA , Hotaka MARUYAMA , Hiromichi GODO , Daisuke KAWAE , Shunpei YAMAZAKI
发明人： Yoshiaki OIKAWA , Hotaka MARUYAMA , Hiromichi GODO , Daisuke KAWAE , Shunpei YAMAZAKI
IPC分类号： H01L21/363
CPC分类号： H01L27/1225 , G02F1/1368 , G02F2201/121 , G02F2201/123 , H01L21/02565 , H01L21/02631 , H01L27/1214 , H01L27/124 , H01L27/156 , H01L27/3248 , H01L27/3262 , H01L29/24 , H01L29/78618 , H01L29/7869 , H01L29/78693 , H01L29/78696
摘要： An object is to provide a semiconductor device provided with a thin film transistor having excellent electric characteristics using an oxide semiconductor layer. An In—Sn—O-based oxide semiconductor layer including SiOX is used for a channel formation region. In order to reduce contact resistance between the In—Sn—O-based oxide semiconductor layer including SiOX and a wiring layer formed from a metal material having low electric resistance, a source region or drain region is formed between a source electrode layer or drain electrode layer and the In—Sn—O-based oxide semiconductor layer including SiOX. The source region or drain region and a pixel region are formed using an In—Sn—O-based oxide semiconductor layer which does not include SiOX.
摘要翻译：本发明的目的是提供一种具有使用氧化物半导体层的具有优异电特性的薄膜晶体管的半导体器件。包括SiOX的In-Sn-O系氧化物半导体层用于沟道形成区域。为了降低包含SiOX的In-Sn-O系氧化物半导体层与由电阻低的金属材料形成的布线层之间的接触电阻，在源电极层或漏电极之间形成源极区或漏极区层和包含SiOX的In-Sn-O系氧化物半导体层。使用不包含SiOX的In-Sn-O系氧化物半导体层来形成源极区域或漏极区域以及像素区域。

7. 发明申请

US20100237418A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100237418A1
公开(公告)日：2010-09-23
申请号：US12793237
申请日：2010-06-03
申请人： Shunpei YAMAZAKI , Atsuo ISOBE , Tetsuji YAMAGUCHI , Hiromichi GODO
发明人： Shunpei YAMAZAKI , Atsuo ISOBE , Tetsuji YAMAGUCHI , Hiromichi GODO
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L27/127 , H01L27/1214 , H01L27/1285 , H01L27/1288 , H01L27/13 , H01L29/458 , H01L29/4908 , H01L29/78621 , H01L29/78624
摘要： It is an object of the present invention to manufacture a thin film transistor having a required property without complicating steps and devices. It is another object of the present invention to provide a technique for manufacturing a semiconductor device having high reliability and better electrical characteristics with a higher yield at lower cost. In the present invention, a lightly doped impurity region is formed in a source region side or a drain region side of a semiconductor layer covered with a gate electrode layer in a thin film transistor. The semiconductor layer is doped diagonally to the surface thereof using the gate electrode layer as a mask to form the lightly doped impurity region. Therefore, the properties of the thin film transistor can be minutely controlled.
摘要翻译：本发明的目的是制造具有所需性能的薄膜晶体管，而不会使步骤和装置复杂化。本发明的另一个目的是提供一种以更低的成本制造具有高可靠性和更好的电气特性并以较高产量获得的半导体器件的技术。在本发明中，在薄膜晶体管中由栅极电极层覆盖的半导体层的源区域侧或漏极区侧形成有轻掺杂杂质区。使用栅极电极层作为掩模将半导体层以其对面的方式对角地掺杂以形成轻掺杂杂质区域。因此，可以精细地控制薄膜晶体管的性质。

8. 发明申请

US20100219410A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100219410A1
公开(公告)日：2010-09-02
申请号：US12706737
申请日：2010-02-17
申请人： Hiromichi GODO , Kengo AKIMOTO , Shunpei YAMAZAKI
发明人： Hiromichi GODO , Kengo AKIMOTO , Shunpei YAMAZAKI
IPC分类号： H01L29/786 , H01L29/22 , H01L21/44 , H01L21/34
CPC分类号： H01L29/78693 , H01L21/02554 , H01L21/02565 , H01L21/02573 , H01L21/02631 , H01L29/24 , H01L29/66742 , H01L29/78606 , H01L29/7869 , H01L29/78696
摘要： An object is to reduce to reduce variation in threshold voltage to stabilize electric characteristics of thin film transistors each using an oxide semiconductor layer. An object is to reduce an off current. The thin film transistor using an oxide semiconductor layer is formed by stacking an oxide semiconductor layer containing insulating oxide over the oxide semiconductor layer so that the oxide semiconductor layer and source and drain electrode layers are in contact with each other with the oxide semiconductor layer containing insulating oxide interposed therebetween; whereby, variation in threshold voltage of the thin film transistors can be reduced and thus the electric characteristics can be stabilized. Further, an off current can be reduced.
摘要翻译：目的是为了减小阈值电压的变化，以稳定每个使用氧化物半导体层的薄膜晶体管的电特性。目的是减少关断电流。使用氧化物半导体层的薄膜晶体管通过在氧化物半导体层上层叠含有绝缘氧化物的氧化物半导体层而形成，使得氧化物半导体层和源极和漏极电极层彼此接触，氧化物半导体层包含绝缘体介于其间的氧化物; 从而可以减小薄膜晶体管的阈值电压的变化，从而能够稳定电特性。此外，可以减少截止电流。

9. 发明申请

US20090218576A1 THIN-FILM TRANSISTOR AND DISPLAY DEVICE 有权
标题翻译：薄膜晶体管和显示器件
公开(公告)号：US20090218576A1
公开(公告)日：2009-09-03
申请号：US12390144
申请日：2009-02-20
申请人： Koji DAIRIKI , Hidekazu MIYAIRI , Yoshiyuki KUROKAWA , Shunpei YAMAZAKI , Hiromichi GODO , Daisuke KAWAE , Satoshi KOBAYASHI
发明人： Koji DAIRIKI , Hidekazu MIYAIRI , Yoshiyuki KUROKAWA , Shunpei YAMAZAKI , Hiromichi GODO , Daisuke KAWAE , Satoshi KOBAYASHI
IPC分类号： H01L33/00 , H01L29/786
CPC分类号： H01L27/1214 , H01L27/1288 , H01L29/04 , H01L29/458 , H01L29/4908 , H01L29/66765
摘要： A thin-film transistor includes a pair of impurity semiconductor layers in which an impurity element imparting one conductivity type is added to form a source and drain regions so as to be overlapped at least partly with a gate electrode with a gate insulating layer interposed between the gate electrode and the impurity semiconductor layers; a pair of conductive layers which is overlapped over the gate insulating layers at least partly with the gate electrode and the impurity semiconductor layers, and is disposed with a space therebetween in a channel length direction; and an amorphous semiconductor layer which is in contact with the gate insulating layer and the pair of conductive layers and is extended between the pair of conductive layers.
摘要翻译：薄膜晶体管包括一对杂质半导体层，其中添加赋予一种导电类型的杂质元素以形成源极区和漏极区，以至少部分地与栅电极重叠，栅极绝缘层介于栅电极和杂质半导体层; 一对导电层，其至少部分地与所述栅极电极和所述杂质半导体层重叠在所述栅极绝缘层上方，并且在沟道长度方向上间隔开; 以及与所述栅极绝缘层和所述一对导电层接触并在所述一对导电层之间延伸的非晶半导体层。

10. 发明申请

US20090079000A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090079000A1
公开(公告)日：2009-03-26
申请号：US12209739
申请日：2008-09-12
申请人： Shunpei YAMAZAKI , Atsuo ISOBE , Hiromichi GODO , Yutaka OKAZAKI
发明人： Shunpei YAMAZAKI , Atsuo ISOBE , Hiromichi GODO , Yutaka OKAZAKI
IPC分类号： H01L27/08
CPC分类号： H01L27/1266 , H01L21/823807 , H01L21/823871 , H01L23/433 , H01L23/481 , H01L23/552 , H01L27/0688 , H01L27/1214 , H01L27/1229 , H01L29/7843 , H01L2224/16 , H01L2224/73253 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/12044 , H01L2924/16152 , H01L2924/16195
摘要： An object is to realize high performance and low power consumption in a semiconductor device having an SOI structure. In addition, another object is to provide a semiconductor device having a high performance semiconductor element which is more highly integrated. A semiconductor device is such that a plurality of n-channel field-effect transistors and p-channel field-effect transistors are stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. By controlling a distortion caused to a semiconductor layer due to an insulating film having a stress, a plane orientation of the semiconductor layer, and a crystal axis in a channel length direction, difference in mobility between the n-channel field-effect transistor and the p-channel field-effect transistor can be reduced, whereby current driving capabilities and response speeds of the n-channel field-effect transistor and the p-channel field-effect can be comparable.
摘要翻译：目的是在具有SOI结构的半导体器件中实现高性能和低功耗。此外，另一个目的是提供一种具有更高集成度的高性能半导体元件的半导体器件。半导体器件使得多个n沟道场效应晶体管和p沟道场效应晶体管层叠在其间具有绝缘表面的衬底之间的层间绝缘层。通过控制由于具有应力的绝缘膜，半导体层的平面取向和沟道长度方向的晶轴引起的半导体层的失真，n沟道场效应晶体管和可以减小p沟道场效应晶体管，由此n沟道场效应晶体管的电流驱动能力和响应速度与p沟道场效应相当。

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