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    • 3. 发明授权
    • Particle characterization cell and particle characterization instrument
    • 颗粒表征细胞和颗粒表征仪
    • US09034164B2
    • 2015-05-19
    • US13220813
    • 2011-08-30
    • Tetsuji YamaguchiMakoto Nagura
    • Tetsuji YamaguchiMakoto Nagura
    • G01N1/10G01N21/51
    • G01N21/51G01N2021/513
    • The present invention is configured to be provided with: a bottom-equipped tubular cell main body that forms an internal space S1 that extends in a longer direction, and has one end part that is opened; a pair of applying electrodes that are arranged so as to face to each other in the internal space; and a fixing spacer that intervenes between the pair of applying electrodes to thereby define a distance between the applying electrodes, and fixes the pair of applying electrodes, wherein in a state where the fixing spacer is inserted into the cell main body, in a lower part of the internal space of the cell main body, a zeta potential measuring space in which the pair of applying electrodes are exposed is formed.
    • 本发明的目的是提供一种底部装配的管状电池主体,其形成一个沿较长方向延伸的内部空间S1,并且具有一个端部被打开; 一对施加电极,其布置成在所述内部空间中彼此面对; 以及固定间隔物,其插入在所述一对施加电极之间,由此限定所述施加电极之间的距离,并且将所述一对施加电极固定在所述固定间隔件插入所述电池主体的状态下, 形成电池主体的内部空间,形成有一对施加电极露出的ζ电位测量空间。
    • 4. 发明授权
    • Solid-state imaging device, method of manufacturing the same, and electronic apparatus
    • 固态成像装置及其制造方法以及电子装置
    • US08450728B2
    • 2013-05-28
    • US12974295
    • 2010-12-21
    • Tetsuji Yamaguchi
    • Tetsuji Yamaguchi
    • H01L31/113
    • H01L27/14603H01L27/1464H01L27/14643
    • A solid-state imaging device including a semiconductor substrate, a photoelectric conversion portion interposed between a lower electrode and an upper electrode, a contact plug formed so as to connect the lower electrode and the semiconductor substrate in order to read signal charges generated in the photoelectric conversion portion to the semiconductor substrate side, a vertical type transmitting path configured by sequentially laminating a connection portion for electrically connecting the contact plug to the semiconductor substrate, a charge accumulation layer for accumulating the signal charges read to the connection portion, and a potential barrier layer configuring a potential barrier between the connection portion and the charge accumulation layer in a vertical direction of the semiconductor substrate, and a charge reading portion configured to read the signal charges accumulated in the charge accumulation layer to the circuit forming surface side of the semiconductor substrate.
    • 一种固态成像装置,包括半导体衬底,介于下电极和上电极之间的光电转换部分,形成为连接下电极和半导体衬底的接触插塞,以便读取在光电 转换部分到半导体衬底侧,垂直型传输路径,其通过顺序地层叠用于将接触插塞电连接到半导体衬底的连接部分,用于累积读取到连接部分的信号电荷的电荷累积层,以及势垒 层构成在半导体衬底的垂直方向上的连接部分和电荷累积层之间的势垒;以及电荷读取部分,被配置为将累积在电荷累积层中的信号电荷读取到半导体衬底的电路形成表面侧 。
    • 7. 发明授权
    • Thin film transistor including insulating film and island-shaped semiconductor film
    • 薄膜晶体管包括绝缘膜和岛状半导体膜
    • US08120111B2
    • 2012-02-21
    • US12078738
    • 2008-04-04
    • Tetsuji YamaguchiKengo AkimotoHiroki KayoijiToru Takayama
    • Tetsuji YamaguchiKengo AkimotoHiroki KayoijiToru Takayama
    • H01L27/13
    • H01L27/12H01L27/1248
    • An object of the present invention is to provide a method for manufacturing a thin film transistor which enables heat treatment aimed at improving characteristics of a gate insulating film such as lowering of an interface level or reduction in a fixed charge without causing a problem of misalignment in patterning due to expansion or shrinkage of glass. A method for manufacturing a thin film transistor of the present invention comprises the steps of heat-treating in a state where at least a gate insulating film is formed over a semiconductor film on which element isolation is not performed, simultaneously isolating the gate insulating film and the semiconductor film into an element structure, forming an insulating film covering a side face of an exposed semiconductor film, thereby preventing a short-circuit between the semiconductor film and a gate electrode. Expansion or shrinkage of a glass substrate during the heat treatment can be prevented from affecting misalignment in patterning since the gate insulating film and the semiconductor film are simultaneously processed into element shapes after the heat treatment.
    • 本发明的目的是提供一种薄膜晶体管的制造方法,其能够进行旨在提高栅极绝缘膜的特性的热处理,例如降低界面电平或降低固定电荷,而不会引起不对准的问题 由于玻璃的膨胀或收缩造成图案化。 本发明的薄膜晶体管的制造方法包括以下步骤:在不进行元件隔离的半导体膜上形成至少栅极绝缘膜的状态下进行热处理,同时隔离栅极绝缘膜和 将半导体膜形成为元件结构,形成覆盖露出的半导体膜的侧面的绝缘膜,由此防止半导体膜与栅电极之间的短路。 由于栅极绝缘膜和半导体膜在热处理后同时被加工成元件形状,所以可以防止热处理期间的玻璃基板的膨胀或收缩,从而影响图案中的未对准。
    • 8. 发明申请
    • THIN FILM TRANSISTOR, ELECTRONIC DEVICE HAVING THE SAME, AND METHOD FOR MANUFACTURING THE SAME
    • 薄膜晶体管,具有该薄膜晶体管的电子器件及其制造方法
    • US20110272700A1
    • 2011-11-10
    • US13185931
    • 2011-07-19
    • Tetsuji YAMAGUCHIKengo AKIMOTOHiroki KAYOIJIToru TAKAYAMA
    • Tetsuji YAMAGUCHIKengo AKIMOTOHiroki KAYOIJIToru TAKAYAMA
    • H01L29/786
    • H01L27/12H01L27/1248
    • An object of the present invention is to provide a method for manufacturing a thin film transistor which enables heat treatment aimed at improving characteristics of a gate insulating film such as lowering of an interface level or reduction in a fixed charge without causing a problem of misalignment in patterning due to expansion or shrinkage of glass. A method for manufacturing a thin film transistor of the present invention comprises the steps of heat-treating in a state where at least a gate insulating film is formed over a semiconductor film on which element isolation is not performed, simultaneously isolating the gate insulating film and the semiconductor film into an element structure, forming an insulating film covering a side face of an exposed semiconductor film, thereby preventing a short-circuit between the semiconductor film and a gate electrode. Expansion or shrinkage of a glass substrate during the heat treatment can be prevented from affecting misalignment in patterning since the gate insulating film and the semiconductor film are simultaneously processed into element shapes after the heat treatment.
    • 本发明的目的是提供一种薄膜晶体管的制造方法,其能够进行旨在提高栅极绝缘膜的特性的热处理,例如降低界面电平或降低固定电荷,而不会引起不对准的问题 由于玻璃的膨胀或收缩造成图案化。 本发明的薄膜晶体管的制造方法包括以下步骤:在不进行元件隔离的半导体膜上形成至少栅极绝缘膜的状态下进行热处理,同时隔离栅极绝缘膜和 将半导体膜形成为元件结构,形成覆盖露出的半导体膜的侧面的绝缘膜,由此防止半导体膜与栅电极之间的短路。 由于栅极绝缘膜和半导体膜在热处理后同时被加工成元件形状,所以可以防止热处理期间的玻璃基板的膨胀或收缩,从而影响图案中的未对准。
    • 10. 发明授权
    • Correlator
    • 相关者
    • US07724369B2
    • 2010-05-25
    • US12245902
    • 2008-10-06
    • Tetsuji YamaguchiShigeyuki Kawarabayashi
    • Tetsuji YamaguchiShigeyuki Kawarabayashi
    • G01N15/02
    • G01N15/0205
    • In order to improve an accuracy of an autocorrelation function, a correlator comprises a counter 61 for receiving a pulse signal at given time intervals (sampling times) and counting the number of pulses; a shift register 63 for receiving the number of pulses counted by the counter 61 and performing sequential time delay; an operation part 64 for performing a product-sum operation of an output from the counter 61 and that delayed by the shift register 63 for each channel; and a control part 65 for setting a delay time or a sampling time by the shift register 63 on a basis of a relationship of the Fibonacci sequence.
    • 为了提高自相关函数的精度,相关器包括用于以给定时间间隔(采样时间)接收脉冲信号并计数脉冲数的计数器61; 移位寄存器63,用于接收由计数器61计数的脉冲数,并执行连续时间延迟; 操作部分64,用于对每个通道执行来自计数器61的输出和由移位寄存器63延迟的乘积和运算; 以及控制部分65,用于根据斐波纳契序列的关系设置移位寄存器63的延迟时间或采样时间。