专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090078970A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090078970A1
公开(公告)日：2009-03-26
申请号：US12209696
申请日：2008-09-12
申请人： Shunpei YAMAZAKI , Atsuo ISOBE , Hiromichi GODO , Yutaka OKAZAKI
发明人： Shunpei YAMAZAKI , Atsuo ISOBE , Hiromichi GODO , Yutaka OKAZAKI
IPC分类号： H01L27/12
CPC分类号： H01L21/8221 , H01L27/0688 , H01L2224/16225 , H01L2224/16227 , H01L2224/32245 , H01L2924/00011 , H01L2924/00014 , H01L2224/29099 , H01L2224/13099 , H01L2224/80001
摘要： A semiconductor device is demonstrated in which a plurality of field-effect transistors is stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. Each of the plurality of filed-effect transistors has a semiconductor layer which is prepared by a process including separation of the semiconductor layer from a semiconductor substrate followed by bonding thereof over the substrate. Each of the plurality of field-effect transistors is covered with an insulating film which provides distortion of the semiconductor layer. Furthermore, the crystal axis of the semiconductor layer, which is parallel to the crystal plane thereof, is set to a channel length direction of the semiconductor layer, which enables production of the semiconductor device with high performance and low power consumption having an SOI structure.
摘要翻译：示出了一种半导体器件，其中在具有绝缘表面的衬底上层叠多个场效应晶体管，层间绝缘层介于其间。多个场效应晶体管中的每一个具有半导体层，该半导体层通过包括将半导体层与半导体衬底分离并随后在衬底上结合的工艺制备。多个场效应晶体管中的每一个被覆盖有提供半导体层失真的绝缘膜。此外，将半导体层的与其晶面平行的晶轴设定为半导体层的沟道长度方向，能够制造具有SOI结构的高性能，低功耗的半导体器件。

2. 发明申请

US20120032236A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120032236A1
公开(公告)日：2012-02-09
申请号：US13277489
申请日：2011-10-20
申请人： Shunpei YAMAZAKI , Atsuo ISOBE , Hiromichi GODO , Yutaka OKAZAKI
发明人： Shunpei YAMAZAKI , Atsuo ISOBE , Hiromichi GODO , Yutaka OKAZAKI
IPC分类号： H01L27/092
CPC分类号： H01L27/1266 , H01L21/823807 , H01L21/823871 , H01L23/433 , H01L23/481 , H01L23/552 , H01L27/0688 , H01L27/1214 , H01L27/1229 , H01L29/7843 , H01L2224/16 , H01L2224/73253 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/12044 , H01L2924/16152 , H01L2924/16195
摘要： An object is to realize high performance and low power consumption in a semiconductor device having an SOI structure. In addition, another object is to provide a semiconductor device having a high performance semiconductor element which is more highly integrated. A semiconductor device is such that a plurality of n-channel field-effect transistors and p-channel field-effect transistors are stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. By controlling a distortion caused to a semiconductor layer due to an insulating film having a stress, a plane orientation of the semiconductor layer, and a crystal axis in a channel length direction, difference in mobility between the n-channel field-effect transistor and the p-channel field-effect transistor can be reduced, whereby current driving capabilities and response speeds of the n-channel field-effect transistor and the p-channel field-effect can be comparable.
摘要翻译：目的是在具有SOI结构的半导体器件中实现高性能和低功耗。此外，另一个目的是提供一种具有更高集成度的高性能半导体元件的半导体器件。半导体器件使得多个n沟道场效应晶体管和p沟道场效应晶体管层叠在其间具有绝缘表面的衬底之间的层间绝缘层。通过控制由于具有应力的绝缘膜，半导体层的平面取向和沟道长度方向的晶轴引起的半导体层的失真，n沟道场效应晶体管和可以减小p沟道场效应晶体管，由此n沟道场效应晶体管的电流驱动能力和响应速度与p沟道场效应相当。

3. 发明申请

US20090079000A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090079000A1
公开(公告)日：2009-03-26
申请号：US12209739
申请日：2008-09-12
申请人： Shunpei YAMAZAKI , Atsuo ISOBE , Hiromichi GODO , Yutaka OKAZAKI
发明人： Shunpei YAMAZAKI , Atsuo ISOBE , Hiromichi GODO , Yutaka OKAZAKI
IPC分类号： H01L27/08
CPC分类号： H01L27/1266 , H01L21/823807 , H01L21/823871 , H01L23/433 , H01L23/481 , H01L23/552 , H01L27/0688 , H01L27/1214 , H01L27/1229 , H01L29/7843 , H01L2224/16 , H01L2224/73253 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/12044 , H01L2924/16152 , H01L2924/16195
摘要： An object is to realize high performance and low power consumption in a semiconductor device having an SOI structure. In addition, another object is to provide a semiconductor device having a high performance semiconductor element which is more highly integrated. A semiconductor device is such that a plurality of n-channel field-effect transistors and p-channel field-effect transistors are stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. By controlling a distortion caused to a semiconductor layer due to an insulating film having a stress, a plane orientation of the semiconductor layer, and a crystal axis in a channel length direction, difference in mobility between the n-channel field-effect transistor and the p-channel field-effect transistor can be reduced, whereby current driving capabilities and response speeds of the n-channel field-effect transistor and the p-channel field-effect can be comparable.
摘要翻译：目的是在具有SOI结构的半导体器件中实现高性能和低功耗。此外，另一个目的是提供一种具有更高集成度的高性能半导体元件的半导体器件。半导体器件使得多个n沟道场效应晶体管和p沟道场效应晶体管层叠在其间具有绝缘表面的衬底之间的层间绝缘层。通过控制由于具有应力的绝缘膜，半导体层的平面取向和沟道长度方向的晶轴引起的半导体层的失真，n沟道场效应晶体管和可以减小p沟道场效应晶体管，由此n沟道场效应晶体管的电流驱动能力和响应速度与p沟道场效应相当。

4. 发明申请

US20080179675A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080179675A1
公开(公告)日：2008-07-31
申请号：US12015362
申请日：2008-01-16
申请人： Shunpei YAMAZAKI , Atsuo ISOBE , Hiromichi GODO
发明人： Shunpei YAMAZAKI , Atsuo ISOBE , Hiromichi GODO
IPC分类号： H01L27/12 , H01L21/782
CPC分类号： H01L29/78621 , H01L29/42384 , H01L29/4908 , H01L29/66757 , H01L29/78618 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a novel structure by which the operating characteristics and reliability are improved and a manufacturing method thereof. An island-shaped semiconductor layer provided over a substrate, including a channel formation region provided between a pair of impurity regions; a first insulating layer provided so as to be in contact with the side surface of the semiconductor layer; a gate electrode provided over the channel formation region so as to get across the semiconductor layer; and a second insulating layer provided between the channel formation region and the gate electrode are included. The semiconductor layer is locally thinned, the channel formation region is provided in the thinned region, and the second insulating layer covers the first insulating layer provided on the side surface of the semiconductor layer at least in the region which overlaps with the gate electrode.
摘要翻译：具有改善其操作特性和可靠性的新颖结构的半导体器件及其制造方法。一种岛状半导体层，设置在衬底上，包括设置在一对杂质区之间的沟道形成区; 设置成与半导体层的侧表面接触的第一绝缘层; 栅电极，设置在所述沟道形成区上方以穿过所述半导体层; 并且包括设置在沟道形成区域和栅电极之间的第二绝缘层。半导体层被局部变薄，沟道形成区域设置在减薄区域中，并且第二绝缘层至少在与栅电极重叠的区域中覆盖设置在半导体层的侧表面上的第一绝缘层。

5. 发明申请

US20100237418A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100237418A1
公开(公告)日：2010-09-23
申请号：US12793237
申请日：2010-06-03
申请人： Shunpei YAMAZAKI , Atsuo ISOBE , Tetsuji YAMAGUCHI , Hiromichi GODO
发明人： Shunpei YAMAZAKI , Atsuo ISOBE , Tetsuji YAMAGUCHI , Hiromichi GODO
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L27/127 , H01L27/1214 , H01L27/1285 , H01L27/1288 , H01L27/13 , H01L29/458 , H01L29/4908 , H01L29/78621 , H01L29/78624
摘要： It is an object of the present invention to manufacture a thin film transistor having a required property without complicating steps and devices. It is another object of the present invention to provide a technique for manufacturing a semiconductor device having high reliability and better electrical characteristics with a higher yield at lower cost. In the present invention, a lightly doped impurity region is formed in a source region side or a drain region side of a semiconductor layer covered with a gate electrode layer in a thin film transistor. The semiconductor layer is doped diagonally to the surface thereof using the gate electrode layer as a mask to form the lightly doped impurity region. Therefore, the properties of the thin film transistor can be minutely controlled.
摘要翻译：本发明的目的是制造具有所需性能的薄膜晶体管，而不会使步骤和装置复杂化。本发明的另一个目的是提供一种以更低的成本制造具有高可靠性和更好的电气特性并以较高产量获得的半导体器件的技术。在本发明中，在薄膜晶体管中由栅极电极层覆盖的半导体层的源区域侧或漏极区侧形成有轻掺杂杂质区。使用栅极电极层作为掩模将半导体层以其对面的方式对角地掺杂以形成轻掺杂杂质区域。因此，可以精细地控制薄膜晶体管的性质。

6. 发明申请

US20130075722A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20130075722A1
公开(公告)日：2013-03-28
申请号：US13613192
申请日：2012-09-13
申请人： Shunpei YAMAZAKI , Atsuo ISOBE , Yutaka OKAZAKI , Takehisa HATANO , Sachiaki TEZUKA , Suguru HONDO , Toshihiko SAITO
发明人： Shunpei YAMAZAKI , Atsuo ISOBE , Yutaka OKAZAKI , Takehisa HATANO , Sachiaki TEZUKA , Suguru HONDO , Toshihiko SAITO
IPC分类号： H01L29/786
CPC分类号： H01L29/41733 , H01L29/42384 , H01L29/78618 , H01L29/7869
摘要： A highly reliable structure for high-speed response and high-speed driving of a semiconductor device, in which on-state characteristics of a transistor are increased is provided. In the coplanar transistor, an oxide semiconductor layer, a source and drain electrode layers including a stack of a first conductive layer and a second conductive layer, a gate insulating layer, and a gate electrode layer are sequentially stacked in this order. The gate electrode layer is overlapped with the first conductive layer with the gate insulating layer provided therebetween, and is not overlapped with the second conductive layer with the gate insulating layer provided therebetween.
摘要翻译：提供了一种用于高速响应和高速驱动半导体器件的高度可靠的结构，其中晶体管的导通状态特性增加。在共面晶体管中，依次层叠氧化物半导体层，包括第一导电层和第二导电层的堆叠的源极和漏极电极层，栅极绝缘层和栅极电极层。栅极电极层与第一导电层重叠，栅极绝缘层设置在它们之间，并且与其间设置有栅极绝缘层的第二导电层不重叠。

7. 发明申请

US20120146144A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120146144A1
公开(公告)日：2012-06-14
申请号：US13402212
申请日：2012-02-22
申请人： Hideto OHNUMA , Atsuo ISOBE , Hiromichi GODO
发明人： Hideto OHNUMA , Atsuo ISOBE , Hiromichi GODO
IPC分类号： H01L29/786 , H01L21/20
CPC分类号： H01L29/78696 , H01L21/0237 , H01L21/02675 , H01L21/02691 , H01L27/1281
摘要： A semiconductor device having a highly responsive thin film transistor (TFT) with low subthreshold swing and suppressed decrease in the on-state current and a manufacturing method thereof are demonstrated. The TFT of the present invention is characterized by its semiconductor layer where the thickness of the source region or the drain region is larger than that of the channel formation region. Manufacture of the TFT is readily achieved by the formation of an amorphous semiconductor layer on a projection portion and a depression portion, which is followed by subjecting the melting process of the semiconductor layer, resulting in the formation of a crystalline semiconductor layer having different thicknesses. Selective addition of impurity to the thick portion of the semiconductor layer provides a semiconductor layer in which the channel formation region is thinner than the source or drain region.
摘要翻译：示出了具有低亚阈值摆动和抑制导通电流下降的高响应性薄膜晶体管（TFT）的半导体器件及其制造方法。本发明的TFT的特征在于其源极区域或漏极区域的厚度大于沟道形成区域的厚度的半导体层。通过在突起部分和凹陷部分上形成非晶半导体层来容易地实现TFT的制造，随后对半导体层进行熔化处理，形成具有不同厚度的晶体半导体层。选择性地向半导体层的厚部分添加杂质提供了沟道形成区域比源区或漏区更薄的半导体层。

8. 发明申请

US20130075721A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130075721A1
公开(公告)日：2013-03-28
申请号：US13613178
申请日：2012-09-13
申请人： Shunpei YAMAZAKI , Atsuo ISOBE , Toshinari SASAKI
发明人： Shunpei YAMAZAKI , Atsuo ISOBE , Toshinari SASAKI
IPC分类号： H01L29/12
CPC分类号： H01L29/7869 , H01L27/12 , H01L27/1225 , H01L29/10 , H01L29/41733 , H01L29/41775
摘要： Provided is a semiconductor device including a transistor with large on-state current even when it is miniaturized. The transistor includes a pair of first conductive films over an insulating surface; a semiconductor film over the pair of first conductive films; a pair of second conductive films, with one of the pair of second conductive films and the other of the pair of second conductive films being connected to one of the pair of first conductive films and the other of the pair of first conductive films, respectively; an insulating film over the semiconductor film; and a third conductive film provided in a position overlapping with the semiconductor film over the insulating film. Further, over the semiconductor film, the third conductive film is interposed between the pair of second conductive films and away from the pair of second conductive films.
摘要翻译：提供了即使在小型化时也具有大导通状态的晶体管的半导体装置。晶体管包括在绝缘表面上的一对第一导电膜; 在一对第一导电膜上的半导体膜; 一对第二导电膜，其中一对第二导电膜中的一个和一对第二导电膜中的另一个分别连接到一对第一导电膜中的一个和一对第一导电膜中的另一个; 半导体膜上的绝缘膜; 以及设置在与绝缘膜上的半导体膜重叠的位置的第三导电膜。此外，在半导体膜之上，第三导电膜插入在一对第二导电膜之间并远离一对第二导电膜。

9. 发明申请

US20130069053A1 SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20130069053A1
公开(公告)日：2013-03-21
申请号：US13608039
申请日：2012-09-10
申请人： Shunpei YAMAZAKI , Atsuo ISOBE , Toshinari SASAKI
发明人： Shunpei YAMAZAKI , Atsuo ISOBE , Toshinari SASAKI
IPC分类号： H01L29/786
CPC分类号： H01L29/7869 , H01L27/1218 , H01L27/1225
摘要： To provide a transistor which includes an oxide semiconductor and is capable of operating at high speed or a highly reliable semiconductor device including the transistor, a transistor in which an oxide semiconductor layer including a pair of low-resistance regions and a channel formation region is provided over an electrode layer, which is embedded in a base insulating layer and whose upper surface is at least partly exposed from the base insulating layer, and a wiring layer provided above the oxide semiconductor layer is electrically connected to the electrode layer or a part of a low-resistance region of the oxide semiconductor layer, which overlaps with the electrode layer.

10. 发明申请

US20120286270A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120286270A1
公开(公告)日：2012-11-15
申请号：US13463092
申请日：2012-05-03
申请人： Atsuo ISOBE , Toshinari SASAKI , Junichi KOEZUKA , Shunpei YAMAZAKI
发明人： Atsuo ISOBE , Toshinari SASAKI , Junichi KOEZUKA , Shunpei YAMAZAKI
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/4238 , H01L21/02565 , H01L21/265 , H01L21/425 , H01L21/84 , H01L27/1085 , H01L27/10876 , H01L27/1156 , H01L27/1203 , H01L27/1225 , H01L28/40 , H01L29/045 , H01L29/0847 , H01L29/66477 , H01L29/66742 , H01L29/66969 , H01L29/78603 , H01L29/7869 , H01L29/78693
摘要： It is an object to provide a semiconductor device in which a short-channel effect is suppressed and miniaturization is achieved, and a manufacturing method thereof. A trench is formed in an insulating layer and impurities are added to an oxide semiconductor film in contact with an upper end corner portion of the trench, whereby a source region and a drain region are formed. With the above structure, miniaturization can be achieved. Further, with the trench, a short-channel effect can be suppressed setting the depth of the trench as appropriate even when a distance between a source electrode layer and a drain electrode layer is shortened.
摘要翻译：本发明的目的是提供一种抑制短路效应并实现小型化的半导体器件及其制造方法。在绝缘层中形成沟槽，并且将杂质添加到与沟槽的上端角部接触的氧化物半导体膜，由此形成源极区域和漏极区域。利用上述结构，可以实现小型化。此外，利用沟槽，即使当源电极层和漏电极层之间的距离缩短时，也可以适当地抑制沟槽的深度适当地设定短沟道效应。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式