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1. 发明授权

US06638874B2 Methods used in fabricating gates in integrated circuit device structures 失效
标题翻译：在集成电路器件结构中用于制造栅极的方法
公开(公告)号：US06638874B2
公开(公告)日：2003-10-28
申请号：US10198298
申请日：2002-07-17
申请人： Sang In Yi , Seowoo Nam , Kenlin Huang , Padmapani C. Nallan
发明人： Sang In Yi , Seowoo Nam , Kenlin Huang , Padmapani C. Nallan
IPC分类号： H01L21302
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/32136
摘要： One embodiment of the present invention is a method used to fabricate a device on a substrate, which method is utilized at a stage of processing wherein a metal gate stack is disposed or formed over a gate oxide, which metal stack includes a refractory metal layer disposed or formed over a refractory metal barrier/adhesion layer, which method includes steps of: (a) etching the refractory metal layer and stopping on or in the refractory metal barrier/adhesion layer; and (b) etching the refractory metal barrier/adhesion layer using a passivation etching chemistry without oxygen.
摘要翻译：本发明的一个实施方案是用于在衬底上制造器件的方法，该方法在处理阶段被利用，其中在栅极氧化物上设置或形成金属栅极堆叠，该金属堆叠包括设置的难熔金属层或形成在难熔金属阻挡层/粘合层上，该方法包括以下步骤：（a）蚀刻难熔金属层并停留在难熔金属屏障/粘合层上或其中; 和（b）使用无氧的钝化蚀刻化学蚀刻难熔金属阻挡层/粘附层。

2. 发明授权

US06893893B2 Method of preventing short circuits in magnetic film stacks 失效
标题翻译：防止磁性薄膜堆叠短路的方法
公开(公告)号：US06893893B2
公开(公告)日：2005-05-17
申请号：US10235100
申请日：2002-09-04
申请人： Padmapani C. Nallan , Ajay Kumar , Jeng H. Hwang , Guangxiang Jin , Ralph Kerns
发明人： Padmapani C. Nallan , Ajay Kumar , Jeng H. Hwang , Guangxiang Jin , Ralph Kerns
IPC分类号： H01L21/00 , H01L23/00 , H01L43/12
CPC分类号： H01L23/564 , H01L21/67069 , H01L43/12 , H01L2924/0002 , H01L2924/00
摘要： A method for preventing electrical short circuits in a multi-layer magnetic film stack comprises providing a film stack that includes a layer of magnetic material having an exposed surface. A protective layer is deposited on the exposed surface of the magnetic layer. The protective layer may comprise, for example, a fluorocarbon or a hydrofluorocarbon. The film stack is etched and the protective layer protects the exposed surface from a conductive residue produced while etching the film stack. The method may be used in film stacks to form a magneto-resistive random access memory (MRAM) device.
摘要翻译：一种用于防止多层磁性膜堆叠中的电短路的方法包括提供包括具有暴露表面的磁性材料层的膜堆叠。保护层沉积在磁性层的暴露表面上。保护层可以包括例如碳氟化合物或氢氟烃。蚀刻薄膜叠层并且保护层保护暴露的表面免受在蚀刻薄膜叠层时产生的导电残留物。该方法可以用于膜堆叠中以形成磁阻随机存取存储器（MRAM）装置。

3. 发明授权

US06642127B2 Method for dicing a semiconductor wafer 有权
标题翻译：切割半导体晶片的方法
公开(公告)号：US06642127B2
公开(公告)日：2003-11-04
申请号：US10035372
申请日：2001-10-19
申请人： Ajay Kumar , Padmapani C. Nallan , Anisul Khan , Dragan V. Podlesnik
发明人： Ajay Kumar , Padmapani C. Nallan , Anisul Khan , Dragan V. Podlesnik
IPC分类号： H01L21301
CPC分类号： H01L21/304 , H01L21/78
摘要： A method and apparatus for dicing a semiconductor wafer using a plasma etch process. The method begins by applying a patterned mask to the integrated circuits on a wafer. The pattern covers the circuits and exposes the streets between the dice. Next, the method deposits a uniform layer of adhesive material upon a carrier wafer. The wafer to be diced is affixed to the carrier wafer via the adhesive material that is sandwiched between the bottom surface of the wafer to be diced and the top surface of the carrier wafer. The combination assembly of the carrier wafer, adhesive and wafer to be diced is placed in an etch reactor that is capable of etching silicon. When the reactive gas is applied to the combination assembly, the etch plasma will consume the unprotected silicon within the streets and dice the wafer into individual integrated circuit chips. The carrier wafer is then removed from the etch chamber with the dice still attached to the adhesive layer. A well-known process is used to remove the adhesive material as well as any mask material and detach the dice from the carrier wafer.
摘要翻译：一种使用等离子体蚀刻工艺对半导体晶片进行切割的方法和装置。该方法开始于将图案化掩模应用于晶片上的集成电路。模式涵盖电路并暴露骰子之间的街道。接下来，该方法将均匀的粘合剂材料层沉积在载体晶片上。要切割的晶片通过夹在要切割的晶片的底表面和载体晶片的顶表面之间的粘合剂材料固定到载体晶片上。将要切割的载体晶片，粘合剂和晶片的组合组件放置在能够蚀刻硅的蚀刻反应器中。当将反应性气体施加到组合组件时，蚀刻等离子体将消耗街道内的未受保护的硅，并将晶片切割成单独的集成电路芯片。然后将载体晶片从蚀刻室移除，其中骰子仍附着到粘合剂层。使用众所周知的方法去除粘合剂材料以及任何掩模材料，并将骰子从载体晶片上分离。

4. 发明授权

US06415198B1 Plasma etching of silicon using a chlorine chemistry augmented with sulfur dioxide 失效
标题翻译：使用二氧化硫的氯化学等离子体蚀刻硅
公开(公告)号：US06415198B1
公开(公告)日：2002-07-02
申请号：US09344878
申请日：1999-06-25
申请人： Padmapani C. Nallan , Ajay Kumar , Jeffrey D. Chinn
发明人： Padmapani C. Nallan , Ajay Kumar , Jeffrey D. Chinn
IPC分类号： G06F1900
CPC分类号： H01J37/321 , H01J37/32935 , H01L21/3065
摘要： A method of etching silicon using a chlorine and sulfur dioxide gas chemistry. An embodiment of the method is accomplished using a 20 to 300 sccm of chlorine and 2 to 100 sccm of sulfur dioxide, regulated to a total chamber pressure of 2-100 mTorr.
摘要翻译：使用氯和二氧化硫气体化学蚀刻硅的方法。该方法的一个实施方案是使用20至300sccm的氯和2至100sccm的二氧化硫，调节至总室压力为2-100mTorr。

5. 发明授权

US07217665B2 Method of plasma etching high-K dielectric materials with high selectivity to underlying layers 失效
标题翻译：等离子体蚀刻高K电介质材料的方法，具有对底层的高选择性
公开(公告)号：US07217665B2
公开(公告)日：2007-05-15
申请号：US10301239
申请日：2002-11-20
申请人： Padmapani C. Nallan , Guangxiang Jin , Ajay Kumar
发明人： Padmapani C. Nallan , Guangxiang Jin , Ajay Kumar
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , H01L21/31122
摘要： A method of plasma etching a layer of dielectric material having a dielectric constant that is greater than four (4). The method includes exposing the dielectric material layer to a plasma comprising a hydrocarbon gas and a halogen containing gas.
摘要翻译：一种等离子体蚀刻具有大于四（4）的介电常数的介电材料层的方法。该方法包括将介电材料层暴露于包含烃气体和含卤素气体的等离子体。

6. 发明授权

US06855643B2 Method for fabricating a gate structure 失效
标题翻译：栅极结构的制造方法
公开(公告)号：US06855643B2
公开(公告)日：2005-02-15
申请号：US10194609
申请日：2002-07-12
申请人： Padmapani C. Nallan , Ajay Kumar
发明人： Padmapani C. Nallan , Ajay Kumar
IPC分类号： H01L21/28 , H01L21/3213 , H01L29/51 , H01L21/31 , H01L21/469
CPC分类号： H01L21/32137 , H01L21/28035 , H01L29/51 , H01L29/517 , H01L29/518
摘要： A method for fabricating a gate structure having a polysilicon electrode using an oxygen-free chemistry to etch the polysilicon. In one embodiment, the chemistry further includes nitrogen.
摘要翻译：一种使用无氧化学制造具有多晶硅电极以蚀刻多晶硅的栅极结构的方法。在一个实施方案中，化学还包括氮。

7. 发明授权

US06767824B2 Method of fabricating a gate structure of a field effect transistor using an alpha-carbon mask 失效
公开(公告)号：US06767824B2
公开(公告)日：2004-07-27
申请号：US10338251
申请日：2003-01-06
申请人： Padmapani C. Nallan , Ajay Kumar , Guangxiang Jin , Wei Liu
发明人： Padmapani C. Nallan , Ajay Kumar , Guangxiang Jin , Wei Liu
IPC分类号： H01L214763
CPC分类号： H01L21/31144 , H01L21/0273 , H01L21/28123 , H01L21/31122 , H01L21/31138 , H01L21/32137 , H01L21/32139 , Y10S438/945
摘要： A method of fabricating a gate structure of a field effect transistor comprising processes of forming an &agr;-carbon mask and plasma etching a gate electrode and a gate dielectric using the &agr;-carbon mask. In one embodiment, the gate dielectric comprises hafnium dioxide.

8. 发明授权

US06984585B2 Method for removal of residue from a magneto-resistive random access memory (MRAM) film stack using a sacrificial mask layer 失效
标题翻译：使用牺牲掩模层从磁阻随机存取存储器（MRAM）膜层去除残留物的方法
公开(公告)号：US06984585B2
公开(公告)日：2006-01-10
申请号：US10218473
申请日：2002-08-12
申请人： Chentsau Ying , Xiaoyi Chen , Padmapani C. Nallan , Ajay Kumar
发明人： Chentsau Ying , Xiaoyi Chen , Padmapani C. Nallan , Ajay Kumar
IPC分类号： H01L21/302
CPC分类号： H01L21/02071 , B82Y25/00 , B82Y40/00 , H01F41/308 , H01L21/31133 , H01L21/32136 , H01L21/32139 , H01L43/12
摘要： A method for removal of residues after plasma etching a film stack comprising a first layer and a sacrificial layer. The method treats a substrate containing the film stack after the first layer of the film stack has been etched to remove residue produced during the etching process. The treatment is performed in a buffered oxide etch wet dip solution that removes the residue and the sacrificial layer.
摘要翻译：一种用于在等离子体蚀刻包括第一层和牺牲层的薄膜堆叠之后去除残余物的方法。在蚀刻第一层薄膜叠层之后，该方法处理含有薄膜叠层的基板，以除去在蚀刻过程中产生的残留物。处理在缓冲氧化物蚀刻湿浸液中进行，其去除残余物和牺牲层。

9. 发明授权

US06942813B2 Method of etching magnetic and ferroelectric materials using a pulsed bias source 失效
标题翻译：使用脉冲偏压源蚀刻磁性和铁电材料的方法
公开(公告)号：US06942813B2
公开(公告)日：2005-09-13
申请号：US10382964
申请日：2003-03-05
申请人： Chentsau Ying , Padmapani C. Nallan , Ajay Kumar , Xiaoyi Chen
发明人： Chentsau Ying , Padmapani C. Nallan , Ajay Kumar , Xiaoyi Chen
IPC分类号： C23F4/00 , H01F41/30 , H01L21/311 , H01L21/3213 , H01L21/8246 , B44C1/22 , H01L21/00
CPC分类号： H01F41/308 , B82Y10/00 , B82Y25/00 , B82Y40/00 , C23F4/00 , H01F41/301 , H01J2237/3348 , H01L21/31122 , H01L21/32136 , H01L27/228 , H01L43/12
摘要： A method for etching magnetic and ferroelectric materials using a pulsed substrate biasing technique (PSBT) that applies a plurality of processing cycles to the substrate, where each cycle comprises a period of plasma etching without substrate bias and a period of plasma etching with the substrate bias. In exemplary applications, the method is used for fabricating magneto-resistive random access memory (MRAM) and ferroelectric random access memory (FeRAM) devices.
摘要翻译：一种使用向基板施加多个处理循环的脉冲衬底偏置技术（PSBT）蚀刻磁性和铁电材料的方法，其中每个循环包括没有衬底偏压的等离子体蚀刻周期和具有衬底偏置的等离子体蚀刻周期。在示例性应用中，该方法用于制造磁阻随机存取存储器（MRAM）和铁电随机存取存储器（FeRAM）器件。

10. 发明授权

US06902681B2 Method for plasma etching of high-K dielectric materials 失效
标题翻译：高K电介质材料等离子体蚀刻方法
公开(公告)号：US06902681B2
公开(公告)日：2005-06-07
申请号：US10184301
申请日：2002-06-26
申请人： Padmapani C. Nallan , Ajay Kumar
发明人： Padmapani C. Nallan , Ajay Kumar
IPC分类号： H01L21/28 , H01L21/311 , B44C1/22
CPC分类号： H01L21/31122 , H01L21/28123
摘要： A method of etching high dielectric constant materials (a material with a dielectric constant greater than 4) using a halogen gas, reducing gas, and passivating gas chemistry. An embodiment of the method is accomplished using chlorine, carbon monoxide, and nitrogen to etch and passivate a hafnium dioxide layer.
摘要翻译：使用卤素气体，还原气体和钝化气体化学法蚀刻高介电常数材料（介电常数大于4的材料）的方法。使用氯气，一氧化碳和氮气来实现该方法的一个实施例，以蚀刻和钝化二氧化铪层。

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