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1. 发明授权

US06415198B1 Plasma etching of silicon using a chlorine chemistry augmented with sulfur dioxide 失效
标题翻译：使用二氧化硫的氯化学等离子体蚀刻硅
公开(公告)号：US06415198B1
公开(公告)日：2002-07-02
申请号：US09344878
申请日：1999-06-25
申请人： Padmapani C. Nallan , Ajay Kumar , Jeffrey D. Chinn
发明人： Padmapani C. Nallan , Ajay Kumar , Jeffrey D. Chinn
IPC分类号： G06F1900
CPC分类号： H01J37/321 , H01J37/32935 , H01L21/3065
摘要： A method of etching silicon using a chlorine and sulfur dioxide gas chemistry. An embodiment of the method is accomplished using a 20 to 300 sccm of chlorine and 2 to 100 sccm of sulfur dioxide, regulated to a total chamber pressure of 2-100 mTorr.
摘要翻译：使用氯和二氧化硫气体化学蚀刻硅的方法。该方法的一个实施方案是使用20至300sccm的氯和2至100sccm的二氧化硫，调节至总室压力为2-100mTorr。

2. 发明授权

US06303513B1 Method for controlling a profile of a structure formed on a substrate 失效
标题翻译：用于控制形成在基板上的结构的轮廓的方法
公开(公告)号：US06303513B1
公开(公告)日：2001-10-16
申请号：US09326334
申请日：1999-06-07
申请人： Anisul Khan , Ajay Kumar , Dragan V. Podlesnik , Jeffrey D. Chinn
发明人： Anisul Khan , Ajay Kumar , Dragan V. Podlesnik , Jeffrey D. Chinn
IPC分类号： H01L2100
CPC分类号： H01L21/67069 , H01J37/321 , H01J37/3299 , H01L21/3065
摘要： A method for controlling a profile of a structure formed on a substrate using nitrogen trifluoride (NF3) in a high density plasma (HDP) process. Changing the amount of NF3 in the plasma controls the profile of the structure. It has been found that the best results are obtained with an inductively coupled plasma wherein the ion density is at least 1012 ions/cm3. The method is particularly suited to etch processes such as deep trench etch in silicon wafers.
摘要翻译：一种用于在高密度等离子体（HDP）工艺中使用三氟化氮（NF 3）在基板上形成的结构的轮廓进行控制的方法。改变等离子体中NF3的量控制结构的轮廓。已经发现，使用电感耦合等离子体获得最佳结果，其中离子密度为至少1012离子/ cm3。该方法特别适用于蚀刻诸如硅晶片中的深沟槽蚀刻的工艺。

3. 发明授权

US06372655B2 Two etchant etch method 失效
公开(公告)号：US06372655B2
公开(公告)日：2002-04-16
申请号：US09836934
申请日：2001-04-17
申请人： Anisul Khan , Ajay Kumar , Jeffrey D. Chinn , Dragan Podlesnik
发明人： Anisul Khan , Ajay Kumar , Jeffrey D. Chinn , Dragan Podlesnik
IPC分类号： H01L2100
CPC分类号： H01L21/30655 , B81B2203/033 , B81C1/00571 , B81C2201/0132 , H01L21/3065 , H01L21/32137
摘要： A two etchant etch method for etching a layer that is part of a masked structure is described. The method is useful, for example, in microelectrical mechanical system (MEMS) applications, and in the fabrication of integrated circuits and other electronic devices. The method can be used advantageously to optimize a plasma etch process capable of etching strict profile control trenches with 89°+/−1° sidewalls in silicon layers formed as part of a mask structure where the mask structure induces variations in etch rate. The inventive two etchant etch method etches a layer in a structure with a first etchant etch until a layer in a fastest etching region is etched. The layer is then etched with a second etchant until a layer in a region with a slowest etch rate is etched. A second etchant may also be selected to provide sidewall passivation and selectivity to an underlying layer of the structure.

4. 发明授权

US06518192B2 Two etchant etch method 失效
公开(公告)号：US06518192B2
公开(公告)日：2003-02-11
申请号：US10013115
申请日：2001-12-07
申请人： Anisul Khan , Ajay Kumar , Jeffrey D. Chinn , Dragan Podlesnik
发明人： Anisul Khan , Ajay Kumar , Jeffrey D. Chinn , Dragan Podlesnik
IPC分类号： H01L2100
CPC分类号： H01L21/30655 , B81B2203/033 , B81C1/00571 , B81C2201/0132 , H01L21/3065 , H01L21/32137
摘要： A two-step etch method for etching a masked layer or layers that include fast and slow etching regions is described. Fast and slow etching regions may arise in a variety of devices, such as microelectrical mechanical system (“MEMS”) applications and mixed signal (i.e. analog and digital) integrated circuits, as well as other integrated circuits and devices. In one embodiment, a first etchant is used to etch through the layer in the fastest etching region, and then a second etchant is used to complete etching through the layer in the slowest etching region.

5. 发明授权

US06391788B1 Two etchant etch method 失效
标题翻译：两种蚀刻剂蚀刻方法
公开(公告)号：US06391788B1
公开(公告)日：2002-05-21
申请号：US09513552
申请日：2000-02-25
申请人： Anisul Khan , Ajay Kumar , Jeffrey D. Chinn , Dragan Podlesnik
发明人： Anisul Khan , Ajay Kumar , Jeffrey D. Chinn , Dragan Podlesnik
IPC分类号： H01L2100
CPC分类号： H01L21/30655 , B81B2203/033 , B81C1/00571 , B81C2201/0132 , H01L21/3065 , H01L21/32137
摘要： A two etchant etch method for etching a layer that is part of a masked structure is described. The method is useful, for example, in microelectrical mechanical system (MEMS) applications, and in the fabrication of integrated circuits and other electronic devices. The method can be used advantageously to optimize a plasma etch process capable of etching strict profile control trenches with 89°+/−1° sidewalls in silicon layers formed as part of a mask structure where the mask structure induces variations in etch rate. The inventive two etchant etch method etches a layer in a structure with a first etchant etch until a layer in a fastest etching region is etched. The layer is then etched with a second etchant until a layer in a region with a slowest etch rate is etched. A second etchant may also be selected to provide sidewall passivation and selectivity to an underlying layer of the structure.
摘要翻译：描述了用于蚀刻作为掩模结构的一部分的层的两种蚀刻剂蚀刻方法。该方法例如在微电机械系统（MEMS）应用中以及集成电路和其它电子设备的制造中是有用的。该方法可以有利地用于优化等离子体蚀刻工艺，该等离子体蚀刻工艺能够蚀刻具有89°+/- 1°侧壁的严格轮廓控制沟槽，该硅层形成为掩模结构的一部分，其中掩模结构引起蚀刻速率的变化。本发明的两种蚀刻剂蚀刻方法蚀刻具有第一蚀刻剂蚀刻的结构中的层，直到蚀刻最快蚀刻区域中的层。然后用第二蚀刻剂蚀刻该层，直到蚀刻具有最慢蚀刻速率的区域中的层。还可以选择第二蚀刻剂以向结构的下层提供侧壁钝化和选择性。

6. 发明授权

US06802933B2 Apparatus for performing self cleaning method of forming deep trenches in silicon substrates 失效
标题翻译：用于在硅衬底中形成深沟槽的自清洁方法的装置
公开(公告)号：US06802933B2
公开(公告)日：2004-10-12
申请号：US09740146
申请日：2000-12-18
申请人： Anisul Khan , Ajay Kumar , Jeffrey D. Chinn , Dragan Podlesnik
发明人： Anisul Khan , Ajay Kumar , Jeffrey D. Chinn , Dragan Podlesnik
IPC分类号： C23F100
CPC分类号： H01L21/67069 , H01L21/3065 , H01L21/76232 , H01L27/1087 , Y10S156/916
摘要： This invention is directed to a method for etching films on semiconductor substrates and cleaning etch chambers. The method includes an improved processing sequence and cleaning method where residue formed from processing a previous substrate are cleaned by the etching process used to remove an exposed layer of material from the present substrate. The process provides improved substrate throughput by combining the step to clean residue from a previous substrate with an etch step conducted on the present substrate. Applicants have found the method particularly useful in processing structures such as DRAM stacks, especially where the residue is formed by a trench etched in the previous silicon substrate and the exposed layer etched from the present substrate is silicon nitride.
摘要翻译：本发明涉及一种用于蚀刻半导体衬底上的薄膜和清洗蚀刻室的方法。该方法包括改进的处理顺序和清洁方法，其中通过用于从本基板去除暴露的材料层的蚀刻工艺来清洁由先前基板处理形成的残留物。该方法通过将该步骤与在本发明的基底上进行的蚀刻步骤清洗来自先前基底的残余物来提供改进的基底产量。申请人已经发现该方法在诸如DRAM堆叠的处理结构中特别有用，特别是在通过在先前硅衬底中蚀刻的沟槽形成残留物的情况下，并且从本衬底蚀刻的暴露层是氮化硅。

7. 发明授权

US06368978B1 Hydrogen-free method of plasma etching indium tin oxide 失效
标题翻译：无氢等离子体蚀刻氧化铟锡的方法
公开(公告)号：US06368978B1
公开(公告)日：2002-04-09
申请号：US09262785
申请日：1999-03-04
申请人： Ajay Kumar , Padmapani Nallan , Jeffrey D. Chinn
发明人： Ajay Kumar , Padmapani Nallan , Jeffrey D. Chinn
IPC分类号： B01J1500
CPC分类号： H01L21/32136 , H01L31/1884 , Y02E10/50
摘要： The present invention is a method for hydrogen-free plasma etching of indium tin oxide using a plasma generated from an etchant gas containing chlorine as a major constituent (i.e., chlorine comprises at least 20 atomic %, preferably at least 50 atomic %, of the etchant gas). Etching is performed at a substrate temperature of 100° C. or lower. The chlorine-comprising gas is preferably Cl2. The etchant gas may further comprise a non-reactive gas, which is used to provide ion bombardment of the surface being etched, and which is preferably argon. The present invention provides a clean, fast method for plasma etching indium tin oxide. The method of the invention is particularly useful for etching a semiconductor device film stack which includes at least one layer of a material that would be adversely affected by exposure to hydrogen, such as N- or P-doped silicon.
摘要翻译：本发明是使用由含有氯作为主要成分的蚀刻剂气体产生的等离子体对氧化铟锡进行无氢等离子体蚀刻的方法（即氯包含至少20原子％，优选至少50原子％蚀刻剂气体）。在100℃以下的基板温度下进行蚀刻。含氯气体优选为Cl 2。蚀刻剂气体可以进一步包括非反应性气体，其用于提供被蚀刻的表面的离子轰击，并且其优选为氩。本发明提供了一种清洁，快速的等离子体蚀刻氧化铟锡的方法。本发明的方法特别适用于蚀刻半导体器件膜堆叠，其包括至少一层将受到暴露于氢的不利影响的材料，例如N或P掺杂的硅。

8. 发明授权

US06318384B1 Self cleaning method of forming deep trenches in silicon substrates 失效
标题翻译：在硅衬底中形成深沟槽的自清洗方法
公开(公告)号：US06318384B1
公开(公告)日：2001-11-20
申请号：US09405349
申请日：1999-09-24
申请人： Anisul Khan , Ajay Kumar , Jeffrey D. Chinn , Dragan Podlesnik
发明人： Anisul Khan , Ajay Kumar , Jeffrey D. Chinn , Dragan Podlesnik
IPC分类号： H01L21302
CPC分类号： H01L21/67069 , H01L21/3065 , H01L21/76232 , H01L27/1087 , Y10S156/916
摘要： This invention is directed to a method for etching films on semiconductor substrates and cleaning etch chambers. The method includes an improved processing sequence and cleaning method where residue formed from processing a previous substrate are cleaned by the etching process used to remove an exposed layer of material from the present substrate. The process provides improved substrate throughput by combining the step to clean residue from a previous substrate with an etch step conducted on the present substrate. Applicants have found the method particularly useful in processing structures such as DRAM stacks, especially where the residue is formed by a trench etched in the previous silicon substrate and the exposed layer etched from the present substrate is silicon nitride.
摘要翻译：本发明涉及一种用于蚀刻半导体衬底上的薄膜和清洗蚀刻室的方法。该方法包括改进的处理顺序和清洁方法，其中通过用于从本基板去除暴露的材料层的蚀刻工艺来清洁由先前基板处理形成的残留物。该方法通过将该步骤与在本发明的基底上进行的蚀刻步骤清洗来自先前基底的残余物来提供改进的基底产量。申请人已经发现该方法在诸如DRAM堆叠的处理结构中特别有用，特别是在通过在先前硅衬底中蚀刻的沟槽形成残留物的情况下，并且从本衬底蚀刻的暴露层是氮化硅。

9. 发明授权

US6103632A In situ Etching of inorganic dielectric anti-reflective coating from a substrate 失效
标题翻译：从基材原位蚀刻无机介电抗反射涂层
公开(公告)号：US6103632A
公开(公告)日：2000-08-15
申请号：US955771
申请日：1997-10-22
申请人： Ajay Kumar , Jeffrey D. Chinn
发明人： Ajay Kumar , Jeffrey D. Chinn
IPC分类号： H01L21/027 , H01L21/311 , H01L21/3213 , H01L21/302
CPC分类号： H01L21/32139 , H01L21/0276 , H01L21/31116 , H01L21/32137
摘要： The present invention is embodied in a method and apparatus for etching dielectric layers and inorganic ARC's without the need for removing the substrate being processed from the processing chamber and without the need for intervening processing steps such as chamber cleaning operations (in situ process). A layer and/or a multi-layer film deposited on a substrate, such as silicon, is located within a processing chamber. The substrate has a base, an underlying layer above the base, an overlying layer above the underlying layer, and a top dielectric anti-reflective coating (DARC) layer formed on the overlying layer. In the preferred method, first, the DARC layer and the overlying layer is etched by a first process gas. Next, the underlying layer is etched by a second process gas.
摘要翻译：本发明体现在一种用于蚀刻电介质层和无机ARC的方法和装置，而不需要从处理室移除正在处理的衬底，而不需要中间处理步骤，例如室清洁操作（原位处理）。沉积在诸如硅的衬底上的层和/或多层膜位于处理室内。基底具有基底，基底之上的下层，在下层之上的上覆层，以及形成在上覆层上的顶部介电抗反射涂层（DARC）层。在优选的方法中，首先，通过第一工艺气体蚀刻DARC层和上覆层。接下来，通过第二工艺气体蚀刻下层。

10. 发明授权

US09725805B2 Apparatus and method for controlled application of reactive vapors to produce thin films and coatings 有权
公开(公告)号：US09725805B2
公开(公告)日：2017-08-08
申请号：US11445706
申请日：2006-06-02
申请人： Boris Kobrin , Romuald Nowak , Richard C. Yi , Jeffrey D. Chinn
发明人： Boris Kobrin , Romuald Nowak , Richard C. Yi , Jeffrey D. Chinn
IPC分类号： C23C16/448 , C23C16/455 , B05D1/00 , B82Y30/00 , B05D3/14
CPC分类号： C23C16/45557 , B05D1/60 , B05D3/142 , B82Y30/00 , C23C16/4485 , C23C16/45561
摘要： A vapor phase deposition method and apparatus for the application of thin layers and coatings on substrates. The method and apparatus are useful in the fabrication of electronic devices, micro-electromechanical systems (MEMS), Bio-MEMS devices, micro and nano imprinting lithography, and microfluidic devices. The apparatus used to carry out the method provides for the addition of a precise amount of each of the reactants to be consumed in a single reaction step of the coating formation process. The apparatus provides for precise addition of quantities of different combinations of reactants during a single step or when there are a number of different individual steps in the coating formation process. The precise addition of each of the reactants in vapor form is metered into a predetermined set volume at a specified temperature to a specified pressure, to provide a highly accurate amount of reactant.

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