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1. 发明申请

US20060032833A1 Encapsulation of post-etch halogenic residue 审中-公开
标题翻译：蚀刻后的卤素残留物的封装
公开(公告)号：US20060032833A1
公开(公告)日：2006-02-16
申请号：US10915519
申请日：2004-08-10
申请人： Mark Kawaguchi , Thorsten Lill , Anisul Khan
发明人： Mark Kawaguchi , Thorsten Lill , Anisul Khan
IPC分类号： B44C1/22
CPC分类号： H01L21/0206 , H01L21/02063 , H01L21/02071 , H01L21/32136
摘要： A method of etching is provided that includes transferring a substrate into a vacuum environment, etching a material layer on the substrate and depositing a polymeric film encapsulating etch residues on the substrate without removing the substrate from the vacuum environment.
摘要翻译：提供了一种蚀刻方法，其包括将衬底转移到真空环境中，蚀刻衬底上的材料层并且在衬底上沉积封装蚀刻残留物的聚合物膜，而不从真空环境中移除衬底。

2. 发明授权

US06827869B2 Method of micromachining a multi-part cavity 失效
标题翻译：微加工多部分腔体的方法
公开(公告)号：US06827869B2
公开(公告)日：2004-12-07
申请号：US10194167
申请日：2002-07-11
申请人： Dragan Podlesnik , Thorsten Lill , Jeff Chinn , Shaoher X. Pan , Anisul Khan , Maocheng Li , Yiqiong Wang
发明人： Dragan Podlesnik , Thorsten Lill , Jeff Chinn , Shaoher X. Pan , Anisul Khan , Maocheng Li , Yiqiong Wang
IPC分类号： H01L21302
CPC分类号： H01L27/1087 , B81B2201/052 , B81B2203/0315 , B81B2203/033 , B81C1/00119 , B81C2201/016 , H01L21/3065 , H01L21/3086
摘要： The present disclosure pertains to our discovery of a particularly efficient method for etching a multi-part cavity in a substrate. The method provides for first etching a shaped opening, depositing a protective layer over at least a portion of the inner surface of the shaped opening, and then etching a shaped cavity directly beneath and in continuous communication with the shaped opening. The protective layer protects the etch profile of the shaped opening during etching of the shaped cavity, so that the shaped opening and the shaped cavity can be etched to have different shapes, if desired. In particular embodiments of the method of the invention, lateral etch barrier layers and/or implanted etch stops are also used to direct the etching process. The method of the invention can be applied to any application where it is necessary or desirable to provide a shaped opening and an underlying shaped cavity having varying shapes. The method is also useful whenever it is necessary to maintain tight control over the dimensions of the shaped opening.
摘要翻译：本公开涉及我们发现用于蚀刻衬底中的多部分空腔的特别有效的方法。该方法提供了首先蚀刻成形开口，在成形开口的内表面的至少一部分上沉积保护层，然后直接在成形开口下面蚀刻成形腔，并与成形开口连续连通。保护层在蚀刻成形腔体期间保护成形开口的蚀刻轮廓，从而如果需要，成形开口和成形腔体可以被蚀刻以具有不同的形状。在本发明方法的特定实施例中，横向蚀刻阻挡层和/或注入的蚀刻停止点也用于引导蚀刻工艺。本发明的方法可以应用于需要或期望提供具有不同形状的成形开口和下面的成形腔的任何应用。只要需要对成形开口的尺寸进行严格控制，该方法也是有用的。

3. 发明授权

US06270634B1 Method for plasma etching at a high etch rate 失效
标题翻译：用于以高蚀刻速率进行等离子体蚀刻的方法
公开(公告)号：US06270634B1
公开(公告)日：2001-08-07
申请号：US09430798
申请日：1999-10-29
申请人： Ajay Kumar , Anisul Khan , Jeffrey D Chinn , Dragan Podlesnik
发明人： Ajay Kumar , Anisul Khan , Jeffrey D Chinn , Dragan Podlesnik
IPC分类号： C23C1434
CPC分类号： H01L21/67069 , H01J37/321 , H01J37/32935 , H01L21/3065
摘要： This invention is directed to a method for rapid plasma etching of materials which are difficult to etch at a high rate. The method is particularly useful in plasma etching silicon nitride layers more than five microns thick. The method includes the use of a plasma source gas that includes an etchant gas and a sputtering gas. Two separate power sources are used in the etching process and the power to each power source as well as the ratio between the flow rates of the etchant gas and sputtering gas can be advantageously adjusted to obtain etch rates of silicon nitride greater than two microns per minute. Additionally, an embodiment of the method of the invention provides a two etch step process which combines a high etch rate process with a low etch rate process to achieve high throughput while minimizing the likelihood of damage to underlying layers. The first etch step of the two-step method provides a high etch rate of about two microns per minute to remove substantially all of a layer to be etched. In the second step, a low etch rate process having an etch rate below about two microns per minute is used to remove any residual material not removed by the first etch step.
摘要翻译：本发明涉及用于快速等离子体蚀刻难以高速蚀刻的材料的方法。该方法在等离子体蚀刻中超过5微米厚的氮化硅层特别有用。该方法包括使用包括蚀刻剂气体和溅射气体的等离子体源气体。在蚀刻工艺中使用两个单独的电源，并且可以有利地调整蚀刻剂气体和溅射气体的流量之间的比例，以获得大于每分钟2微米的氮化硅的蚀刻速率。另外，本发明的方法的一个实施例提供了两个蚀刻步骤方法，其将高蚀刻速率工艺与低蚀刻速率工艺组合以实现高通量，同时最小化对下层的损伤的可能性。两步法的第一蚀刻步骤提供了每分钟约2微米的高蚀刻速率，以便基本上除去所有待蚀刻的层。在第二步骤中，使用蚀刻速率低于每分钟约2微米的低蚀刻速率工艺来去除通过第一蚀刻步骤未被去除的任何残留材料。

4. 发明授权

US08231736B2 Wet clean process for recovery of anodized chamber parts 有权
标题翻译：用于回收阳极氧化室部件的湿清洁工艺
公开(公告)号：US08231736B2
公开(公告)日：2012-07-31
申请号：US11845620
申请日：2007-08-27
申请人： Jennifer Y. Sun , Senh Thach , Xi Zhu , Li Xu , Anisul Khan
发明人： Jennifer Y. Sun , Senh Thach , Xi Zhu , Li Xu , Anisul Khan
IPC分类号： B08B3/00
CPC分类号： C23C16/4407 , C11D7/08 , C11D7/10 , C11D11/0047 , C11D11/0064
摘要： A cleaning process for recovering an anodized aluminum part is particularly useful when the part has been exposed to a fluorine-containing plasma in etch reactor. The part is bathed in an agitated solution of a fluoride acid, such as ammonium fluoride, which converts aluminum fluoride to a soluble fluoride. The part is rinsed in water. The pores of the cleaned anodization may be resealed by a submerging the part in hot agitated deionized water.
摘要翻译：当在蚀刻反应器中暴露于含氟等离子体时，用于回收阳极氧化铝部件的清洁方法是特别有用的。将该部分浸渍在氟化物酸如氟化铵的搅拌溶液中，其将氟化铝转化为可溶性氟化物。该部件在水中冲洗。清洁的阳极氧化的孔可以通过将部件浸没在热的搅拌去离子水中来重新密封。

5. 发明授权

US06954561B1 Methods for forming thermo-optic switches, routers and attenuators 失效
标题翻译：形成热电开关，路由器和衰减器的方法
公开(公告)号：US06954561B1
公开(公告)日：2005-10-11
申请号：US09907183
申请日：2001-07-16
申请人： Anisul Khan , Ajay Kumar
发明人： Anisul Khan , Ajay Kumar
IPC分类号： G02F1/01 , G02F1/313 , G02B6/12
CPC分类号： G02F1/0147 , G02F1/011 , G02F1/313
摘要： Thermo-optic devices including a bottom cladding layer, a patterned core material and a top cladding layer, each having a different refractive index, can be made by depositing a heater material, such as tungsten or chromium, on the outside of the bottom and/or top cladding layer. Depending on the refractive index differences between the cladding layers and the core layers, the amount of heater material can also be varied. The heater material can surround the cladding layers, can be present on the sidewalls and top only, or the sidewalls alone, to provide sufficient heat to change the refractive index of the layers and thus the path of light passing-through the device. These devices when built into the substrate can be connected to underlying devices for vertical integration, or connected to other devices and components formed on the same substrate for increased integration.
摘要翻译：可以通过在底部和/或底部的外侧沉积诸如钨或铬的加热材料来形成包括底部包层，图案化芯材料和折射率不同的顶部包层的热光器件，或上覆层。取决于包覆层和芯层之间的折射率差异，加热器材料的量也可以变化。加热器材料可以围绕包覆层，可以仅存在于侧壁和顶部或单独的侧壁上，以提供足够的热量来改变层的折射率，从而改变穿过该装置的光的路径。当这些器件内置于基板中时，可以连接到底层器件以进行垂直整合，或者连接到形成在同一衬底上的其他器件和元件，以增加集成度。

6. 发明授权

US06696365B2 Process for in-situ etching a hardmask stack 失效
标题翻译：用于原位蚀刻硬掩模堆栈的过程
公开(公告)号：US06696365B2
公开(公告)日：2004-02-24
申请号：US10041540
申请日：2002-01-07
申请人： Ajay Kumar , Anisul Khan , Sanjay Thekdi , Dragan V. Podlesnik
发明人： Ajay Kumar , Anisul Khan , Sanjay Thekdi , Dragan V. Podlesnik
IPC分类号： H01L21302
CPC分类号： H01L21/3081 , H01L21/0276 , H01L21/3065 , H01L21/31116
摘要： A method of etching high aspect ratio, anisotropic deep trench openings in a silicon substrate coated with a multilayer mask comprising in sequence a pad oxide layer, a silicon nitride layer, a doped or undoped silicon oxide hard mask layer, a polysilicon hard mask layer, an antireflection coating and a patterned photoresist layer in a single chamber comprising patterning the antireflection coating and hard mask layer, removing the photoresist and antireflection layers with oxygen, using the patterned polysilicon as a hard mask layer etching an opening in the silicon oxide hard mask layer, the silicon nitride layer and the pad oxide layer, removing the polysilicon hard mask layer with CF4/CHF3, and etching an anisotropic deep trench in the silicon substrate using the patterned silicon oxide hard mask layer as a mask and an etchant mixture including nitrogen trifluoride that self-cleans the chamber.
摘要翻译：一种在涂覆有多层掩模的硅衬底中蚀刻高纵横比的各向异性深沟槽开口的方法，其中依次包括衬垫氧化物层，氮化硅层，掺杂或未掺杂的氧化硅硬掩模层，多晶硅硬掩模层，抗反射涂层和图案化的光致抗蚀剂层，其包括使抗反射涂层和硬掩模层图案化，用氧去除光致抗蚀剂和抗反射层，使用图案化多晶硅作为蚀刻氧化硅硬掩模层中的开口的硬掩模层，氮化硅层和焊盘氧化物层，用CF4 / CHF3去除多晶硅硬掩模层，并使用图案化的氧化硅硬掩模层作为掩模蚀刻硅衬底中的各向异性深沟槽，以及包括三氟化氮的蚀刻剂混合物自我清理的房间。

7. 发明授权

US06518192B2 Two etchant etch method 失效
公开(公告)号：US06518192B2
公开(公告)日：2003-02-11
申请号：US10013115
申请日：2001-12-07
申请人： Anisul Khan , Ajay Kumar , Jeffrey D. Chinn , Dragan Podlesnik
发明人： Anisul Khan , Ajay Kumar , Jeffrey D. Chinn , Dragan Podlesnik
IPC分类号： H01L2100
CPC分类号： H01L21/30655 , B81B2203/033 , B81C1/00571 , B81C2201/0132 , H01L21/3065 , H01L21/32137
摘要： A two-step etch method for etching a masked layer or layers that include fast and slow etching regions is described. Fast and slow etching regions may arise in a variety of devices, such as microelectrical mechanical system (“MEMS”) applications and mixed signal (i.e. analog and digital) integrated circuits, as well as other integrated circuits and devices. In one embodiment, a first etchant is used to etch through the layer in the fastest etching region, and then a second etchant is used to complete etching through the layer in the slowest etching region.

8. 发明授权

US06471833B2 High etch rate method for plasma etching silicon nitride 失效
标题翻译：用于等离子体蚀刻氮化硅的高蚀刻速率方法
公开(公告)号：US06471833B2
公开(公告)日：2002-10-29
申请号：US09853847
申请日：2001-05-11
申请人： Ajay Kumar , Anisul Khan , Jeffrey D Chin , Dragan V Podlesnik
发明人： Ajay Kumar , Anisul Khan , Jeffrey D Chin , Dragan V Podlesnik
IPC分类号： C23C1434
CPC分类号： H01L21/67069 , H01J37/321 , H01J37/32935 , H01L21/3065
摘要： This invention is directed to a method for rapid plasma etching of materials which are difficult to etch at a high rate. The method is particularly useful in plasma etching silicon nitride layers more than five microns thick. The method includes the use of a plasma source gas that includes an etchant gas and a sputtering gas. Two separate power sources are used in the etching process and the power to each power source as well as the ratio between the flow rates of the etchant gas and sputtering gas can be advantageously adjusted to obtain etch rates of silicon nitride greater than two microns per minute. Additionally, an embodiment of the method of the invention provides a two etch step process which combines a high etch rate process with a low etch rate process to achieve high throughput while minimizing the likelihood of damage to underlying layers. The first etch step of the two-step method provides a high etch rate of about two microns per minute to remove substantially all of a layer to be etched. In the second step, a low etch rate process having an etch rate below about two microns per minute is used to remove any residual material not removed by the first etch step.
摘要翻译：本发明涉及用于快速等离子体蚀刻难以高速蚀刻的材料的方法。该方法在等离子体蚀刻中超过5微米厚的氮化硅层特别有用。该方法包括使用包括蚀刻剂气体和溅射气体的等离子体源气体。在蚀刻工艺中使用两个单独的电源，并且可以有利地调整蚀刻剂气体和溅射气体的流量之间的比例，以获得大于每分钟2微米的氮化硅的蚀刻速率。另外，本发明的方法的一个实施例提供了两个蚀刻步骤方法，其将高蚀刻速率工艺与低蚀刻速率工艺组合以实现高通量，同时最小化对下层的损伤的可能性。两步法的第一蚀刻步骤提供了每分钟约2微米的高蚀刻速率，以便基本上除去所有待蚀刻的层。在第二步骤中，使用蚀刻速率低于每分钟约2微米的低蚀刻速率工艺来去除通过第一蚀刻步骤未被去除的任何残留材料。

9. 发明授权

US06391788B1 Two etchant etch method 失效
标题翻译：两种蚀刻剂蚀刻方法
公开(公告)号：US06391788B1
公开(公告)日：2002-05-21
申请号：US09513552
申请日：2000-02-25
申请人： Anisul Khan , Ajay Kumar , Jeffrey D. Chinn , Dragan Podlesnik
发明人： Anisul Khan , Ajay Kumar , Jeffrey D. Chinn , Dragan Podlesnik
IPC分类号： H01L2100
CPC分类号： H01L21/30655 , B81B2203/033 , B81C1/00571 , B81C2201/0132 , H01L21/3065 , H01L21/32137
摘要： A two etchant etch method for etching a layer that is part of a masked structure is described. The method is useful, for example, in microelectrical mechanical system (MEMS) applications, and in the fabrication of integrated circuits and other electronic devices. The method can be used advantageously to optimize a plasma etch process capable of etching strict profile control trenches with 89°+/−1° sidewalls in silicon layers formed as part of a mask structure where the mask structure induces variations in etch rate. The inventive two etchant etch method etches a layer in a structure with a first etchant etch until a layer in a fastest etching region is etched. The layer is then etched with a second etchant until a layer in a region with a slowest etch rate is etched. A second etchant may also be selected to provide sidewall passivation and selectivity to an underlying layer of the structure.
摘要翻译：描述了用于蚀刻作为掩模结构的一部分的层的两种蚀刻剂蚀刻方法。该方法例如在微电机械系统（MEMS）应用中以及集成电路和其它电子设备的制造中是有用的。该方法可以有利地用于优化等离子体蚀刻工艺，该等离子体蚀刻工艺能够蚀刻具有89°+/- 1°侧壁的严格轮廓控制沟槽，该硅层形成为掩模结构的一部分，其中掩模结构引起蚀刻速率的变化。本发明的两种蚀刻剂蚀刻方法蚀刻具有第一蚀刻剂蚀刻的结构中的层，直到蚀刻最快蚀刻区域中的层。然后用第二蚀刻剂蚀刻该层，直到蚀刻具有最慢蚀刻速率的区域中的层。还可以选择第二蚀刻剂以向结构的下层提供侧壁钝化和选择性。

10. 发明申请

US20090170333A1 SHALLOW TRENCH ISOLATION ETCH PROCESS 失效
标题翻译： SHOWOW TRENCH隔离蚀刻工艺
公开(公告)号：US20090170333A1
公开(公告)日：2009-07-02
申请号：US12325220
申请日：2008-11-30
申请人： Hiroki Sasano , Meihua Shen , Radhika Mani , Sunil Srinivasan , Daehee Weon , Nicolas Gani , Shashank Deshmukh , Anisul Khan
发明人： Hiroki Sasano , Meihua Shen , Radhika Mani , Sunil Srinivasan , Daehee Weon , Nicolas Gani , Shashank Deshmukh , Anisul Khan
IPC分类号： H01L21/302
CPC分类号： H01L21/3065 , H01L21/76224
摘要： Methods for fabricating one or more shallow trench isolation (STI) structures are provided herein. In some embodiments, a method for fabricating one or more shallow trench isolation (STI) structures may include providing a substrate having a patterned mask layer disposed thereon to define one or more STI structures. The substrate may be etched using a plasma formed from a process gas mixture to form one or more STI structures on the substrate, wherein the process gas mixture comprises a fluorine-containing gas and either a fluorocarbon-containing gas or a hydrofluorocarbon-containing gas.
摘要翻译：本文提供了制造一个或多个浅沟槽隔离（STI）结构的方法。在一些实施例中，用于制造一个或多个浅沟槽隔离（STI）结构的方法可以包括提供具有设置在其上以限定一个或多个STI结构的图案化掩模层的衬底。可以使用由工艺气体混合物形成的等离子体来蚀刻衬底，以在衬底上形成一个或多个STI结构，其中工艺气体混合物包含含氟气体和含氟烃气体或含氢氟烃的气体。

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