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    • 2. 发明授权
    • Deposited semiconductor structure to minimize N-type dopant diffusion and method of making
    • 沉积的半导体结构使N型掺杂剂扩散最小化和制备方法
    • US08314477B2
    • 2012-11-20
    • US13247723
    • 2011-09-28
    • S. Brad Herner
    • S. Brad Herner
    • H01L21/02
    • H01L45/08H01L27/1021H01L27/2409H01L27/2463H01L29/161H01L29/165H01L45/04H01L45/1233H01L45/145H01L45/146
    • A memory cell is provided that includes a semiconductor pillar and a reversible state-change element coupled to the semiconductor pillar. The semiconductor pillar includes a heavily doped bottom region of a first conductivity type, a heavily doped top region of a second conductivity type, and a lightly doped or intrinsic middle region interposed between and contacting the top and bottom regions. The middle region comprises a first proportion of germanium, and either the top region or the bottom region comprises no germanium or comprises a second proportion of germanium less than the first proportion. The reversible state-change element includes a layer of a resistivity-switching metal oxide or nitride compound selected from the group consisting of NiO, Nb2O5, TiO2, HfO2, Al2O3, CoO, MgOx, CrO2, VO, BN, and AlN. Numerous other aspects are provided.
    • 提供了存储单元,其包括半导体柱和耦合到半导体柱的可逆状态变换元件。 半导体柱包括第一导电类型的重掺杂底部区域,第二导电类型的重掺杂顶部区域,以及插入并接触顶部区域和底部区域之间的轻掺杂或固有中间区域。 中间区域包括第一比例的锗,并且顶部区域或底部区域不包含锗,或者包括小于第一比例的第二比例的锗。 可逆态变化元件包括选自NiO,Nb 2 O 5,TiO 2,HfO 2,Al 2 O 3,CoO,MgO x,CrO 2,VO,BN和AlN的电阻率切换金属氧化物或氮化物层。 提供了许多其他方面。
    • 3. 发明授权
    • Nonvolatile memory cell operating by increasing order in polycrystalline semiconductor material
    • 非易失性存储单元通过增加多晶半导体材料的顺序来操作
    • US08243509B2
    • 2012-08-14
    • US13074509
    • 2011-03-29
    • S. Brad HernerAbhijit Bandyopadhyay
    • S. Brad HernerAbhijit Bandyopadhyay
    • G11C11/36G11C11/34G11C11/00
    • G11C11/36G11C5/02G11C11/39G11C17/06G11C17/16H01L27/1021
    • A nonvolatile memory cell is described, the memory cell comprising a semiconductor diode. The semiconductor material making up the diode is formed with significant defect density, and allows very low current flow at a typical read voltage. Application of a programming voltage permanently changes the nature of the semiconductor material, resulting in an improved diode. The programmed diode allows much higher current flow, in some embodiments one, two or three orders of magnitude higher, at the same read voltage. The difference in current allows a programmed memory cell to be distinguished from an unprogrammed memory cell. Fabrication techniques to generate an advantageous unprogrammed defect density are described. The memory cell of the present invention can be formed in a monolithic three dimensional memory array, having multiple stacked memory levels formed above a single substrate.
    • 描述非易失性存储单元,存储单元包括半导体二极管。 构成二极管的半导体材料形成有明显的缺陷密度,并且在典型的读取电压下允许非常低的电流流动。 编程电压的应用永久地改变了半导体材料的性质,导致改进的二极管。 在相同的读取电压下,编程的二极管允许更高的电流流动,在一些实施例中高一个,两个或三个数量级。 电流差异允许将编程的存储器单元与未编程的存储器单元进行区分。 描述了产生有利的未编程缺陷密度的制造技术。 本发明的存储单元可以形成为在单个衬底上形成多个堆叠存储器级的单片三维存储器阵列。
    • 7. 发明授权
    • High-density nonvolatile memory
    • 高密度非易失性存储器
    • US08004033B2
    • 2011-08-23
    • US12477216
    • 2009-06-03
    • S. Brad HernerMaitreyee Mahajani
    • S. Brad HernerMaitreyee Mahajani
    • H01L29/788
    • G11C5/02H01L21/8238H01L23/48H01L27/1021H01L27/148H01L29/94H01L2924/0002H01L2924/00
    • Nonvolatile memory cells and methods of forming the same are provided, the methods including forming a first conductor at a first height above a substrate; forming a first pillar-shaped semiconductor element above the first conductor, wherein the first pillar-shaped semiconductor element comprises a first heavily doped layer of a first conductivity type, a second lightly doped layer above and in contact with the first heavily doped layer, and a third heavily doped layer of a second conductivity type above and in contact with the second lightly doped layer, the second conductivity type opposite the first conductivity type; forming a first dielectric antifuse above the third heavily doped layer of the first pillar-shaped semiconductor element; and forming a second conductor above the first dielectric antifuse.
    • 提供了非易失存储器单元及其形成方法,所述方法包括在衬底上方的第一高度处形成第一导体; 在所述第一导体上形成第一柱状半导体元件,其中所述第一柱状半导体元件包括第一导电类型的第一重掺杂层,在所述第一重掺杂层上方并与其接触的第二轻掺杂层,以及 第二导电类型的第三重掺杂层在第二轻掺杂层上方并与第二轻掺杂层接触,第二导电类型与第一导电类型相反; 在所述第一柱状半导体元件的所述第三重掺杂层的上方形成第一介电反熔丝; 以及在所述第一介电反熔丝之上形成第二导体。