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1. 发明授权

US07238607B2 Method to minimize formation of recess at surface planarized by chemical mechanical planarization 有权
标题翻译：通过化学机械平面化平坦化的表面减少凹陷形成的方法
公开(公告)号：US07238607B2
公开(公告)日：2007-07-03
申请号：US11237169
申请日：2005-09-28
申请人： Samuel V. Dunton , S. Brad Herner
发明人： Samuel V. Dunton , S. Brad Herner
IPC分类号： H01L21/4763
CPC分类号： G11C11/39 , G11C5/02 , G11C17/16 , G11C2213/71 , G11C2213/77
摘要： When chemical mechanical planarization (CMP) is used to planarize a surface coexposing patterned features and dielectric fill, where patterned features and the fill are formed of materials having very different CMP removal rates or characteristics, the planarized surface may have excessively rough, dishing or recessing may take place, or one or more or the materials may be damaged. In structures in which planarity is important, these problems can be prevented by forming a capping layer on the patterned features, wherein the CMP removal rate of the material forming the capping layer is similar to the CMP removal rate of the dielectric fill.
摘要翻译：当化学机械平面化（CMP）用于平坦化表面共同图案化特征和电介质填充时，其中图案特征和填充物由具有非常不同的CMP去除速率或特性的材料形成，平坦化表面可能具有过度粗糙，凹陷或凹陷可能发生，或者一个或多个，或者材料可能被损坏。在平面度重要的结构中，通过在图案化特征上形成覆盖层可以防止这些问题，其中形成覆盖层的材料的CMP去除速率类似于介电填料的CMP去除速率。

2. 发明授权

US08314477B2 Deposited semiconductor structure to minimize N-type dopant diffusion and method of making 有权
标题翻译：沉积的半导体结构使N型掺杂剂扩散最小化和制备方法
公开(公告)号：US08314477B2
公开(公告)日：2012-11-20
申请号：US13247723
申请日：2011-09-28
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： H01L21/02
CPC分类号： H01L45/08 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L29/161 , H01L29/165 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146
摘要： A memory cell is provided that includes a semiconductor pillar and a reversible state-change element coupled to the semiconductor pillar. The semiconductor pillar includes a heavily doped bottom region of a first conductivity type, a heavily doped top region of a second conductivity type, and a lightly doped or intrinsic middle region interposed between and contacting the top and bottom regions. The middle region comprises a first proportion of germanium, and either the top region or the bottom region comprises no germanium or comprises a second proportion of germanium less than the first proportion. The reversible state-change element includes a layer of a resistivity-switching metal oxide or nitride compound selected from the group consisting of NiO, Nb2O5, TiO2, HfO2, Al2O3, CoO, MgOx, CrO2, VO, BN, and AlN. Numerous other aspects are provided.
摘要翻译：提供了存储单元，其包括半导体柱和耦合到半导体柱的可逆状态变换元件。半导体柱包括第一导电类型的重掺杂底部区域，第二导电类型的重掺杂顶部区域，以及插入并接触顶部区域和底部区域之间的轻掺杂或固有中间区域。中间区域包括第一比例的锗，并且顶部区域或底部区域不包含锗，或者包括小于第一比例的第二比例的锗。可逆态变化元件包括选自NiO，Nb 2 O 5，TiO 2，HfO 2，Al 2 O 3，CoO，MgO x，CrO 2，VO，BN和AlN的电阻率切换金属氧化物或氮化物层。提供了许多其他方面。

3. 发明授权

US08243509B2 Nonvolatile memory cell operating by increasing order in polycrystalline semiconductor material 有权
标题翻译：非易失性存储单元通过增加多晶半导体材料的顺序来操作
公开(公告)号：US08243509B2
公开(公告)日：2012-08-14
申请号：US13074509
申请日：2011-03-29
申请人： S. Brad Herner , Abhijit Bandyopadhyay
发明人： S. Brad Herner , Abhijit Bandyopadhyay
IPC分类号： G11C11/36 , G11C11/34 , G11C11/00
CPC分类号： G11C11/36 , G11C5/02 , G11C11/39 , G11C17/06 , G11C17/16 , H01L27/1021
摘要： A nonvolatile memory cell is described, the memory cell comprising a semiconductor diode. The semiconductor material making up the diode is formed with significant defect density, and allows very low current flow at a typical read voltage. Application of a programming voltage permanently changes the nature of the semiconductor material, resulting in an improved diode. The programmed diode allows much higher current flow, in some embodiments one, two or three orders of magnitude higher, at the same read voltage. The difference in current allows a programmed memory cell to be distinguished from an unprogrammed memory cell. Fabrication techniques to generate an advantageous unprogrammed defect density are described. The memory cell of the present invention can be formed in a monolithic three dimensional memory array, having multiple stacked memory levels formed above a single substrate.
摘要翻译：描述非易失性存储单元，存储单元包括半导体二极管。构成二极管的半导体材料形成有明显的缺陷密度，并且在典型的读取电压下允许非常低的电流流动。编程电压的应用永久地改变了半导体材料的性质，导致改进的二极管。在相同的读取电压下，编程的二极管允许更高的电流流动，在一些实施例中高一个，两个或三个数量级。电流差异允许将编程的存储器单元与未编程的存储器单元进行区分。描述了产生有利的未编程缺陷密度的制造技术。本发明的存储单元可以形成为在单个衬底上形成多个堆叠存储器级的单片三维存储器阵列。

4. 发明授权

US08163593B2 Method of making a nonvolatile phase change memory cell having a reduced contact area 有权
标题翻译：制造具有减小的接触面积的非挥发性相变存储单元的方法
公开(公告)号：US08163593B2
公开(公告)日：2012-04-24
申请号：US11560792
申请日：2006-11-16
申请人： Usha Raghuram , S. Brad Herner
发明人： Usha Raghuram , S. Brad Herner
IPC分类号： H01L21/00
CPC分类号： H01L45/144 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1683 , H01L45/1691
摘要： A method is described to form a nonvolatile memory cell having a contact area between a phase-change material such as a chalcogenide and a heat source which is smaller than photolithographic limits. A conductive or semiconductor pillar is exposed at a dielectric surface and recessed by selective etch. A thin, conformal layer of a spacer material is deposited on the dielectric top surface, the pillar top surface, and the sidewalls of the recess, then removed from horizontal surfaces by anistropic etch, leaving a spacer on the sidewalls defining a reduced volume within the recess. The phase change material is deposited within the spacer, having a reduced contact area to the underlying conductive or semiconductor pillar.
摘要翻译：描述了一种形成非易失性存储单元的方法，所述非易失性存储单元具有诸如硫族化物的相变材料与小于光刻极限的热源之间的接触面积。导电或半导体柱在电介质表面露出并通过选择性蚀刻凹陷。间隔材料的薄的共形层被沉积在电介质顶表面，柱顶表面和凹槽的侧壁上，然后通过无功蚀刻从水平表面去除，在侧壁上留下间隔，限定内部减小的体积休息。相变材料沉积在间隔物内，具有减小的与下面的导电或半导体柱的接触面积。

5. 发明授权

US08049104B2 Intermetal stack for use in a photovoltaic cell 有权
标题翻译：用于光伏电池的金属间叠层
公开(公告)号：US08049104B2
公开(公告)日：2011-11-01
申请号：US12571415
申请日：2009-09-30
申请人： S. Brad Herner , Mark H. Clark
发明人： S. Brad Herner , Mark H. Clark
IPC分类号： H01L31/00
CPC分类号： H01L31/0747 , H01L21/187 , H01L31/1804 , H01L31/1896 , Y02E10/547 , Y02P70/521
摘要： A donor silicon wafer may be bonded to a substrate and a lamina cleaved from the donor wafer. A photovoltaic cell may be formed from the lamina bonded to the substrate. An intermetal stack is described that is optimized for use in such a cell. The intermetal stack may include a transparent conductive oxide layer serving as a quarter-wave plate, a low resistance layer, an adhesion layer to help adhesion to the receiver element, and may also include a barrier layer to prevent or impede unwanted diffusion within the stack.
摘要翻译：供体硅晶片可以结合到基底和从施主晶片分离的薄片。可以从结合到衬底的薄片形成光伏电池。描述了优化用于这种电池的金属间堆叠。金属间堆叠可以包括用作四分之一波片的透明导电氧化物层，低电阻层，用于帮助粘附到接收器元件的粘合层，并且还可以包括防止或阻碍堆叠内的不期望扩散的阻挡层。

6. 发明授权

US08018025B2 Nonvolatile memory cell comprising a reduced height vertical diode 有权
标题翻译：非易失性存储单元包括减小的高度的垂直二极管
公开(公告)号：US08018025B2
公开(公告)日：2011-09-13
申请号：US12481684
申请日：2009-06-10
申请人： S. Brad Herner , Steven J. Radigan
发明人： S. Brad Herner , Steven J. Radigan
IPC分类号： H01L29/00
CPC分类号： G11C5/02 , G11C11/39 , G11C17/06 , G11C17/16 , G11C2213/71 , G11C2213/77 , H01L27/1021 , H01L29/0649 , H01L29/66272 , H01L29/732 , H01L29/868
摘要： A nonvolatile memory cell includes: a rail-shaped first conductor formed at a first height above a substrate; a rail-shaped second conductor formed above the first conductor; and a vertically oriented first pillar comprising a p-i-n first diode; wherein the first pillar is disposed between the second conductor and the first conductor; wherein the first diode comprises an intrinsic or lightly doped region; and wherein the intrinsic or lightly doped region has a first thickness of about 300 angstroms or greater. Numerous additional aspects are provided.
摘要翻译：非易失性存储单元包括：形成在衬底上方的第一高度处的轨道状第一导体; 形成在第一导体上方的轨道形状的第二导体; 以及包括p-i-n第一二极管的垂直取向的第一柱; 其中所述第一柱设置在所述第二导体和所述第一导体之间; 其中所述第一二极管包括固有或轻掺杂区域; 并且其中所述固有或轻掺杂区域具有约300埃或更大的第一厚度。还提供了许多其他方面。

7. 发明授权

US08004033B2 High-density nonvolatile memory 有权
标题翻译：高密度非易失性存储器
公开(公告)号：US08004033B2
公开(公告)日：2011-08-23
申请号：US12477216
申请日：2009-06-03
申请人： S. Brad Herner , Maitreyee Mahajani
发明人： S. Brad Herner , Maitreyee Mahajani
IPC分类号： H01L29/788
CPC分类号： G11C5/02 , H01L21/8238 , H01L23/48 , H01L27/1021 , H01L27/148 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： Nonvolatile memory cells and methods of forming the same are provided, the methods including forming a first conductor at a first height above a substrate; forming a first pillar-shaped semiconductor element above the first conductor, wherein the first pillar-shaped semiconductor element comprises a first heavily doped layer of a first conductivity type, a second lightly doped layer above and in contact with the first heavily doped layer, and a third heavily doped layer of a second conductivity type above and in contact with the second lightly doped layer, the second conductivity type opposite the first conductivity type; forming a first dielectric antifuse above the third heavily doped layer of the first pillar-shaped semiconductor element; and forming a second conductor above the first dielectric antifuse.
摘要翻译：提供了非易失存储器单元及其形成方法，所述方法包括在衬底上方的第一高度处形成第一导体; 在所述第一导体上形成第一柱状半导体元件，其中所述第一柱状半导体元件包括第一导电类型的第一重掺杂层，在所述第一重掺杂层上方并与其接触的第二轻掺杂层，以及第二导电类型的第三重掺杂层在第二轻掺杂层上方并与第二轻掺杂层接触，第二导电类型与第一导电类型相反; 在所述第一柱状半导体元件的所述第三重掺杂层的上方形成第一介电反熔丝; 以及在所述第一介电反熔丝之上形成第二导体。

8. 发明授权

US07994064B2 Selective etch for damage at exfoliated surface 有权
标题翻译：选择性蚀刻在剥离表面的损伤
公开(公告)号：US07994064B2
公开(公告)日：2011-08-09
申请号：US12484271
申请日：2009-06-15
申请人： Mark H. Clark , S. Brad Herner , Mohamed M. Hilali
发明人： Mark H. Clark , S. Brad Herner , Mohamed M. Hilali
IPC分类号： H01L21/302
CPC分类号： H01L21/30604 , H01L21/76254 , H01L31/028 , H01L31/068 , H01L31/1892 , Y02E10/547
摘要： Ions are implanted into a silicon donor body, defining a cleave plane. A first surface of the donor body is affixed to a receiver element, and a lamina is exfoliated at the cleave plane, creating a second surface of the lamina. There is damaged silicon at the second surface, which will compromise the efficiency of a photovoltaic cell formed from the lamina. A selective etchant, having an etch rate which is positively correlated with the concentration of structural defects in silicon, is used to remove the damaged silicon at the second surface, while removing very little of the relatively undamaged lamina.
摘要翻译：离子被植入到硅供体体内，限定了一个解理面。供体主体的第一表面固定在接收元件上，并且在分裂面上剥离薄片，形成薄片的第二表面。在第二表面有损坏的硅，这将损害由薄片形成的光伏电池的效率。使用具有与硅中的结构缺陷的浓度正相关的蚀刻速率的选择性蚀刻剂来除去第二表面处的损坏的硅，同时去除非常少的相对未损伤的层。

9. 发明申请

US20110049466A1 LARGE ARRAY OF UPWARD POINTING P-I-N DIODES HAVING LARGE AND UNIFORM CURRENT 有权
标题翻译：指向具有大电流和均匀电流的上行P-I-N二极管的大阵列
公开(公告)号：US20110049466A1
公开(公告)日：2011-03-03
申请号：US12940251
申请日：2010-11-05
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： H01L47/00 , B82Y30/00
CPC分类号： H01L45/122 , B82Y10/00 , G11C13/0007 , G11C17/16 , G11C2213/16 , G11C2213/32 , G11C2213/71 , H01L27/1021 , H01L27/24 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/149 , H01L45/16 , Y10S977/742 , Y10S977/842
摘要： A memory is provided that includes a first memory level having a plurality of memory cells. Each memory cell includes a vertically oriented p-i-n diode including a bottom heavily doped p-type region, a middle intrinsic or lightly doped region, and a top heavily doped n-type region. When a voltage between about 1.5 volts and about 3.0 volts is applied across each p-i-n diode, a current of at least 1.5 microamps flows through 99 percent of the p-i-n diodes. Numerous other aspects are also provided.
摘要翻译：提供了包括具有多个存储器单元的第一存储器级的存储器。每个存储单元包括垂直取向的p-i-n二极管，其包括底部重掺杂p型区域，中间固有或轻掺杂区域和顶部重掺杂n型区域。当在每个p-i-n二极管之间施加约1.5伏和约3.0伏之间的电压时，至少1.5微安的电流流过99％的p-i-n二极管。还提供了许多其他方面。

10. 发明申请

US20110036397A1 INTERMETAL STACK FRO USE IN PHOTOVOLTAIC DEVICE 失效
标题翻译： INTERMETAL STACK FRO在光电器件中的使用
公开(公告)号：US20110036397A1
公开(公告)日：2011-02-17
申请号：US12540463
申请日：2009-08-13
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： H01L31/00 , H01L31/18
CPC分类号： H01L31/1896 , H01L31/022425 , H01L31/03921 , H01L31/072 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A donor silicon wafer may be bonded to a substrate and a lamina cleaved from the donor wafer. A photovoltaic cell may be formed from the lamina bonded to the substrate. An intermetal stack is described that is optimized for use in such a cell. The intermetal stack may include a titanium layer in contact with the lamina, which reacts to form titanium silicide, a non-reactive barrier layer to check the silicide reaction, a low-resistance layer, and an adhesion layer to help adhesion to the receiver element.
摘要翻译：供体硅晶片可以结合到基底和从施主晶片分离的薄片。可以从结合到衬底的薄片形成光伏电池。描述了优化用于这种电池的金属间堆叠。金属间堆叠可以包括与层接触的钛层，其与反应形成硅化钛，用于检查硅化物反应的非反应性阻挡层，低电阻层和粘合层以帮助粘附到接收器元件。

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