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1. 发明授权

US08633119B2 Methods for manufacturing high dielectric constant films 失效
公开(公告)号：US08633119B2
公开(公告)日：2014-01-21
申请号：US13189982
申请日：2011-07-25
申请人： Tatsuya E. Sato , Maitreyee Mahajani
发明人： Tatsuya E. Sato , Maitreyee Mahajani
IPC分类号： H01L21/314
CPC分类号： H01L21/0228 , H01L21/02046 , H01L21/02052 , H01L21/02181 , H01L21/02301 , H01L21/28088 , H01L21/28194 , H01L21/324 , H01L21/823857 , H01L29/4966 , H01L29/517 , H01L29/78
摘要： Provided are methods for depositing a high-k dielectric film on a substrate. The methods comprise annealing a substrate after cleaning the surface to create dangling bonds and depositing the high-k dielectric film on the annealed surface.

2. 发明申请

US20130122697A1 Doping aluminum in tantalum silicide 有权
公开(公告)号：US20130122697A1
公开(公告)日：2013-05-16
申请号：US13296715
申请日：2011-11-15
申请人： Xinliang Lu , Seshadri Ganguli , Michael S. Chen , Atif Noori , Shih Chung Chen , Maitreyee Mahajani , Mei Chang
发明人： Xinliang Lu , Seshadri Ganguli , Michael S. Chen , Atif Noori , Shih Chung Chen , Maitreyee Mahajani , Mei Chang
IPC分类号： H01L21/28 , H01B1/02
CPC分类号： H01L21/28088 , H01L29/4966
摘要： Provided are methods of providing aluminum-doped TaSix films. Doping TaSix films allows for the tuning of the work function value to make the TaSix film better suited as an N-metal for NMOS applications. One such method relates to soaking a TaSix film with an aluminum-containing compound. Another method relates to depositing a TaSix film, soaking with an aluminum-containing compound, and repeating for a thicker film. A third method relates to depositing an aluminum-doped TaSix film using tantalum, aluminum and silicon precursors.

3. 发明授权

US08383478B2 High-density nonvolatile memory and methods of making the same 有权
标题翻译：高密度非易失性存储器及其制作方法
公开(公告)号：US08383478B2
公开(公告)日：2013-02-26
申请号：US13195518
申请日：2011-08-01
申请人： Scott Brad Herner , Maitreyee Mahajani
发明人： Scott Brad Herner , Maitreyee Mahajani
IPC分类号： H01L21/336
CPC分类号： G11C5/02 , H01L21/8238 , H01L23/48 , H01L27/1021 , H01L27/148 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： Nonvolatile memory cells and methods of forming the same are provided, the methods including forming a first conductor at a first height above a substrate; forming a first pillar-shaped semiconductor element above the first conductor, wherein the first pillar-shaped semiconductor element comprises a first heavily doped layer of a first conductivity type, a second lightly doped layer above and in contact with the first heavily doped layer, and a third heavily doped layer of a second conductivity type above and in contact with the second lightly doped layer, the second conductivity type opposite the first conductivity type; forming a first dielectric antifuse above the third heavily doped layer of the first pillar-shaped semiconductor element; and forming a second conductor above the first dielectric antifuse.
摘要翻译：提供了非易失存储器单元及其形成方法，所述方法包括在衬底上方的第一高度处形成第一导体; 在所述第一导体上形成第一柱状半导体元件，其中所述第一柱状半导体元件包括第一导电类型的第一重掺杂层，在所述第一重掺杂层上方并与其接触的第二轻掺杂层，以及第二导电类型的第三重掺杂层在第二轻掺杂层上方并与第二轻掺杂层接触，第二导电类型与第一导电类型相反; 在所述第一柱状半导体元件的所述第三重掺杂层的上方形成第一介电反熔丝; 以及在所述第一介电反熔丝之上形成第二导体。

4. 发明申请

US20110021019A1 METHOD FOR FORMING DOPED POLYSILICON VIA CONNECTING POLYSILICON LAYERS 有权
标题翻译：通过连接多晶硅层形成掺杂多晶硅的方法
公开(公告)号：US20110021019A1
公开(公告)日：2011-01-27
申请号：US12897696
申请日：2010-10-04
申请人： Michael W. Konevecki , Usha Raghuram , Maitreyee Mahajani , Sucheta Nallamothu , Andrew J. Walker , Tanmay Kumar
发明人： Michael W. Konevecki , Usha Raghuram , Maitreyee Mahajani , Sucheta Nallamothu , Andrew J. Walker , Tanmay Kumar
IPC分类号： H01L21/768
CPC分类号： H01L27/12 , H01L21/28282 , H01L21/84 , H01L23/535 , H01L27/0688 , H01L27/115 , H01L27/11521 , H01L27/11551 , H01L27/11568 , H01L27/11578 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.
摘要翻译：本发明提供了连接在不同高度形成的导电多晶硅层的多晶硅通孔。多晶硅通孔有利地用于电荷存储晶体管的单片三维存储器阵列中。根据本发明的多晶硅通孔可以用于例如将电荷存储晶体管存储单元的第一器件电平的沟道层连接到形成在第一器件电平之上的这样的单元的第二器件层的沟道层。类似地，根据本发明的通孔可用于将电荷存储晶体管存储单元的第一器件电平的字线连接到这种单元的第二器件层的沟道层。

5. 发明授权

US07798096B2 Plasma, UV and ion/neutral assisted ALD or CVD in a batch tool 有权
标题翻译：等离子体，紫外线和离子/中性辅助ALD或CVD在批量工具中
公开(公告)号：US07798096B2
公开(公告)日：2010-09-21
申请号：US11381970
申请日：2006-05-05
申请人： Maitreyee Mahajani , Joseph Yudovsky , Brendan McDougall
发明人： Maitreyee Mahajani , Joseph Yudovsky , Brendan McDougall
IPC分类号： C23C16/00
CPC分类号： H01J37/32009 , C23C16/45508 , C23C16/45574 , C23C16/4583 , C23C16/46 , C23C16/509
摘要： A batch processing chamber includes a chamber housing, a substrate boat for containing a batch of substrates in a process region, and an excitation assembly for exciting species of a processing gas. The excitation assembly is positioned within the chamber housing and may include plasma, UV, or ion assistance.
摘要翻译：批处理室包括：室壳体，用于在处理区域中容纳一批衬底的衬底舟和用于激发加工气体种类的激发组件。激发组件定位在腔室内，并且可以包括等离子体，UV或离子辅助。

6. 发明申请

US20100227061A1 LOW TEMPERATURE ALD Si02 有权
标题翻译：低温ALD Si02
公开(公告)号：US20100227061A1
公开(公告)日：2010-09-09
申请号：US12788131
申请日：2010-05-26
申请人： Maitreyee Mahajani , Yi-Chiau Huang , Brendan McDougall
发明人： Maitreyee Mahajani , Yi-Chiau Huang , Brendan McDougall
IPC分类号： C23C16/40
CPC分类号： C23C16/402 , C23C16/45534
摘要： The present invention generally comprises a silicon dioxide atomic layer deposition method. By providing pyridine as a catalyst, water may be utilized as the oxidization source while depositing at a low temperature. Prior to exposing the substrate to the water, the substrate may be exposed to a pyridine soak process. Additionally, the water may be co-flowed to the chamber with the pyridine through separate conduits to reduce interaction prior to entering the chamber. Alternatively, the pyridine may be co-flowed with a silicon precursor that does not react with pyridine.
摘要翻译：本发明通常包括二氧化硅原子层沉积方法。通过提供吡啶作为催化剂，可以在低温下沉积时使用水作为氧化源。在将基底暴露于水之前，可以将底物暴露于吡啶浸泡过程。此外，水可以通过单独的导管与吡啶共同流到室中，以减少进入室之前的相互作用。或者，吡啶可以与不与吡啶反应的硅前体共流。

7. 发明申请

US20090261343A1 HIGH-DENSITY NONVOLATILE MEMORY AND METHODS OF MAKING THE SAME 有权
标题翻译：高密度非易失性存储器及其制造方法
公开(公告)号：US20090261343A1
公开(公告)日：2009-10-22
申请号：US12477216
申请日：2009-06-03
申请人： S. Brad Herner , Maitreyee Mahajani
发明人： S. Brad Herner , Maitreyee Mahajani
IPC分类号： H01L29/04 , H01L21/20
CPC分类号： G11C5/02 , H01L21/8238 , H01L23/48 , H01L27/1021 , H01L27/148 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： Nonvolatile memory cells and methods of forming the same are provided, the methods including forming a first conductor at a first height above a substrate; forming a first pillar-shaped semiconductor element above the first conductor, wherein the first pillar-shaped semiconductor element comprises a first heavily doped layer of a first conductivity type, a second lightly doped layer above and in contact with the first heavily doped layer, and a third heavily doped layer of a second conductivity type above and in contact with the second lightly doped layer, the second conductivity type opposite the first conductivity type; forming a first dielectric antifuse above the third heavily doped layer of the first pillar-shaped semiconductor element; and forming a second conductor above the first dielectric antifuse.
摘要翻译：提供了非易失存储器单元及其形成方法，所述方法包括在衬底上方的第一高度处形成第一导体; 在所述第一导体上形成第一柱状半导体元件，其中所述第一柱状半导体元件包括第一导电类型的第一重掺杂层，在所述第一重掺杂层上方并与其接触的第二轻掺杂层，以及第二导电类型的第三重掺杂层在第二轻掺杂层上方并与第二轻掺杂层接触，第二导电类型与第一导电类型相反; 在所述第一柱状半导体元件的所述第三重掺杂层的上方形成第一介电反熔丝; 以及在所述第一介电反熔丝之上形成第二导体。

8. 发明授权

US07495337B2 Dual-gate device and method 有权
标题翻译：双栅极器件及方法
公开(公告)号：US07495337B2
公开(公告)日：2009-02-24
申请号：US11671859
申请日：2007-02-06
申请人： Andrew J. Walker , Maitreyee Mahajani
发明人： Andrew J. Walker , Maitreyee Mahajani
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L27/1203 , G11C16/0483 , H01L21/84 , H01L27/115 , H01L27/11517 , H01L27/11568 , H01L29/4908 , H01L29/66742 , H01L29/78645 , H01L29/78648 , Y10S438/951
摘要： A dual-gate device is formed over and insulated from a semiconductor substrate which may include additional functional circuits that can be interconnected to the dual-gate device. The dual-gate device includes two semiconductor devices formed on opposite surfaces of a common active semiconductor region which is provided a thickness and material sufficient to isolate the semiconductor devices from electrostatically interacting. In one embodiment, one of the semiconductor devices includes a charge storing layer, such as an ONO layer. Such a dual-gate device is suitable for use in a non-volatile memory array.
摘要翻译：双栅极器件形成在半导体衬底上并与半导体衬底绝缘，半导体衬底可以包括可以互连到双栅极器件的附加功能电路。双栅极器件包括形成在公共有源半导体区域的相对表面上的两个半导体器件，其提供足以将半导体器件与静电相互作用隔离的厚度和材料。在一个实施例中，半导体器件之一包括诸如ONO层的电荷存储层。这种双栅极器件适用于非易失性存储器阵列。

9. 发明申请

US20080113096A1 METHOD OF DEPOSITING CATALYST ASSISTED SILICATES OF HIGH-K MATERIALS 有权
标题翻译：沉积催化剂辅助高K材料的硅酸盐的方法
公开(公告)号：US20080113096A1
公开(公告)日：2008-05-15
申请号：US11559486
申请日：2006-11-14
申请人： MAITREYEE MAHAJANI
发明人： MAITREYEE MAHAJANI
IPC分类号： C23C16/06
CPC分类号： C23C16/45546 , C23C16/401 , C23C16/45525 , C23C16/45534
摘要： A high-k silicate atomic layer deposition method is disclosed. To produce a hafnium silicate layer, a substrate may be exposed to a pulse of a hafnium precursor, a pulse of an oxidizer, a pulse of a silicon precursor, and a pulse of another oxidizer. A catalyst may additionally be co-flowed with one or more reactants into the chamber through a separate inlet. Alternatively, the catalyst may be flowed to the chamber before the reactant is introduced in a soaking procedure. By either co-flowing the catalyst through separate inlets or by performing a catalyst soak, hafnium silicate formation may proceed at a fast rate and/or at a low temperature.
摘要翻译：公开了一种高k硅酸盐原子层沉积方法。为了生产硅酸铪层，可以将衬底暴露于铪前体的脉冲，氧化剂的脉冲，硅前体的脉冲和另一氧化剂的脉冲。另外可以通过单独的入口将催化剂与一种或多种反应物共同流入室中。或者，在反应物以浸泡方法引入之前，催化剂可以流到室。通过使催化剂通过单独的入口共同流动或通过进行催化剂浸泡，可以以快速速率和/或低温进行硅酸铪形成。

10. 发明申请

US20070126033A1 DUAL-GATE DEVICE AND METHOD 有权
标题翻译：双门装置和方法
公开(公告)号：US20070126033A1
公开(公告)日：2007-06-07
申请号：US11671859
申请日：2007-02-06
申请人： Andrew Walker , Maitreyee Mahajani
发明人： Andrew Walker , Maitreyee Mahajani
IPC分类号： H01L29/768
CPC分类号： H01L27/1203 , G11C16/0483 , H01L21/84 , H01L27/115 , H01L27/11517 , H01L27/11568 , H01L29/4908 , H01L29/66742 , H01L29/78645 , H01L29/78648 , Y10S438/951
摘要： A dual-gate device is formed over and insulated from a semiconductor substrate which may include additional functional circuits that can be interconnected to the dual-gate device. The dual-gate device includes two semiconductor devices formed on opposite surfaces of a common active semiconductor region which is provided a thickness and material sufficient to isolate the semiconductor devices from electrostatically interacting. In one embodiment, one of the semiconductor devices includes a charge storing layer, such as an ONO layer. Such a dual-gate device is suitable for use in a non-volatile memory array.
摘要翻译：双栅极器件形成在半导体衬底上并与半导体衬底绝缘，半导体衬底可以包括可以互连到双栅极器件的附加功能电路。双栅极器件包括形成在公共有源半导体区域的相对表面上的两个半导体器件，其提供足以将半导体器件与静电相互作用隔离的厚度和材料。在一个实施例中，半导体器件之一包括诸如ONO层的电荷存储层。这种双栅极器件适用于非易失性存储器阵列。

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