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1. 发明授权

US09070801B2 Method to texture a lamina surface within a photovoltaic cell 有权
标题翻译：纹理光伏电池内薄片表面的方法
公开(公告)号：US09070801B2
公开(公告)日：2015-06-30
申请号：US13446051
申请日：2012-04-13
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： H01L21/00 , H01L31/0236 , H01L31/028 , H01L31/0392 , H01L31/18
CPC分类号： H01L31/0236 , H01L31/02363 , H01L31/028 , H01L31/03921 , H01L31/1804 , H01L31/1892 , Y02E10/547 , Y02E10/548 , Y02P70/521
摘要： It is advantageous to create texture at the surface of a photovoltaic cell to reduce reflection and increase travel length of light within the cell. A method is disclosed to create texture at the surface of a silicon body by reacting a silicide-forming metal at the surface, where the silicide-silicon interface is non-planar, then stripping the silicide, leaving behind a textured surface. Depending on the metal and the conditions of silicide formation, the resulting surface may be faceted. The peak-to-valley height of this texturing will generally be between about 300 and about 5000 angstroms, which is well-suited for use in photovoltaic cells comprising a thin silicon lamina.
摘要翻译：有利的是在光伏电池的表面处产生纹理以减少反射并增加电池内的光的行进长度。公开了一种通过使表面处的硅化物形成金属（其中硅化物 - 硅界面是非平面的）反应然后剥离硅化物，留下纹理表面来在硅体的表面上产生纹理的方法。取决于金属和硅化物形成的条件，所得到的表面可以是刻面的。该纹理的峰谷高度通常在约300至约5000埃之间，这非常适用于包含薄硅层的光伏电池。

2. 发明授权

US08987119B2 Pillar devices and methods of making thereof 有权
公开(公告)号：US08987119B2
公开(公告)日：2015-03-24
申请号：US13026381
申请日：2011-02-14
申请人： Vance Dunton , S. Brad Herner , Paul Wai Kie Poon , Chuanbin Pan , Michael Chan , Michael Konevecki , Usha Raghuram
发明人： Vance Dunton , S. Brad Herner , Paul Wai Kie Poon , Chuanbin Pan , Michael Chan , Michael Konevecki , Usha Raghuram
IPC分类号： H01L21/36 , H01L27/102 , H01L29/861 , H01L29/868
CPC分类号： H01L27/1021 , H01L29/8613 , H01L29/8615 , H01L29/868
摘要： A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer. The second conductivity type second portions of the second semiconductor layer remain in upper portions of the plurality of openings in the insulating layer to form a plurality of pillar shaped diodes in the plurality of openings.

3. 发明授权

US08575719B2 Silicon nitride antifuse for use in diode-antifuse memory arrays 有权
标题翻译：用于二极管 - 反熔丝存储器阵列的氮化硅反熔丝
公开(公告)号：US08575719B2
公开(公告)日：2013-11-05
申请号：US10610804
申请日：2003-06-30
申请人： Mark G. Johnson , N. Johan Knall , S. Brad Herner
发明人： Mark G. Johnson , N. Johan Knall , S. Brad Herner
IPC分类号： H01L23/52 , H01L29/04 , H01L29/10 , H01L31/036
CPC分类号： H01L27/0688 , G11C16/0466 , H01L21/822 , H01L21/8221 , H01L27/101 , H01L27/1021
摘要： Silicon nitride antifuses can be advantageously used in memory arrays employing diode-antifuse cells. Silicon nitride antifuses can be ruptured faster and at a lower breakdown field than antifuses formed of other materials, such as silicon dioxide. Examples are given of monolithic three dimensional memory arrays using silicon nitride antifuses with memory cells disposed in rail-stacks and pillars, and including PN and Schottky diodes. Pairing a silicon nitride antifuse with a low-density, high-resistivity conductor gives even better device performance.
摘要翻译：氮化硅反熔丝可以有利地用于采用二极管 - 反熔丝电池的存储器阵列中。氮化硅反熔丝可以比其它材料（例如二氧化硅）形成的反熔丝更快地破裂场破裂。给出了使用具有设置在轨道堆叠和柱中的存储器单元，并且包括PN和肖特基二极管的氮化硅反熔丝的单片三维存储器阵列的示例。将氮化硅反熔丝与低密度，高电阻导体配对可提供更好的器件性能。

4. 发明授权

US08349663B2 Vertical diode based memory cells having a lowered programming voltage and methods of forming the same 有权
标题翻译：具有降低的编程电压的基于垂直二极管的存储单元及其形成方法
公开(公告)号：US08349663B2
公开(公告)日：2013-01-08
申请号：US11864848
申请日：2007-09-28
申请人： S. Brad Herner , Tanmay Kumar
发明人： S. Brad Herner , Tanmay Kumar
IPC分类号： H01L21/82
CPC分类号： H01L27/1021 , G11C17/16 , H01L23/5252 , H01L29/868 , H01L2924/0002 , H01L2924/00
摘要： In a first aspect, a method for forming a non-volatile memory cell is provided. The method includes (1) forming a metal-insulator-metal (MIM) antifuse stack including (a) a first metal layer; (b) a silicon dioxide, oxynitride or silicon nitride antifuse layer formed above the first metal layer; and (c) a second metal layer formed above the antifuse layer. The method also includes (2) forming a contiguous p-i-n diode above the MIM antifuse stack, the contiguous p-i-n diode comprising deposited semiconductor material; (3) forming a layer of a silicide, silicide-germanide, or germanide in contact with the deposited semiconductor material; and (4) crystallizing the deposited semiconductor material in contact with the layer of silicide, silicide-germanide, or germanide. The memory cell comprises the contiguous p-i-n diode and the MIM antifuse stack. Other aspects are provided.
摘要翻译：在第一方面，提供了一种用于形成非易失性存储单元的方法。该方法包括（1）形成包括（a）第一金属层的金属 - 绝缘体 - 金属（MIM）反熔丝堆叠; （b）形成在第一金属层上方的二氧化硅，氧氮化物或氮化硅反熔层; 和（c）形成在反熔丝层之上的第二金属层。该方法还包括（2）在MIM反熔丝堆叠之上形成连续的p-i-n二极管，连续的p-i-n二极管包括沉积的半导体材料; （3）形成与沉积的半导体材料接触的硅化物层，硅化锗 - 锗化物或锗化物层; 和（4）使沉积的半导体材料与硅化物，硅化锗 - 锗化物或锗化物层接触。存储单元包括相邻的p-i-n二极管和MIM反熔丝堆叠。提供其他方面。

5. 发明申请

US20120205655A1 METHOD TO TEXTURE A LAMINA SURFACE WITHIN A PHOTOVOLTAIC CELL 有权
标题翻译：在光伏电池中纹理表面的方法
公开(公告)号：US20120205655A1
公开(公告)日：2012-08-16
申请号：US13446051
申请日：2012-04-13
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： H01L31/0376
CPC分类号： H01L31/0236 , H01L31/02363 , H01L31/028 , H01L31/03921 , H01L31/1804 , H01L31/1892 , Y02E10/547 , Y02E10/548 , Y02P70/521
摘要： It is advantageous to create texture at the surface of a photovoltaic cell to reduce reflection and increase travel length of light within the cell. A method is disclosed to create texture at the surface of a silicon body by reacting a silicide-forming metal at the surface, where the silicide-silicon interface is non-planar, then stripping the silicide, leaving behind a textured surface. Depending on the metal and the conditions of silicide formation, the resulting surface may be faceted. The peak-to-valley height of this texturing will generally be between about 300 and about 5000 angstroms, which is well-suited for use in photovoltaic cells comprising a thin silicon lamina.
摘要翻译：有利的是在光伏电池的表面处产生纹理以减少反射并增加电池内的光的行进长度。公开了一种通过使表面处的硅化物形成金属（其中硅化物 - 硅界面是非平面的）反应然后剥离硅化物，留下纹理表面来在硅体的表面上产生纹理的方法。取决于金属和硅化物形成的条件，所得到的表面可以是刻面的。该纹理的峰谷高度通常在约300至约5000埃之间，这非常适用于包含薄硅层的光伏电池。

6. 发明申请

US20120001296A1 P-I-N DIODE CRYSTALLIZED ADJACENT TO A SILICIDE IN SERIES WITH A DIELECTRIC MATERIAL 有权
标题翻译： P-I-N二极管与电介质材料系列中的二氧化硅结晶相结合
公开(公告)号：US20120001296A1
公开(公告)日：2012-01-05
申请号：US13229747
申请日：2011-09-11
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： H01L27/06
CPC分类号： H01L27/06 , G11C13/0069 , G11C17/16 , G11C2013/009 , G11C2213/33 , H01L23/5252 , H01L27/101 , H01L27/1021 , H01L2924/0002 , H01L2924/3011 , Y10S257/91 , H01L2924/00
摘要： A vertically oriented p-i-n diode is provided that includes semiconductor material crystallized adjacent a silicide, germanide, or silicide-germanide layer, and a dielectric material arranged electrically in series with the diode. The dielectric material has a dielectric constant greater than 8, and is adjacent a first metallic layer and a second metallic layer. Numerous other aspects are provided.
摘要翻译：提供了一种垂直取向的p-i-n二极管，其包括在硅化物，锗化物或硅化物 - 锗化物层附近结晶的半导体材料，以及与二极管串联设置的电介质材料。电介质材料的介电常数大于8，并且与第一金属层和第二金属层相邻。提供了许多其他方面。

7. 发明申请

US20110176352A1 NONVOLATILE MEMORY CELL OPERATING BY INCREASING ORDER IN POLYCRYSTALLINE SEMICONDUCTOR MATERIAL 有权
标题翻译：通过在多晶半导体材料中增加订单来操作非易失性存储器单元
公开(公告)号：US20110176352A1
公开(公告)日：2011-07-21
申请号：US13074509
申请日：2011-03-29
申请人： S. Brad Herner , Abhijit Bandyopadhyay
发明人： S. Brad Herner , Abhijit Bandyopadhyay
IPC分类号： G11C11/36
CPC分类号： G11C11/36 , G11C5/02 , G11C11/39 , G11C17/06 , G11C17/16 , H01L27/1021
摘要： A nonvolatile memory cell is described, the memory cell comprising a semiconductor diode. The semiconductor material making up the diode is formed with significant defect density, and allows very low current flow at a typical read voltage. Application of a programming voltage permanently changes the nature of the semiconductor material, resulting in an improved diode. The programmed diode allows much higher current flow, in some embodiments one, two or three orders of magnitude higher, at the same read voltage. The difference in current allows a programmed memory cell to be distinguished from an unprogrammed memory cell. Fabrication techniques to generate an advantageous unprogrammed defect density are described. The memory cell of the present invention can be formed in a monolithic three dimensional memory array, having multiple stacked memory levels formed above a single substrate.
摘要翻译：描述非易失性存储单元，存储单元包括半导体二极管。构成二极管的半导体材料形成有明显的缺陷密度，并且在典型的读取电压下允许非常低的电流流动。编程电压的应用永久地改变了半导体材料的性质，导致改进的二极管。在相同的读取电压下，编程的二极管允许更高的电流流动，在一些实施例中高一个，两个或三个数量级。电流差异允许将编程的存储器单元与未编程的存储器单元进行区分。描述了产生有利的未编程缺陷密度的制造技术。本发明的存储单元可以形成为在单个衬底上形成多个堆叠存储器级的单片三维存储器阵列。

8. 发明申请

US20110114913A1 HETEROJUNCTION DEVICE COMPRISING A SEMICONDUCTOR AND A RESISTIVITY-SWITCHING OXIDE OR NITRIDE 有权
标题翻译：包含半导体和电阻率切换氧化物或氮化物的异质结器件
公开(公告)号：US20110114913A1
公开(公告)日：2011-05-19
申请号：US13007812
申请日：2011-01-17
申请人： Tanmay Kumar , S. Brad Herner
发明人： Tanmay Kumar , S. Brad Herner
IPC分类号： H01L45/00 , H01L29/78
CPC分类号： H01L29/868 , H01L21/84 , H01L27/1021 , H01L27/2409 , H01L29/165 , H01L29/22 , H01L29/267 , H01L29/417 , H01L29/737 , H01L29/8615 , H01L45/04 , H01L45/1233 , H01L45/146
摘要： In the present invention, a metal oxide or nitride compound which is a wide-band-gap semiconductor abuts a silicon, germanium, or alloy of silicon and/or germanium of the opposite conductivity type to form a p-n heterojunction. This p-n heterojunction can be used to advantage in various devices. In preferred embodiments, one terminal of a vertically oriented p-i-n heterojunction diode is a metal oxide or nitride layer, while the rest of the diode is formed of a silicon or silicon-germanium resistor. For example, a diode may include a heavily doped n-type silicon region, an intrinsic silicon region, and a nickel oxide layer serving as the p-type terminal. Many of these metal oxides and nitrides exhibit resistivity-switching behavior, and such a heterojunction diode can be used in a nonvolatile memory cell, for example in a monolithic three dimensional memory array.
摘要翻译：在本发明中，作为宽带隙半导体的金属氧化物或氮化物化合物与相反导电型的硅和/或锗的硅，锗或合金相接触以形成p-n异质结。该p-n异质结可以用于各种装置中。在优选实施例中，垂直取向的p-i-n异质结二极管的一个端子是金属氧化物或氮化物层，而二极管的其余部分由硅或硅 - 锗电阻器形成。例如，二极管可以包括重掺杂的n型硅区，本征硅区和用作p型端的氧化镍层。这些金属氧化物和氮化物中的许多表现出电阻率切换行为，并且这种异质结二极管可以用在非易失性存储单元中，例如在单片三维存储器阵列中。

9. 发明授权

US07915095B2 Silicide-silicon oxide-semiconductor antifuse device and method of making 有权
标题翻译：硅化硅 - 氧化硅半导体反熔丝装置及其制造方法
公开(公告)号：US07915095B2
公开(公告)日：2011-03-29
申请号：US12656016
申请日：2010-01-13
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： H01L21/82
CPC分类号： H01L27/101 , H01L23/5252 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： An antifuse contains a first silicide layer, a grown silicon oxide antifuse layer on a first surface of the first silicide layer, and a first semiconductor layer having a first surface in contact with the antifuse layer.
摘要翻译：反熔丝包含第一硅化物层，在第一硅化物层的第一表面上生长的氧化硅反熔层，以及具有与反熔丝层接触的第一表面的第一半导体层。

10. 发明授权

US07906392B2 Pillar devices and methods of making thereof 有权
标题翻译：支柱装置及其制造方法
公开(公告)号：US07906392B2
公开(公告)日：2011-03-15
申请号：US12007781
申请日：2008-01-15
申请人： Vance Dunton , S. Brad Herner , Paul Wai Kie Poon , Chuanbin Pan , Michael Chan , Michael Konevecki , Usha Raghuram
发明人： Vance Dunton , S. Brad Herner , Paul Wai Kie Poon , Chuanbin Pan , Michael Chan , Michael Konevecki , Usha Raghuram
IPC分类号： H01L21/8242 , H01L21/8234 , H01L21/8222
CPC分类号： H01L27/1021 , H01L29/8613 , H01L29/8615 , H01L29/868
摘要： A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer. The second conductivity type second portions of the second semiconductor layer remain in upper portions of the plurality of openings in the insulating layer to form a plurality of pillar shaped diodes in the plurality of openings.
摘要翻译：制造半导体器件的方法包括提供包含多个开口的绝缘层，在绝缘层中的多个开口中并在绝缘层之上形成第一半导体层，以及去除第一半导体层的第一部分，第一半导体层的第一导电类型的第二部分保留在绝缘层中的多个开口的下部，并且绝缘层中的多个开口的上部保持未填充。该方法还包括在绝缘层中的多个开口的上部和绝缘层上形成第二半导体层，以及去除位于绝缘层之上的第二半导体层的第一部分。第二半导体层的第二导电类型的第二部分保留在绝缘层中的多个开口的上部，以在多个开口中形成多个柱状二极管。

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