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1. 发明授权

US08163593B2 Method of making a nonvolatile phase change memory cell having a reduced contact area 有权
标题翻译：制造具有减小的接触面积的非挥发性相变存储单元的方法
公开(公告)号：US08163593B2
公开(公告)日：2012-04-24
申请号：US11560792
申请日：2006-11-16
申请人： Usha Raghuram , S. Brad Herner
发明人： Usha Raghuram , S. Brad Herner
IPC分类号： H01L21/00
CPC分类号： H01L45/144 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1683 , H01L45/1691
摘要： A method is described to form a nonvolatile memory cell having a contact area between a phase-change material such as a chalcogenide and a heat source which is smaller than photolithographic limits. A conductive or semiconductor pillar is exposed at a dielectric surface and recessed by selective etch. A thin, conformal layer of a spacer material is deposited on the dielectric top surface, the pillar top surface, and the sidewalls of the recess, then removed from horizontal surfaces by anistropic etch, leaving a spacer on the sidewalls defining a reduced volume within the recess. The phase change material is deposited within the spacer, having a reduced contact area to the underlying conductive or semiconductor pillar.
摘要翻译：描述了一种形成非易失性存储单元的方法，所述非易失性存储单元具有诸如硫族化物的相变材料与小于光刻极限的热源之间的接触面积。导电或半导体柱在电介质表面露出并通过选择性蚀刻凹陷。间隔材料的薄的共形层被沉积在电介质顶表面，柱顶表面和凹槽的侧壁上，然后通过无功蚀刻从水平表面去除，在侧壁上留下间隔，限定内部减小的体积休息。相变材料沉积在间隔物内，具有减小的与下面的导电或半导体柱的接触面积。

2. 发明授权

US07728318B2 Nonvolatile phase change memory cell having a reduced contact area 有权
标题翻译：具有减小的接触面积的非挥发性相变存储器单元
公开(公告)号：US07728318B2
公开(公告)日：2010-06-01
申请号：US11560791
申请日：2006-11-16
申请人： Usha Raghuram , S. Brad Herner
发明人： Usha Raghuram , S. Brad Herner
IPC分类号： H01L29/02
CPC分类号： H01L45/06 , H01L27/2409 , H01L27/2481 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1683 , H01L45/1691
摘要： A nonvolatile memory cell having a contact area between a phase-change material such as a chalcogenide and a heat source which is smaller than photolithographic limits is described. To form this cell, a conductive or semiconductor pillar is exposed at a dielectric surface and recessed by selective etch. A thin, conformal layer of a spacer material is deposited on the dielectric top surface, the pillar top surface, and the sidewalls of the recess, then removed from horizontal surfaces by anistropic etch, leaving a spacer on the sidewalls defining a reduced volume within the recess. The phase change material is deposited within the spacer, having a reduced contact area to the underlying conductive or semiconductor pillar.
摘要翻译：描述了在诸如硫族化物的相变材料和小于光刻极限的热源之间具有接触面积的非易失性存储单元。为了形成该电池，导电或半导体柱在电介质表面露出并通过选择性蚀刻凹陷。间隔材料的薄的共形层被沉积在电介质顶表面，柱顶表面和凹槽的侧壁上，然后通过无功蚀刻从水平表面去除，在侧壁上留下间隔，限定内部减小的体积休息。相变材料沉积在间隔物内，具有减小的与下面的导电或半导体柱的接触面积。

3. 发明申请

US20090179310A1 Pillar devices and methods of making thereof 有权
标题翻译：支柱装置及其制造方法
公开(公告)号：US20090179310A1
公开(公告)日：2009-07-16
申请号：US12007781
申请日：2008-01-15
申请人： Vance Dunton , S. Brad Herner , Paul Wai Kie Poon , Chuanbin Pan , Michael Chan , Michael Konevecki , Usha Raghuram
发明人： Vance Dunton , S. Brad Herner , Paul Wai Kie Poon , Chuanbin Pan , Michael Chan , Michael Konevecki , Usha Raghuram
IPC分类号： H01L29/868 , H01L21/20
CPC分类号： H01L27/1021 , H01L29/8613 , H01L29/8615 , H01L29/868
摘要： A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer. The second conductivity type second portions of the second semiconductor layer remain in upper portions of the plurality of openings in the insulating layer to form a plurality of pillar shaped diodes in the plurality of openings.
摘要翻译：制造半导体器件的方法包括提供包含多个开口的绝缘层，在绝缘层中的多个开口中并在绝缘层之上形成第一半导体层，以及去除第一半导体层的第一部分，第一半导体层的第一导电类型的第二部分保留在绝缘层中的多个开口的下部，并且绝缘层中的多个开口的上部保持未填充。该方法还包括在绝缘层中的多个开口的上部和绝缘层上形成第二半导体层，以及去除位于绝缘层之上的第二半导体层的第一部分。第二半导体层的第二导电类型的第二部分保留在绝缘层中的多个开口的上部，以在多个开口中形成多个柱状二极管。

4. 发明申请

US20080119007A1 METHOD OF MAKING A NONVOLATILE PHASE CHANGE MEMORY CELL HAVING A REDUCED CONTACT AREA 有权
标题翻译：制造具有减少接触面积的非易失性相变记忆体的方法
公开(公告)号：US20080119007A1
公开(公告)日：2008-05-22
申请号：US11560792
申请日：2006-11-16
申请人： Usha Raghuram , S. Brad Herner
发明人： Usha Raghuram , S. Brad Herner
IPC分类号： H01L47/00
CPC分类号： H01L45/144 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1683 , H01L45/1691
摘要： A method is described to form a nonvolatile memory cell having a contact area between a phase-change material such as a chalcogenide and a heat source which is smaller than photolithographic limits. A conductive or semiconductor pillar is exposed at a dielectric surface and recessed by selective etch. A thin, conformal layer of a spacer material is deposited on the dielectric top surface, the pillar top surface, and the sidewalls of the recess, then removed from horizontal surfaces by anistropic etch, leaving a spacer on the sidewalls defining a reduced volume within the recess. The phase change material is deposited within the spacer, having a reduced contact area to the underlying conductive or semiconductor pillar.
摘要翻译：描述了一种形成非易失性存储单元的方法，所述非易失性存储单元具有诸如硫族化物的相变材料与小于光刻极限的热源之间的接触面积。导电或半导体柱在电介质表面露出并通过选择性蚀刻凹陷。间隔材料的薄的共形层被沉积在电介质顶表面，柱顶表面和凹槽的侧壁上，然后通过无功蚀刻从水平表面去除，在侧壁上留下间隔，限定内部减小的体积休息。相变材料沉积在间隔物内，具有减小的与下面的导电或半导体柱的接触面积。

5. 发明授权

US08987119B2 Pillar devices and methods of making thereof 有权
公开(公告)号：US08987119B2
公开(公告)日：2015-03-24
申请号：US13026381
申请日：2011-02-14
申请人： Vance Dunton , S. Brad Herner , Paul Wai Kie Poon , Chuanbin Pan , Michael Chan , Michael Konevecki , Usha Raghuram
发明人： Vance Dunton , S. Brad Herner , Paul Wai Kie Poon , Chuanbin Pan , Michael Chan , Michael Konevecki , Usha Raghuram
IPC分类号： H01L21/36 , H01L27/102 , H01L29/861 , H01L29/868
CPC分类号： H01L27/1021 , H01L29/8613 , H01L29/8615 , H01L29/868
摘要： A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer. The second conductivity type second portions of the second semiconductor layer remain in upper portions of the plurality of openings in the insulating layer to form a plurality of pillar shaped diodes in the plurality of openings.

6. 发明授权

US07906392B2 Pillar devices and methods of making thereof 有权
标题翻译：支柱装置及其制造方法
公开(公告)号：US07906392B2
公开(公告)日：2011-03-15
申请号：US12007781
申请日：2008-01-15
申请人： Vance Dunton , S. Brad Herner , Paul Wai Kie Poon , Chuanbin Pan , Michael Chan , Michael Konevecki , Usha Raghuram
发明人： Vance Dunton , S. Brad Herner , Paul Wai Kie Poon , Chuanbin Pan , Michael Chan , Michael Konevecki , Usha Raghuram
IPC分类号： H01L21/8242 , H01L21/8234 , H01L21/8222
CPC分类号： H01L27/1021 , H01L29/8613 , H01L29/8615 , H01L29/868
摘要： A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer. The second conductivity type second portions of the second semiconductor layer remain in upper portions of the plurality of openings in the insulating layer to form a plurality of pillar shaped diodes in the plurality of openings.
摘要翻译：制造半导体器件的方法包括提供包含多个开口的绝缘层，在绝缘层中的多个开口中并在绝缘层之上形成第一半导体层，以及去除第一半导体层的第一部分，第一半导体层的第一导电类型的第二部分保留在绝缘层中的多个开口的下部，并且绝缘层中的多个开口的上部保持未填充。该方法还包括在绝缘层中的多个开口的上部和绝缘层上形成第二半导体层，以及去除位于绝缘层之上的第二半导体层的第一部分。第二半导体层的第二导电类型的第二部分保留在绝缘层中的多个开口的上部，以在多个开口中形成多个柱状二极管。

7. 发明申请

US20110136326A1 PILLAR DEVICES AND METHODS OF MAKING THEREOF 有权
标题翻译：支柱装置及其制造方法
公开(公告)号：US20110136326A1
公开(公告)日：2011-06-09
申请号：US13026381
申请日：2011-02-14
申请人： Vance DUNTON , S. Brad Herner , Paul Wai Kie Poon , Chuanbin Pan , Michael Chan , Michael Konevecki , Usha Raghuram
发明人： Vance DUNTON , S. Brad Herner , Paul Wai Kie Poon , Chuanbin Pan , Michael Chan , Michael Konevecki , Usha Raghuram
IPC分类号： H01L21/36
CPC分类号： H01L27/1021 , H01L29/8613 , H01L29/8615 , H01L29/868
摘要： A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer. The second conductivity type second portions of the second semiconductor layer remain in upper portions of the plurality of openings in the insulating layer to form a plurality of pillar shaped diodes in the plurality of openings.
摘要翻译：制造半导体器件的方法包括提供包含多个开口的绝缘层，在绝缘层中的多个开口中并在绝缘层之上形成第一半导体层，以及去除第一半导体层的第一部分，第一半导体层的第一导电类型的第二部分保留在绝缘层中的多个开口的下部，并且绝缘层中的多个开口的上部保持未填充。该方法还包括在绝缘层中的多个开口的上部和绝缘层上形成第二半导体层，以及去除位于绝缘层之上的第二半导体层的第一部分。第二半导体层的第二导电类型的第二部分保留在绝缘层中的多个开口的上部，以在多个开口中形成多个柱状二极管。

8. 发明申请

US20080116441A1 NONVOLATILE PHASE CHANGE MEMORY CELL HAVING A REDUCED CONTACT AREA 有权
标题翻译：非易失性相变存储器单元，具有减少的接触面积
公开(公告)号：US20080116441A1
公开(公告)日：2008-05-22
申请号：US11560791
申请日：2006-11-16
申请人： Usha Raghuram , S. Brad Herner
发明人： Usha Raghuram , S. Brad Herner
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , H01L27/2409 , H01L27/2481 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1683 , H01L45/1691
摘要： A nonvolatile memory cell having a contact area between a phase-change material such as a chalcogenide and a heat source which is smaller than photolithographic limits is described. To form this cell, a conductive or semiconductor pillar is exposed at a dielectric surface and recessed by selective etch. A thin, conformal layer of a spacer material is deposited on the dielectric top surface, the pillar top surface, and the sidewalls of the recess, then removed from horizontal surfaces by anistropic etch, leaving a spacer on the sidewalls defining a reduced volume within the recess. The phase change material is deposited within the spacer, having a reduced contact area to the underlying conductive or semiconductor pillar.
摘要翻译：描述了在诸如硫族化物的相变材料和小于光刻极限的热源之间具有接触面积的非易失性存储单元。为了形成该电池，导电或半导体柱在电介质表面露出并通过选择性蚀刻凹陷。间隔材料的薄的共形层被沉积在电介质顶表面，柱顶表面和凹槽的侧壁上，然后通过无功蚀刻从水平表面去除，在侧壁上留下间隔，限定内部减小的体积休息。相变材料沉积在间隔物内，具有减小的与下面的导电或半导体柱的接触面积。

9. 发明授权

US08314477B2 Deposited semiconductor structure to minimize N-type dopant diffusion and method of making 有权
标题翻译：沉积的半导体结构使N型掺杂剂扩散最小化和制备方法
公开(公告)号：US08314477B2
公开(公告)日：2012-11-20
申请号：US13247723
申请日：2011-09-28
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： H01L21/02
CPC分类号： H01L45/08 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L29/161 , H01L29/165 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146
摘要： A memory cell is provided that includes a semiconductor pillar and a reversible state-change element coupled to the semiconductor pillar. The semiconductor pillar includes a heavily doped bottom region of a first conductivity type, a heavily doped top region of a second conductivity type, and a lightly doped or intrinsic middle region interposed between and contacting the top and bottom regions. The middle region comprises a first proportion of germanium, and either the top region or the bottom region comprises no germanium or comprises a second proportion of germanium less than the first proportion. The reversible state-change element includes a layer of a resistivity-switching metal oxide or nitride compound selected from the group consisting of NiO, Nb2O5, TiO2, HfO2, Al2O3, CoO, MgOx, CrO2, VO, BN, and AlN. Numerous other aspects are provided.
摘要翻译：提供了存储单元，其包括半导体柱和耦合到半导体柱的可逆状态变换元件。半导体柱包括第一导电类型的重掺杂底部区域，第二导电类型的重掺杂顶部区域，以及插入并接触顶部区域和底部区域之间的轻掺杂或固有中间区域。中间区域包括第一比例的锗，并且顶部区域或底部区域不包含锗，或者包括小于第一比例的第二比例的锗。可逆态变化元件包括选自NiO，Nb 2 O 5，TiO 2，HfO 2，Al 2 O 3，CoO，MgO x，CrO 2，VO，BN和AlN的电阻率切换金属氧化物或氮化物层。提供了许多其他方面。

10. 发明授权

US08243509B2 Nonvolatile memory cell operating by increasing order in polycrystalline semiconductor material 有权
标题翻译：非易失性存储单元通过增加多晶半导体材料的顺序来操作
公开(公告)号：US08243509B2
公开(公告)日：2012-08-14
申请号：US13074509
申请日：2011-03-29
申请人： S. Brad Herner , Abhijit Bandyopadhyay
发明人： S. Brad Herner , Abhijit Bandyopadhyay
IPC分类号： G11C11/36 , G11C11/34 , G11C11/00
CPC分类号： G11C11/36 , G11C5/02 , G11C11/39 , G11C17/06 , G11C17/16 , H01L27/1021
摘要： A nonvolatile memory cell is described, the memory cell comprising a semiconductor diode. The semiconductor material making up the diode is formed with significant defect density, and allows very low current flow at a typical read voltage. Application of a programming voltage permanently changes the nature of the semiconductor material, resulting in an improved diode. The programmed diode allows much higher current flow, in some embodiments one, two or three orders of magnitude higher, at the same read voltage. The difference in current allows a programmed memory cell to be distinguished from an unprogrammed memory cell. Fabrication techniques to generate an advantageous unprogrammed defect density are described. The memory cell of the present invention can be formed in a monolithic three dimensional memory array, having multiple stacked memory levels formed above a single substrate.
摘要翻译：描述非易失性存储单元，存储单元包括半导体二极管。构成二极管的半导体材料形成有明显的缺陷密度，并且在典型的读取电压下允许非常低的电流流动。编程电压的应用永久地改变了半导体材料的性质，导致改进的二极管。在相同的读取电压下，编程的二极管允许更高的电流流动，在一些实施例中高一个，两个或三个数量级。电流差异允许将编程的存储器单元与未编程的存储器单元进行区分。描述了产生有利的未编程缺陷密度的制造技术。本发明的存储单元可以形成为在单个衬底上形成多个堆叠存储器级的单片三维存储器阵列。

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