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1. 发明专利

JP2007194638A Nonvolatile memory device, and method of manufacturing same 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：JP2007194638A
公开(公告)日：2007-08-02
申请号：JP2007010593
申请日：2007-01-19
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： MOON JUNG-HO , KWON CHUL-SOON , YU JAE-MIN , PARK JAE-HYUN , JEONG YOUNG-CHEON , YOON IN-GU
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521 , H01L29/7885
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile memory device capable of operating more stably.
SOLUTION: The device comprises a source region formed in a semiconductor substrate, a gate insulating film formed so as to overlap with part of the source region, a floating gate having a structure for forming an electric field constantly in a region that overlaps with the source region and formed on the upper part of the gate insulating film, a control gate formed in an insulating state along one sidewall of the floating gate from the upper part of the floating gate, an insulating film between gates interposed between the floating gate and the control gate, and a drain region formed adjacent to the other side of the control gate.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供能够更稳定地操作的非易失性存储器件。解决方案：该器件包括形成在半导体衬底中的源极区域，形成为与源极区域的一部分重叠的栅极绝缘膜，具有用于在重叠的区域中恒定形成电场的结构的浮动栅极与源极区域形成并形成在栅极绝缘膜的上部;控制栅极，其从浮置栅极的上部沿着浮置栅极的一个侧壁形成绝缘状态;栅极之间的绝缘膜，位于浮置栅极之间; 和控制栅极，以及与控制栅极的另一侧相邻形成的漏极区域。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2007053362A Manufacture method of nonvolatile memory device 审中-公开
标题翻译：非易失性存储器件的制造方法
公开(公告)号：JP2007053362A
公开(公告)日：2007-03-01
申请号：JP2006217337
申请日：2006-08-09
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： JEONG YOUNG-CHEON , KWON CHUL-SOON , YU JAE-MIN , PARK ZAIGEN , RIM JI-WOON , YOON IN-GU
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/105 , H01L27/11526 , H01L27/11543 , H01L29/42324
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a split-gate nonvolatile memory device.
SOLUTION: A first gate insulating film and a first conductive film are formed on a substrate, and an oxide film pattern is formed by oxidizing the conductive film partially. A floating gate electrode is formed on the first gate insulating film through a process of partly etching the first conductive film by using the oxide film pattern as an etching mask. After a first silicon film is formed on all the surface of the substrate where the floating gate electrode is formed, a tunnel insulating film and a second gate insulating film are formed on the side of the floating gate electrode and a part of the surface of the substrate adjacent to the floating gate electrode respectively by oxidizing the first silicon film. A control gate electrode is formed on the tunnel insulating film and the second gate insulating film. A second silicon film is formed on all the surface of the substrate where the control gate electrode is formed, and the second silicon film is turned to a thermal oxide film.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供一种制造分离式非易失性存储装置的方法。解决方案：在基板上形成第一栅极绝缘膜和第一导电膜，并且部分地氧化导电膜形成氧化物膜图案。通过使用氧化膜图案作为蚀刻掩模，部分地蚀刻第一导电膜的工艺，在第一栅极绝缘膜上形成浮栅电极。在形成浮栅的衬底的所有表面上形成第一硅膜之后，在浮栅电极的一侧形成隧道绝缘膜和第二栅绝缘膜，通过氧化第一硅膜分别与浮置栅电极相邻的衬底。在隧道绝缘膜和第二栅极绝缘膜上形成控制栅电极。在形成控制栅极的基板的所有表面上形成第二硅膜，并将第二硅膜转变为热氧化膜。版权所有（C）2007，JPO＆INPIT

3. 发明专利

DE102004028425B4 Halbleiterbauelement mit einer Messstruktur und Verfahren zum Messen des Halbleiterbauelements unter Verwendung der Messstruktur 未知
公开(公告)号：DE102004028425B4
公开(公告)日：2016-08-04
申请号：DE102004028425
申请日：2004-06-02
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： PARK SANG-WOOK , YU JAE-MIN , KWON CHUL-SOON , KIM JIN-WOO , PARK JAE-HYUN , KIM YONG-HEE , LEE DON-WOO , KIM DAI-GEUN , KIM JOO-CHAN , KIM KOOK-MIN , RYU EUI-YOUL
IPC分类号： H01L21/66 , H01L21/027 , H01L21/822 , H01L23/544 , H01L27/04
摘要： Halbleiterbauelement mit – einer ersten Materialschicht (40) mit einem Chipgebiet, in dem ein integrierter Schaltkreis ausgebildet ist, und einem Anreißgebiet (20), welches das Chipgebiet umgibt, – einer Messstruktur (42), die in dem Anreißgebiet der ersten Materialschicht ausgebildet ist, wobei eine Oberflächenquerschnittsfläche der Messstruktur größer als eine Oberflächenquerschnittsfläche eines Strahlgebiets ist, in das Messstrahlen projiziert werden, und – einer Dummystruktur (46), die zur Reduzierung der Oberflächenquerschnittsfläche der Messstruktur in der Messstruktur ausgebildet ist, wobei die Oberflächenquerschnittsfläche der Dummystruktur 5% bis 15% der Oberflächenquerschnittsfläche des Strahlgebiets belegt.

4. 发明专利

DE102004028425A1 Semiconductor device e.g. integrated circuit comprises dummy pattern formed within measurement pattern so as to decrease empty space in surface cross-section of measurement pattern 未知
公开(公告)号：DE102004028425A1
公开(公告)日：2005-01-27
申请号：DE102004028425
申请日：2004-06-02
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： PARK SANG-WOOK , YU JAE-MIN , KWON CHUL-SOON , KIM JIN-WOO , PARK JAE-HYUN , KIM YONG-HEE , LEE DON-WOO , KIM DAI-GEUN , KIM JOO-CHAN , KIM KOOK-MIN , RYU EUI-YOUL
IPC分类号： H01L21/66 , H01L21/027 , H01L21/822 , H01L23/544 , H01L27/04
摘要： The semiconductor device comprises a measurement pattern (42) of fixed surface cross-section formed on scribed area of semiconductor substrate. A dummy pattern (46) for decreasing empty space in surface cross-section of measurement pattern, is formed within measurement pattern. An independent claim is also included for semiconductor device measurement method.

5. 发明专利

JP2005101600A Method of manufacturing flash memory cell having split-gate structure 审中-公开
标题翻译：制造具有分层结构的闪存存储单元的方法
公开(公告)号：JP2005101600A
公开(公告)日：2005-04-14
申请号：JP2004258975
申请日：2004-09-06
申请人： Samsung Electronics Co Ltd , 三星電子株式会社
发明人： LEE YONG-SUN , YU JAE-MIN , LEE DON-WOO , CHO JUNG-HUN , KEN TETSUJUN , MOON JUNG-HO , YOON IN-GU , PARK JAE-HYUN
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/336 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a flash memory cell having a split-gate structure.
SOLUTION: A sacrificial film is formed on a floating gate film formed on a semiconductor substrate and patterning is performed thereon, so that a sacrificial film pattern is formed which has an opening exposing a part of the floating gate film. A pattern of a gate interlayer insulating film is formed in the opening. After the sacrificial film pattern is removed, the floating gate film is etched using the pattern of the gate interlayer insulating film as an etching mask, so that a floating gate is formed under the pattern of the gate interlayer insulating film. Thereafter, a control gate overlapping one side of the floating gate is formed.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供一种制造具有分裂栅极结构的闪存单元的方法。解决方案：在形成在半导体衬底上的浮栅上形成牺牲膜，并对其进行图案化，从而形成具有暴露浮栅的一部分的开口的牺牲膜图案。在开口中形成栅极层间绝缘膜的图案。在除去牺牲膜图案之后，使用栅极层间绝缘膜的图案作为蚀刻掩模来蚀刻浮栅，使得在栅极层间绝缘膜的图案下方形成浮栅。此后，形成与浮动栅极重叠一侧的控制栅极。版权所有（C）2005，JPO＆NCIPI

6. 发明专利

JP2004111977A Manufacturing method of split gate type flash memory element 有权
公开(公告)号：JP2004111977A
公开(公告)日：2004-04-08
申请号：JP2003326903
申请日：2003-09-18
申请人： Samsung Electronics Co Ltd , 三星電子株式会社
发明人： YOON JUNG-LIM , YU JAE-MIN , MOON CHANG-ROK
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method for a split gate type flash memory element.
SOLUTION: Trench element separation membranes are formed on a semiconductor substrate, and a plurality of parallel first active regions are formed. Also, there are aligned sidewalls at the sidewalls of the trench element separation membranes on these regions, and gate insulating membrane patterns, conductive membrane patterns and hard mask patterns are formed laminated sequentially. The upper surfaces of the conductive membrane patterns are exposed by removing hard mask patterns at definite intervals along each of the first active regions. Membrane oxide patterns are formed on the exposed conductive membrane patterns, and the hard mask patterns are removed. Stray gate patterns which are ordered at definite intervals on each of the first active regions are formed by etching the conductive membrane patterns by using the membrane oxide patterns as etching masks. Tunnel membranes oxide are formed at the sidewalls of the patterns, and a plurality of control gate electrodes crossing the upper part of the first active regions are formed. The electrodes are positioned at the upper part of the stray gate patterns.
COPYRIGHT: (C)2004,JPO

7. 发明专利

JP2004104125A Manufacturing method of nonvolatile memory device 审中-公开
公开(公告)号：JP2004104125A
公开(公告)日：2004-04-02
申请号：JP2003309291
申请日：2003-09-01
申请人： Samsung Electronics Co Ltd , 三星電子株式会社
发明人： LEE CHANYUPU , CHO JINSHU , YU JAE-MIN , KIM HEIKYU , RYU JUNRETSU
IPC分类号： G11C7/00 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a split-gate nonvolatile memory device.
SOLUTION: This manufacturing method includes the following process: a lower conducting film is formed on a semiconductor substrate, and a lower sacrificial film pattern and an upper sacrificial film pattern, which are laminated, is sequentially formed on the lower conducting film; then a mask spacer is formed on the sidewalls of the sacrificial film patterns. The upper and lower sacrificial film patterns have an opening, to expose the lower conducting film. The upper sacrificial film pattern is preferably made of silicon oxide film or another material, having etching selectivity with respect to the lower sacrificial film pattern. When forming the upper sacrificial film pattern, it is preferable that the low-temperature chemical vapor deposition method be used. As a result, the height of the mask spacer can be increased without thermal budget, which prevents short circuits between a word line and a source line.
COPYRIGHT: (C)2004,JPO

8. 发明专利

JP2005101599A Method of manufacturing split-gate flash memory cell using spacer oxidation process 有权
标题翻译：使用间隔氧化过程制造分离闸门闪存存储器单元的方法
公开(公告)号：JP2005101599A
公开(公告)日：2005-04-14
申请号：JP2004258973
申请日：2004-09-06
申请人： Samsung Electronics Co Ltd , 三星電子株式会社
发明人： PARK JAE-HYUN , YU JAE-MIN , KEN TETSUJUN , YOON IN-GU , AHN EUNG-YUNG , MOON JUNG-HO , LEE YONG-SUN , JEON SUNG-YUNG
IPC分类号： H01L21/8247 , G11C11/42 , G11C16/04 , H01L21/28 , H01L21/336 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L29/66825 , G11C16/0425 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a split-gate flash memory cell using a spacer oxidation process.
SOLUTION: An antioxidant film is formed on a floating gate film, and an opening is formed in the anti-oxidant film so as to expose a part of the floating gate film. Thereafter, as an oxidized material film with an insulating property, a spacer is formed on the side wall of the opening, and the oxidation process is performed to form, in the opening, a gate interlayer oxide film pattern between a floating gate and a control gate while the spacer is oxidized.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供使用间隔物氧化工艺来制造分裂栅极闪存单元的方法。解决方案：在浮栅上形成抗氧化膜，在抗氧化膜中形成开口以露出浮栅的一部分。此后，作为具有绝缘性的氧化材料膜，在开口的侧壁上形成间隔物，并且进行氧化处理，以在开口中形成浮栅和控制层之间的栅极层间氧化膜图案而间隔物被氧化。版权所有（C）2005，JPO＆NCIPI

9. 发明专利

JP2005072578A Semiconductor device and manufacturing method therefor 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005072578A
公开(公告)日：2005-03-17
申请号：JP2004232482
申请日：2004-08-09
申请人： Samsung Electronics Co Ltd , 三星電子株式会社
发明人： YU JAE-MIN , LEE DON-WOO , KEN TETSUJUN , YOON IN-GU , LEE YONG-SUN , PARK JAE-HYUN , MOON JUNG-HO
IPC分类号： H01L27/10 , H01L21/336 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11539
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device, in which a memory device and logic equipment are merged.
SOLUTION: There are included a split gate electrode structure 130 formed on a memory cell region of a substrate 100, which is shared into the memory cell region and a logic region; a silicon oxide film 132 formed on front surfaces of the split gate electrode structure 130 and the substrate 100; a word line 150 contained on both side views of the split gate electrode structure 130, in which the silicon oxide film 132 is formed, with a lower part side view of the word line 150 projecting in the side direction, as compared with an upper part side view of the word line 150; and a logic gate pattern 152 which is formed in the logic region and has a smaller thickness, as compared with the channel length of the word line 150. The lower part side view of the word line 150 is projected, to increase the channel length.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种半导体器件，其中存储器件和逻辑器件被合并。解决方案：包括形成在基板100的存储单元区域上的分离栅极电极结构130，其分成存储单元区域和逻辑区域; 形成在分离栅电极结构130和基板100的前表面上的氧化硅膜132; 与形成有氧化硅膜132的分割栅极电极结构130的两侧视图中包含字线150的侧面侧的侧面侧的侧面方向上的字线150相比，字线150的侧视图; 以及形成在逻辑区域中并且具有比字线150的沟道长度更小的厚度的逻辑门图案152.字线150的下部侧视图被投影以增加通道长度。版权所有（C）2005，JPO＆NCIPI

10. 发明专利

JP2003188251A SEMICONDUCTOR DEVICE WITH TRENCH ELEMENT ISOLATION STRUCTURE, AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：JP2003188251A
公开(公告)日：2003-07-04
申请号：JP2002317537
申请日：2002-10-31
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： YOO SEUNG-HAN , YU JAE-MIN , PARK SANG-WOOK , RI TAISEI
IPC分类号： H01L21/76 , H01L21/762
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having a trench element isolation structure, and to provide a manufacturing method thereof. SOLUTION: This semiconductor device comprises a trench region 214, disposed in a predetermined region of an SOI substrate 206 wherein embedded insulating layer 202 and an upper silicon layer 204 are successively laminated on a support substrate 200, and an element isolation structure 228 filled into the trench region 214. The trench region 214 comprises a deep trench region 214d through the upper silicon layer 214 to the embedded insulating layer 202, and a shallow trench region 214s existing outside the deep trench region 214d. The element isolation structure 228 comprises a trench oxide film 216 and a trench liner 218, successively covering the bottom and the sidewall of the shallow trench region 214s, and an insulating film pattern 226 filling the inside of the trench region 214 covered with trench oxide film 216 and a trench liner 218. COPYRIGHT: (C)2003,JPO

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