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1. 发明专利

JP2005101599A Method of manufacturing split-gate flash memory cell using spacer oxidation process 有权
标题翻译：使用间隔氧化过程制造分离闸门闪存存储器单元的方法
公开(公告)号：JP2005101599A
公开(公告)日：2005-04-14
申请号：JP2004258973
申请日：2004-09-06
申请人： Samsung Electronics Co Ltd , 三星電子株式会社
发明人： PARK JAE-HYUN , YU JAE-MIN , KEN TETSUJUN , YOON IN-GU , AHN EUNG-YUNG , MOON JUNG-HO , LEE YONG-SUN , JEON SUNG-YUNG
IPC分类号： H01L21/8247 , G11C11/42 , G11C16/04 , H01L21/28 , H01L21/336 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L29/66825 , G11C16/0425 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a split-gate flash memory cell using a spacer oxidation process.
SOLUTION: An antioxidant film is formed on a floating gate film, and an opening is formed in the anti-oxidant film so as to expose a part of the floating gate film. Thereafter, as an oxidized material film with an insulating property, a spacer is formed on the side wall of the opening, and the oxidation process is performed to form, in the opening, a gate interlayer oxide film pattern between a floating gate and a control gate while the spacer is oxidized.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供使用间隔物氧化工艺来制造分裂栅极闪存单元的方法。解决方案：在浮栅上形成抗氧化膜，在抗氧化膜中形成开口以露出浮栅的一部分。此后，作为具有绝缘性的氧化材料膜，在开口的侧壁上形成间隔物，并且进行氧化处理，以在开口中形成浮栅和控制层之间的栅极层间氧化膜图案而间隔物被氧化。版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JP2005101600A Method of manufacturing flash memory cell having split-gate structure 审中-公开
标题翻译：制造具有分层结构的闪存存储单元的方法
公开(公告)号：JP2005101600A
公开(公告)日：2005-04-14
申请号：JP2004258975
申请日：2004-09-06
申请人： Samsung Electronics Co Ltd , 三星電子株式会社
发明人： LEE YONG-SUN , YU JAE-MIN , LEE DON-WOO , CHO JUNG-HUN , KEN TETSUJUN , MOON JUNG-HO , YOON IN-GU , PARK JAE-HYUN
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/336 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a flash memory cell having a split-gate structure.
SOLUTION: A sacrificial film is formed on a floating gate film formed on a semiconductor substrate and patterning is performed thereon, so that a sacrificial film pattern is formed which has an opening exposing a part of the floating gate film. A pattern of a gate interlayer insulating film is formed in the opening. After the sacrificial film pattern is removed, the floating gate film is etched using the pattern of the gate interlayer insulating film as an etching mask, so that a floating gate is formed under the pattern of the gate interlayer insulating film. Thereafter, a control gate overlapping one side of the floating gate is formed.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供一种制造具有分裂栅极结构的闪存单元的方法。解决方案：在形成在半导体衬底上的浮栅上形成牺牲膜，并对其进行图案化，从而形成具有暴露浮栅的一部分的开口的牺牲膜图案。在开口中形成栅极层间绝缘膜的图案。在除去牺牲膜图案之后，使用栅极层间绝缘膜的图案作为蚀刻掩模来蚀刻浮栅，使得在栅极层间绝缘膜的图案下方形成浮栅。此后，形成与浮动栅极重叠一侧的控制栅极。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2005159361A Method for manufacturing split gate type flash memory device 有权
标题翻译：用于制造分离栅型闪存存储器件的方法
公开(公告)号：JP2005159361A
公开(公告)日：2005-06-16
申请号：JP2004339296
申请日：2004-11-24
申请人： Samsung Electronics Co Ltd , 三星電子株式会社
发明人： KIM YONG-HEE , KEN TETSUJUN , KIN CHINU , KIM JOO-CHAN , KIM DAI-GEUN , RYU EUI YOUL
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L21/28273 , H01L27/11521 , H01L27/11536 , H01L29/66553 , H01L29/66825
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a split gate type flash memory device.
SOLUTION: The method comprises a step for forming a floating gate structure in a cell region of a semiconductor substrate having a peripheral circuit region divided into a high-voltage region and a low-voltage region and the cell region, a step for forming a first insulating film on the entire surface of a resulting specimen, a step for removing the first insulating film formed in the cell region, a step for forming a second insulating film in the cell region by forming an oxide film on the entire surface of the resulting specimen and forming a third insulating film in the peripheral circuit region, a step for removing the third insulating film formed in the low-voltage region, and a step for forming a control gate insulating film and a tunneling insulating film in the cell region by forming an oxide film on the entire surface of the resulting specimen, forming a high-voltage gate insulating film in the high-voltage region, and forming a low-voltage gate insulating film in the low-voltage region.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于制造分离式闸型闪存装置的方法。解决方案：该方法包括在具有被划分成高压区域和低电压区域的外围电路区域和单元区域的半导体衬底的单元区域中形成浮置栅极结构的步骤，用于在所得样品的整个表面上形成第一绝缘膜，除去形成在单元区域中的第一绝缘膜的步骤，通过在单元区域的整个表面上形成氧化物膜，在单元区域中形成第二绝缘膜的步骤在外围电路区域中形成第三绝缘膜，除去形成在低电压区域中的第三绝缘膜的步骤，以及在电池区域中形成控制栅极绝缘膜和隧道绝缘膜的步骤通过在所得样品的整个表面上形成氧化膜，在高电压区域形成高电压栅极绝缘膜，并在低v电压下形成低压栅极绝缘膜电压区。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2005072578A Semiconductor device and manufacturing method therefor 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005072578A
公开(公告)日：2005-03-17
申请号：JP2004232482
申请日：2004-08-09
申请人： Samsung Electronics Co Ltd , 三星電子株式会社
发明人： YU JAE-MIN , LEE DON-WOO , KEN TETSUJUN , YOON IN-GU , LEE YONG-SUN , PARK JAE-HYUN , MOON JUNG-HO
IPC分类号： H01L27/10 , H01L21/336 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11539
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device, in which a memory device and logic equipment are merged.
SOLUTION: There are included a split gate electrode structure 130 formed on a memory cell region of a substrate 100, which is shared into the memory cell region and a logic region; a silicon oxide film 132 formed on front surfaces of the split gate electrode structure 130 and the substrate 100; a word line 150 contained on both side views of the split gate electrode structure 130, in which the silicon oxide film 132 is formed, with a lower part side view of the word line 150 projecting in the side direction, as compared with an upper part side view of the word line 150; and a logic gate pattern 152 which is formed in the logic region and has a smaller thickness, as compared with the channel length of the word line 150. The lower part side view of the word line 150 is projected, to increase the channel length.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种半导体器件，其中存储器件和逻辑器件被合并。解决方案：包括形成在基板100的存储单元区域上的分离栅极电极结构130，其分成存储单元区域和逻辑区域; 形成在分离栅电极结构130和基板100的前表面上的氧化硅膜132; 与形成有氧化硅膜132的分割栅极电极结构130的两侧视图中包含字线150的侧面侧的侧面侧的侧面方向上的字线150相比，字线150的侧视图; 以及形成在逻辑区域中并且具有比字线150的沟道长度更小的厚度的逻辑门图案152.字线150的下部侧视图被投影以增加通道长度。版权所有（C）2005，JPO＆NCIPI

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