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1. 发明申请

US20060221702A1 Decoding circuit for non-binary groups of memory line drivers 有权
标题翻译：用于非二进制组的存储器线路驱动器的解码电路
公开(公告)号：US20060221702A1
公开(公告)日：2006-10-05
申请号：US11146952
申请日：2005-06-07
申请人： Roy Scheuerlein , Christopher Petti , Luca Fasoli
发明人： Roy Scheuerlein , Christopher Petti , Luca Fasoli
IPC分类号： G11C11/34
CPC分类号： G11C8/10 , G11C5/063 , G11C8/08 , G11C8/14
摘要： A decoding circuit for non-binary groups of memory line drivers is disclosed. In one embodiment, an integrated circuit is disclosed comprising a binary decoder and circuitry operative to perform a non-binary arithmetic operation, wherein a result of the non-binary arithmetic operation is provided as input to the binary decoder. In another embodiment, an integrated circuit is disclosed comprising a memory array comprising a plurality of array lines, a non-integral-power-of-two number of array line driver circuits, and control circuitry configured to select one of the array line driver circuits. The control circuitry can comprise a binary decoder and a pre-decoder portion that performs a non-binary arithmetic operation. The concepts described herein may be used alone or in combination.
摘要翻译：公开了一种用于非二进制组的存储器线驱动器的解码电路。在一个实施例中，公开了一种集成电路，其包括二进制解码器和用于执行非二进制算术运算的电路，其中非二进制算术运算的结果被提供作为二进制解码器的输入。在另一个实施例中，公开了一种集成电路，其包括存储器阵列，该存储器阵列包括多个阵列线，两个非整数倍数量的阵列线驱动器电路，以及控制电路，被配置为选择阵列线驱动电路之一。控制电路可以包括执行非二进制算术运算的二进制解码器和预解码器部分。本文所述的概念可以单独使用或组合使用。

2. 发明授权

US06807119B2 Array containing charge storage and dummy transistors and method of operating the array 有权
公开(公告)号：US06807119B2
公开(公告)日：2004-10-19
申请号：US10325737
申请日：2002-12-23
申请人： Luca Fasoli , Alper Ilkbahar , Roy Scheuerlein
发明人： Luca Fasoli , Alper Ilkbahar , Roy Scheuerlein
IPC分类号： G11C700
CPC分类号： G11C16/0416
摘要： An array of transistors includes a plurality of charge storage transistors and a plurality of dummy transistors interspersed with the plurality of charge storage transistors. Each of the plurality of the dummy transistors is made using the same photolithographic masking steps as each of the plurality of the charge storage transistors. A method of operating the array includes programming and/or erasing the array of transistors, and reading the plurality of charge storage transistors but not the plurality of dummy transistors.

3. 发明授权

US07132335B2 Semiconductor device with localized charge storage dielectric and method of making same 有权
标题翻译：具有局部电荷存储电介质的半导体器件及其制造方法
公开(公告)号：US07132335B2
公开(公告)日：2006-11-07
申请号：US10965763
申请日：2004-10-18
申请人： Alper Ilkbahar , Roy Scheuerlein , Andrew J. Walker , Luca Fasoli
发明人： Alper Ilkbahar , Roy Scheuerlein , Andrew J. Walker , Luca Fasoli
IPC分类号： H01L21/336
CPC分类号： H01L29/66833 , G11C16/0466 , G11C16/0491 , H01L21/28282 , H01L29/792
摘要： An array of transistors includes a plurality of transistors, a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction. Each transistor includes a source, a drain, a channel and a localized charge storage dielectric. A first transistor of the plurality of transistors and a second transistor of the plurality of transistors share a common source/drain. A first localized charge storage dielectric of the first transistor does not overlap the common source/drain and a second localized charge storage dielectric of the second transistor overlaps the common source/drain.
摘要翻译：晶体管阵列包括多个晶体管，沿第一方向延伸的多个字线和沿第二方向延伸的多个位线。每个晶体管包括源极，漏极，沟道和局部电荷存储电介质。所述多个晶体管中的第一晶体管和所述多个晶体管中的第二晶体管共用公共源极/漏极。第一晶体管的第一局部电荷存储电介质不与公共源极/漏极重叠，并且第二晶体管的第二局部电荷存储电介质与公共源极/漏极重叠。

4. 发明申请

US20050122779A1 Memory array incorporating memory cells arranged in NAND strings 有权
标题翻译：包含排列在NAND串中的存储单元的存储器阵列
公开(公告)号：US20050122779A1
公开(公告)日：2005-06-09
申请号：US10729843
申请日：2003-12-05
申请人： Luca Fasoli , Roy Scheuerlein , En-Hsing Chen , Sucheta Nallamothu , Maitreyee Mahajani , Andrew Walker
发明人： Luca Fasoli , Roy Scheuerlein , En-Hsing Chen , Sucheta Nallamothu , Maitreyee Mahajani , Andrew Walker
IPC分类号： G11C16/04
CPC分类号： G11C16/04
摘要： An exemplary NAND string memory array includes at least one plane of memory cells, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a plurality of series-connected NAND strings, and NAND strings including a series select device at each end thereof. Another exemplary NAND string memory array includes a group of more than four adjacent NAND strings within the same memory block each associated with a respective global bit line not shared by the other NAND string of the group. Another exemplary NAND string memory array includes NAND strings on identical pitch as their respective global bit lines.
摘要翻译：示例性NAND串存储器阵列包括至少一个存储器单元平面，所述存储器单元包括薄膜可修改的电导开关器件，并且哪些单元被布置在多个串联的NAND串中，以及包括每个的串联选择器件的NAND串结束。另一示例性的NAND串存储器阵列包括在相同存储器块内的多于四个相邻的NAND串的组，每组相关联的不同于该组的另一个NAND串的相应全局位线。另一示例性的NAND串存储器阵列包括与它们各自的全局位线相同的音调的NAND串。

5. 发明申请

US20070242511A1 NAND MEMORY ARRAY INCORPORATING CAPACITANCE BOOSTING OF CHANNEL REGIONS IN UNSELECTED MEMORY CELLS AND METHOD FOR OPERATION OF SAME 有权
标题翻译： NAND存储器阵列在不连续记忆细胞中的通道增加电容及其操作方法
公开(公告)号：US20070242511A1
公开(公告)日：2007-10-18
申请号：US11764793
申请日：2007-06-18
申请人： En-Hsing Chen , Andrew Walker , Roy Scheuerlein , Sucheta Nallamothu , Alper Ilkbahar , Luca Fasoli
发明人： En-Hsing Chen , Andrew Walker , Roy Scheuerlein , Sucheta Nallamothu , Alper Ilkbahar , Luca Fasoli
IPC分类号： G11C16/10
CPC分类号： G11C16/3418 , G11C11/5621 , G11C16/0483 , G11C16/10 , G11C16/3427 , H01L27/115 , H01L27/11568 , H01L27/1159
摘要： An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.
摘要翻译：示例性的NAND串存储器阵列提供半选择的存储器单元通道的电容性升压以减少半选择单元的程序干扰效应。为了减小升压电平的漏电流劣化的影响，采用较短持续时间的多个编程脉冲来限制这种漏电流可能降低未选择的NAND串中的电压的时间周期。此外，在每个NAND串的一端或两端的多个串联选择装置进一步确保了对于未选择的和选择的NAND串的这种选择装置的减少的泄漏。在某些示例性实施例中，存储器阵列包括具有电荷存储电介质的存储单元晶体管的串联连接的NAND串，并且包括形成在衬底上方的多于一个的存储单元平面。

6. 发明申请

US20070217263A1 MEMORY ARRAY INCORPORATING MEMORY CELLS ARRANGED IN NAND STRINGS 有权
标题翻译：记忆阵列并入记忆细胞安置在NAND条中
公开(公告)号：US20070217263A1
公开(公告)日：2007-09-20
申请号：US11751567
申请日：2007-05-21
申请人： Luca Fasoli , Roy Scheuerlein , En-Hsing Chen , Sucheta Nallamothu , Maitreyee Mahajani , Andrew Walker
发明人： Luca Fasoli , Roy Scheuerlein , En-Hsing Chen , Sucheta Nallamothu , Maitreyee Mahajani , Andrew Walker
IPC分类号： G11C16/04
CPC分类号： G11C16/04
摘要： An exemplary NAND string memory array includes at least one plane of memory cells, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a plurality of series-connected NAND strings, said NAND strings including a series select device at each end thereof. Another exemplary NAND string memory array includes a group of more than four adjacent NAND strings within the same memory block each associated with a respective global bit line not shared by the other NAND string of the group. Another exemplary NAND string memory array includes NAND strings on identical pitch as their respective global bit lines.
摘要翻译：示例性NAND串存储器阵列包括存储器单元的至少一个平面，所述存储器单元包括薄膜可修改的电导开关器件，并且哪些单元被布置在多个串联的NAND串中，所述NAND串包括每个的串联选择器件结束。另一示例性的NAND串存储器阵列包括在相同存储器块内的多于四个相邻的NAND串的组，每组相关联的不同于该组的另一个NAND串的相应全局位线。另一示例性的NAND串存储器阵列包括与它们各自的全局位线相同的音调的NAND串。

7. 发明申请

US20060221752A1 Integrated circuit memory array configuration including decoding compatibility with partial implementation of multiple memory layers 有权
标题翻译：集成电路存储器阵列配置包括与部分实现多个存储器层的解码兼容性
公开(公告)号：US20060221752A1
公开(公告)日：2006-10-05
申请号：US11095415
申请日：2005-03-31
申请人： Luca Fasoli , Roy Scheuerlein
发明人： Luca Fasoli , Roy Scheuerlein
IPC分类号： G11C8/00
CPC分类号： G11C8/14 , G11C5/02 , G11C5/063 , G11C7/18 , G11C29/808 , H01L27/101 , H01L27/105 , Y10T29/49002
摘要： An integrated circuit having a three-dimensional memory array provides for a given number of memory planes, but may be fabricated instead to include a lesser number of memory planes by omitting the masks and processing steps associated with the omitted memory planes, without changing any of the other fabrication masks for the other memory planes or for the remainder of the device, and without requiring routing or other configuration changes to the read or read/write path for the array. Control circuitry for selectively enabling certain layer selector circuits is configurable, and the layer selector circuits are suitably arranged, to couple a respective array line on an implemented memory layer to each respective I/O bus line irrespective of the number of implemented memory planes.
摘要翻译：具有三维存储器阵列的集成电路提供给定数量的存储器平面，但是可以通过省略与所省略的存储器平面相关联的掩模和处理步骤来替代地制造更少数量的存储器层，而不改变任何用于其他存储器平面或其余器件的其他制造掩模，并且不需要对阵列的读取或读取/写入路径进行路由或其他配置更改。用于选择性地启用某些层选择器电路的控制电路是可配置的，并且层选择器电路被适当地布置，以将实现的存储器层上的相应阵列线耦合到每个相应的I / O总线，而与所实现的存储器平面的数量无关。

8. 发明申请

US20060221728A1 Method and apparatus for incorporating block redundancy in a memory array 有权
公开(公告)号：US20060221728A1
公开(公告)日：2006-10-05
申请号：US11095907
申请日：2005-03-31
申请人： Luca Fasoli , Roy Scheuerlein
发明人： Luca Fasoli , Roy Scheuerlein
IPC分类号： G11C29/00
CPC分类号： G11C29/808 , G11C29/76 , G11C29/804 , G11C29/816
摘要： An integrated circuit memory array includes alternating first and second types of memory blocks, each memory block including respective array lines shared with a respective array line in an adjacent memory block. The array lines of a defective block of one type are mapped into a spare block of the same type. The array lines of a first adjacent block which are shared with array lines of the defective block, and the array lines of a second adjacent block which are shared with array lines of the defective block, are mapped into a second spare block of the other type, thereby mapping the defective block and portions of both adjacent blocks into just two spare blocks.

9. 发明申请

US20060146608A1 Integrated circuit including memory array incorporating multiple types of NAND string structures 有权
标题翻译：集成电路包括并入多种类型的NAND串结构的存储器阵列
公开(公告)号：US20060146608A1
公开(公告)日：2006-07-06
申请号：US11026492
申请日：2004-12-30
申请人： Luca Fasoli , Roy Scheuerlein
发明人： Luca Fasoli , Roy Scheuerlein
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/005 , H01L27/11524 , H01L27/11551
摘要： A monolithic integrated circuit includes a memory array having first and second groups of NAND strings, each NAND string comprising at least two series-connected devices and coupled at one end to an associated global array line. NAND strings of the first and second groups differ in at least one physical characteristic, such as the number of series-connected devices forming the NAND string, but both groups are disposed in a region of the memory array traversed by a plurality of global array lines. The memory array may include a three-dimensional memory array having more than one memory plane. Some of the NAND strings of the first group may be disposed on one memory plane, and some of the NAND strings of the second group may be disposed on another memory plane. In some cases, NAND strings of both groups may share global array lines.
摘要翻译：单片集成电路包括具有第一和第二组NAND串的存储器阵列，每个NAND串包括至少两个串联连接的器件，并在一端耦合到相关联的全局阵列线。第一组和第二组的NAND串在至少一个物理特性方面不同，例如形成NAND串的串联连接器件的数量，但两组都设置在由多个全局阵列线穿过的存储器阵列的区域中。存储器阵列可以包括具有多于一个存储器平面的三维存储器阵列。第一组的一些NAND串可以被布置在一个存储器平面上，并且第二组的一些NAND串可以被布置在另一个存储器平面上。在某些情况下，两组的NAND串可能共享全局阵列线。

10. 发明申请

US20060067127A1 Method of programming a monolithic three-dimensional memory 审中-公开
标题翻译：编写单片三维存储器的方法
公开(公告)号：US20060067127A1
公开(公告)日：2006-03-30
申请号：US10955049
申请日：2004-09-30
申请人： Luca Fasoli , Roy Scheuerlein , Alper Ilkbahar , En-Hsing Chen , Tanmay Kumar
发明人： Luca Fasoli , Roy Scheuerlein , Alper Ilkbahar , En-Hsing Chen , Tanmay Kumar
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/12 , G11C16/16
摘要： A method of programming a monolithic three-dimensional (3-D) memory having a plurality of levels of memory cells above a silicon substrate is disclosed. The method includes initializing a program voltage and program time interval; selecting a memory cell to be programmed within the three-dimensional memory having the plurality of levels of memory cells; applying a pulse having the program voltage and the program time interval to the selected memory cell; performing a read after write operation with respect to the selected memory cell to determine a measured threshold voltage value; and comparing the measured threshold voltage value to a minimum program voltage. In response to the comparison between the measured threshold voltage value and the minimum program voltage, the method further includes selectively applying at least one subsequent program pulse to the selected memory cell.
摘要翻译：公开了一种在硅衬底上编程具有多层存储单元的单片三维（3-D）存储器的方法。该方法包括初始化程序电压和程序时间间隔; 选择要在具有多个级别的存储器单元的三维存储器内编程的存储器单元; 将具有编程电压和程序时间间隔的脉冲施加到所选存储单元; 在对所选择的存储单元进行写操作之后执行读取以确定测量的阈值电压值; 以及将所测量的阈值电压值与最小编程电压进行比较。响应于测量的阈值电压值和最小编程电压之间的比较，该方法还包括选择性地将至少一个后续编程脉冲施加到所选存储单元。

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