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1. 发明申请

US20060221702A1 Decoding circuit for non-binary groups of memory line drivers 有权
标题翻译：用于非二进制组的存储器线路驱动器的解码电路
公开(公告)号：US20060221702A1
公开(公告)日：2006-10-05
申请号：US11146952
申请日：2005-06-07
申请人： Roy Scheuerlein , Christopher Petti , Luca Fasoli
发明人： Roy Scheuerlein , Christopher Petti , Luca Fasoli
IPC分类号： G11C11/34
CPC分类号： G11C8/10 , G11C5/063 , G11C8/08 , G11C8/14
摘要： A decoding circuit for non-binary groups of memory line drivers is disclosed. In one embodiment, an integrated circuit is disclosed comprising a binary decoder and circuitry operative to perform a non-binary arithmetic operation, wherein a result of the non-binary arithmetic operation is provided as input to the binary decoder. In another embodiment, an integrated circuit is disclosed comprising a memory array comprising a plurality of array lines, a non-integral-power-of-two number of array line driver circuits, and control circuitry configured to select one of the array line driver circuits. The control circuitry can comprise a binary decoder and a pre-decoder portion that performs a non-binary arithmetic operation. The concepts described herein may be used alone or in combination.
摘要翻译：公开了一种用于非二进制组的存储器线驱动器的解码电路。在一个实施例中，公开了一种集成电路，其包括二进制解码器和用于执行非二进制算术运算的电路，其中非二进制算术运算的结果被提供作为二进制解码器的输入。在另一个实施例中，公开了一种集成电路，其包括存储器阵列，该存储器阵列包括多个阵列线，两个非整数倍数量的阵列线驱动器电路，以及控制电路，被配置为选择阵列线驱动电路之一。控制电路可以包括执行非二进制算术运算的二进制解码器和预解码器部分。本文所述的概念可以单独使用或组合使用。

2. 发明授权

US07505321B2 Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same 有权
标题翻译：并联串联晶体管串的可编程存储器阵列结构及其制造和操作的方法
公开(公告)号：US07505321B2
公开(公告)日：2009-03-17
申请号：US10335078
申请日：2002-12-31
申请人： Roy E. Scheuerlein , Christopher Petti , Andrew J. Walker , En-Hsing Chen , Sucheta Nallamothu , Alper Ilkbahar , Luca Fasoli , Igor Koutnetsov
发明人： Roy E. Scheuerlein , Christopher Petti , Andrew J. Walker , En-Hsing Chen , Sucheta Nallamothu , Alper Ilkbahar , Luca Fasoli , Igor Koutnetsov
IPC分类号： G11C11/34 , G11C16/04 , G11C5/06 , G11C8/00
CPC分类号： H01L27/11568 , G11C11/5621 , G11C16/0483 , H01L27/115 , H01L27/1159
摘要： A three-dimensional flash memory array incorporates thin film transistors having a charge storage dielectric arranged in series-connected NAND strings to achieve a 4F2 memory cell layout. The memory array may be programmed and erased using only tunneling currents, and no leakage paths are formed through non-selected memory cells. Each NAND string includes two block select devices for respectively coupling one end of the NAND string to a global bit line, and the other end to a shared bias node. Pairs of NAND strings within a block share the same global bit line. The memory cells are preferably depletion mode SONOS devices, as are the block select devices. The memory cells may be programmed to a near depletion threshold voltage, and the block select devices are maintained in a programmed state having a near depletion mode threshold voltage. NAND strings on more than one layer may be connected to global bit lines on a single layer. By interleaving the NAND strings on each memory level and using two shared bias nodes per block, very little additional overhead is required for the switch devices at each end of the NAND strings. The NAND strings on different memory levels are preferably connected together by way of vertical stacked vias, each preferably connecting to more than one memory level. Each memory level may be produced with less than three masks per level.
摘要翻译：三维闪存阵列包括具有布置在串联连接的NAND串中的电荷存储电介质的薄膜晶体管，以实现4F2存储单元布局。可以仅使用隧穿电流对存储器阵列进行编程和擦除，并且不通过未选择的存储器单元形成泄漏路径。每个NAND串包括用于分别将NAND串的一端耦合到全局位线的两个块选择器件，另一端连接到共享偏置节点。块内的一对NAND串共享相同的全局位线。存储器单元优选地是耗尽型SONOS器件，块选择器件也是如此。存储器单元可以被编程为接近耗尽阈值电压，并且块选择器件保持在具有接近耗尽模式阈值电压的编程状态。多个层上的NAND串可以连接到单个层上的全局位线。通过在每个存储器级别交错NAND串并且每个块使用两个共享偏置节点，对于NAND串的每一端的开关器件需要非常少的附加开销。不同存储器级别的NAND串优选通过垂直堆叠的通孔连接在一起，每个优选地连接到多于一个的存储器级。每个存储器级别可以以每级别少于三个掩码来生成。

3. 发明授权

US07005350B2 Method for fabricating programmable memory array structures incorporating series-connected transistor strings 有权
标题翻译：用于制造并入串联晶体管串的可编程存储器阵列结构的方法
公开(公告)号：US07005350B2
公开(公告)日：2006-02-28
申请号：US10335089
申请日：2002-12-31
申请人： Andrew J. Walker , En-Hsing Chen , Sucheta Nallamothu , Roy E. Scheuerlein , Alper Ilkbahar , Luca Fasoli , Igor Koutnetsov , Christopher Petti
发明人： Andrew J. Walker , En-Hsing Chen , Sucheta Nallamothu , Roy E. Scheuerlein , Alper Ilkbahar , Luca Fasoli , Igor Koutnetsov , Christopher Petti
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , G11C16/0483 , H01L27/115 , H01L27/11502
摘要： A three-dimensional flash memory array incorporates thin film transistors having a charge storage dielectric arranged in series-connected NAND strings to achieve a 4F2 memory cell layout. The memory array may be programmed and erased using only tunneling currents, and no leakage paths are formed through non-selected memory cells. Each NAND string includes two block select devices for respectively coupling one end of the NAND string to a global bit line, and the other end to a shared bias node. Pairs of NAND strings within a block share the same global bit line. The memory cells are preferably depletion mode SONOS devices, as are the block select devices. The memory cells may be programmed to a near depletion threshold voltage, and the block select devices are maintained in a programmed state having a near depletion mode threshold voltage. NAND strings on more than one layer may be connected to global bit lines on a single layer. By interleaving the NAND strings on each memory level and using two shared bias nodes per block, very little additional overhead is required for the switch devices at each end of the NAND strings. The NAND strings on different memory levels are preferably connected together by way of vertical stacked vias, each preferably connecting to more than one memory level. Each memory level may be produced with less than three masks per level.
摘要翻译：三维闪存阵列包括具有布置在串联连接的NAND串中的电荷存储电介质的薄膜晶体管，以实现4F 2存储单元布局。可以仅使用隧穿电流对存储器阵列进行编程和擦除，并且不通过未选择的存储器单元形成泄漏路径。每个NAND串包括用于分别将NAND串的一端耦合到全局位线的两个块选择器件，另一端连接到共享偏置节点。块内的一对NAND串共享相同的全局位线。存储器单元优选地是耗尽型SONOS器件，块选择器件也是如此。存储器单元可以被编程为接近耗尽阈值电压，并且块选择器件保持在具有接近耗尽模式阈值电压的编程状态。多个层上的NAND串可以连接到单个层上的全局位线。通过在每个存储器级别交错NAND串并且每个块使用两个共享偏置节点，对于NAND串的每一端的开关器件需要非常少的附加开销。不同存储器级别的NAND串优选通过垂直堆叠的通孔连接在一起，每个优选地连接到多于一个的存储器级。每个存储器级别可以以每级别少于三个掩码来生成。

4. 发明申请

US20070072360A1 Method for using a memory cell comprising switchable semiconductor memory element with trimmable resistance 有权
标题翻译：一种用于使用具有可调整电阻的可切换半导体存储元件的存储单元的方法
公开(公告)号：US20070072360A1
公开(公告)日：2007-03-29
申请号：US11496986
申请日：2006-07-31
申请人： Tanmay Kumar , S.B. Herner , Roy Scheuerlein , Christopher Petti
发明人： Tanmay Kumar , S.B. Herner , Roy Scheuerlein , Christopher Petti
IPC分类号： H01L21/8234
CPC分类号： G11C11/5692 , G11C13/0069 , G11C17/14 , G11C17/165 , G11C2013/0073 , H01L27/101
摘要： A nonvolatile memory cell comprising a diode formed of semiconductor material can store memory states by changing the resistance of the semiconductor material by application of a set pulse (decreasing resistance) or a reset pulse (increasing resistance.) In preferred embodiments, set pulses are applied with the diode under forward bias, while reset pulses are applied with the diode in reverse bias. By switching resistivity of the semiconductor material of the diode, a memory cell can be either one-time programmable or rewriteable, and can achieve two, three, four, or more distinct data states.
摘要翻译：包括由半导体材料形成的二极管的非易失性存储单元可以通过施加设置脉冲（降低电阻）或复位脉冲（增加电阻）来改变半导体材料的电阻来存储存储器状态。在优选实施例中，施加设定脉冲二极管在正向偏置下，而复位脉冲以二极管反向施加。通过切换二极管的半导体材料的电阻率，存储器单元可以是一次性可编程的或可重写的，并且可以实现两个，三个，四个或更多个不同的数据状态。

5. 发明申请

US20070007579A1 Memory cell comprising a thin film three-terminal switching device having a metal source and /or drain region 审中-公开
标题翻译：存储单元包括具有金属源极和/或漏极区域的薄膜三端子开关器件
公开(公告)号：US20070007579A1
公开(公告)日：2007-01-11
申请号：US11179095
申请日：2005-07-11
申请人： Roy Scheuerlein , Christopher Petti
发明人： Roy Scheuerlein , Christopher Petti
IPC分类号： H01L29/76
CPC分类号： H01L27/1203 , G11C11/5614 , G11C11/5685 , G11C13/0007 , G11C13/0011 , G11C2213/31 , G11C2213/51 , G11C2213/56 , G11C2213/71 , G11C2213/79 , H01L21/84 , H01L27/101 , H01L27/112 , H01L27/11206 , H01L27/115 , H01L27/11502 , H01L27/11507 , H01L27/2436 , H01L27/2481 , H01L29/685 , H01L29/786 , H01L29/8605 , H01L45/04 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1266 , H01L45/146 , H01L45/147 , H01L45/1675
摘要： A nonvolatile memory cell comprising a switchable resistor memory element and a thin-film three-terminal switching device, preferably a MOSFET, in series. The switchable resistor memory element has the property of having at least two stable resistance states, for example a high-resistance state and a low-resistance state. It is switched between the two states, and its resistance state (and thus the data state of the cell) is sensed by providing appropriate current through the three-terminal switching device. Preferred embodiments of the present invention include a highly dense monolithic three dimensional memory array in which multiple memory levels of such memory cells are formed above a single substrate such as a monocrystalline silicon wafer.
摘要翻译：一种包括可切换电阻存储元件和薄膜三端开关器件（优选为MOSFET）的非易失性存储单元。可切换电阻存储元件具有至少两个稳定的电阻状态的特性，例如高电阻状态和低电阻状态。它在两个状态之间切换，并且通过提供通过三端开关器件的合适电流来感测其电阻状态（并因此感测单元的数据状态）。本发明的优选实施例包括高密度单片三维存储器阵列，其中这种存储器单元的多个存储器级别形成在诸如单晶硅晶片的单个衬底之上。

6. 发明申请

US20060221758A1 TRANSISTOR LAYOUT CONFIGURATION FOR TIGHT-PITCHED MEMORY ARRAY LINES 有权
标题翻译：用于紧凑的内存阵列的晶体管布局配置
公开(公告)号：US20060221758A1
公开(公告)日：2006-10-05
申请号：US11420787
申请日：2006-05-29
申请人： Christopher Petti , Roy Scheuerlein , Tanmay Kumar , Abhijit Bandyopadhyay
发明人： Christopher Petti , Roy Scheuerlein , Tanmay Kumar , Abhijit Bandyopadhyay
IPC分类号： G11C8/00
CPC分类号： G11C8/14 , G11C5/02 , G11C5/063 , G11C8/08 , H01L27/0207 , H01L27/0688 , H01L27/10894 , H01L27/10897
摘要： A multi-headed word line driver circuit incorporates bent-gate transistors to reduce the pitch otherwise achievable for interfacing to tightly-pitched array lines. In certain exemplary embodiments, a three-dimensional memory array includes multiple memory blocks and array lines traversing horizontally across at least one memory block. Vertical active area stripes are disposed beneath a first memory block, and a respective plurality of bent-gate electrodes intersects each respective active area stripe to define individual source/drain regions. Every other source/drain region is coupled to a bias node for the active area stripe, and remaining source/drain regions are respectively coupled to a respective array line associated with the first memory block, thereby forming a respective first driver transistor for the respective array line. In certain embodiments, a respective plurality of complementary array line driver circuits is disposed on each side of a connection area between adjacent memory blocks, and each such driver circuit is responsive to a single driver input node.
摘要翻译：多头字线驱动电路包括弯栅晶体管，以减少为了与紧密排列的阵列线连接而实现的间距。在某些示例性实施例中，三维存储器阵列包括穿过至少一个存储器块水平横越的多个存储器块和阵列线。垂直有源区条纹设置在第一存储块下方，并且相应的多个弯曲栅电极与每个相应的有源区条纹相交以限定各个源/漏区。每个其它源极/漏极区域耦合到用于有源区域条纹的偏置节点，并且剩余的源极/漏极区域分别耦合到与第一存储器模块相关联的相应阵列线，从而形成用于相应阵列的相应的第一驱动器晶体管线。在某些实施例中，相应的多个互补阵列线驱动器电路设置在相邻存储块之间的连接区域的每一侧上，并且每个这样的驱动器电路响应于单个驱动器输入节点。

7. 发明申请

US20050127519A1 High density contact to relaxed geometry layers 有权
标题翻译：高密度接触放松几何层
公开(公告)号：US20050127519A1
公开(公告)日：2005-06-16
申请号：US10728451
申请日：2003-12-05
申请人： Roy Scheuerlein , Christopher Petti
发明人： Roy Scheuerlein , Christopher Petti
IPC分类号： H01L21/8246 , H01L21/8247 , H01L23/522 , H01L27/115 , H01L29/40
CPC分类号： H01L23/5226 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides for a via and staggered routing level structure. Vertically overlapping vias connect to two or more routing levels formed at different heights. The routing levels are either both formed above or both formed below the vias, and all are formed above a semiconductor substrate wafer. In this way vias can be formed having a pitch smaller than the pitch of either the first routing level or the second routing level, saving space.
摘要翻译：本发明提供一种通孔和交错路由级结构。垂直重叠的通孔连接到在不同高度形成的两个或多个路由级别。路由级别既被形成在通孔下方形成，也可以形成在通孔下方，并且都形成在半导体衬底晶片之上。以这种方式，可以形成具有小于第一路由级别或第二路由级别的间距的间距的通孔，从而节省空间。

8. 发明申请

US20070007577A1 Integrated circuit embodying a non-volatile memory cell 审中-公开
标题翻译：集成电路体现了非易失性存储单元
公开(公告)号：US20070007577A1
公开(公告)日：2007-01-11
申请号：US11175688
申请日：2005-07-06
申请人： Abhijit Bandyopadhyay , Christopher Petti , Tanmay Kumar
发明人： Abhijit Bandyopadhyay , Christopher Petti , Tanmay Kumar
IPC分类号： H01L29/788
CPC分类号： H01L29/7883 , G11C16/0416 , G11C2216/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： An integrated circuit is provided including at least one memory cell. Such memory cell, in turn, includes a transistor and a capacitor. The transistor includes a source, a drain, and a gate. Further, the capacitor includes a well and a gate. The gate of the transistor remains in communication with the gate of the capacitor. In various other embodiments, the memory cell includes a transistor and a capacitor including wells of differing types (e.g. P-type, N-type). In such embodiments, the well of the transistor abuts the well of the capacitor. In still further embodiments, for a more compact design, a diffusion region of the transistor is situated less than 2.5 μm from a diffusion region of the capacitor.
摘要翻译：提供了包括至少一个存储单元的集成电路。这样的存储单元又包括晶体管和电容器。晶体管包括源极，漏极和栅极。此外，电容器包括阱和栅极。晶体管的栅极保持与电容器的栅极通信。在各种其他实施例中，存储单元包括晶体管和包括不同类型的阱（例如，P型，N型）的电容器。在这样的实施例中，晶体管的阱邻接电容器的阱。在另外的实施例中，为了更紧凑的设计，晶体管的扩散区域距离电容器的扩散区域小于2.5μm。

9. 发明申请

US20060250836A1 Rewriteable memory cell comprising a diode and a resistance-switching material 审中-公开
标题翻译：包括二极管和电阻切换材料的可重写存储单元
公开(公告)号：US20060250836A1
公开(公告)日：2006-11-09
申请号：US11125939
申请日：2005-05-09
申请人： S. Herner , Christopher Petti
发明人： S. Herner , Christopher Petti
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C11/5685 , G11C13/0069 , G11C2013/009 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146
摘要： In a novel rewriteable nonvolatile memory cell formed above a substrate, a diode is paired with a reversible resistance-switching material, preferably a metal oxide or nitride such as, for example, NiO, Nb2O5, TiO2, HfO2, Al2O3, MgOx, CrO2, VO, BN, and AlN. In preferred embodiments, the diode is formed as a vertical pillar disposed between conductors. Multiple memory levels can be stacked to form a monolithic three dimensional memory array. In some embodiments, the diode comprises germanium or a germanium alloy, which can be deposited and crystallized at relatively low temperatures, allowing use of aluminum or copper in the conductors.
摘要翻译：在形成于基板上方的新型可重写非易失性存储单元中，二极管与可逆电阻切换材料配对，优选为金属氧化物或氮化物，例如NiO，Nb 2 O > 5，TiO 2，HfO 2，Al 2 O 3，MgO， xO，CrO 2，VO，BN和AlN。在优选实施例中，二极管形成为设置在导体之间的垂直支柱。可以堆叠多个存储器级别以形成单片三维存储器阵列。在一些实施例中，二极管包括锗或锗合金，其可以在相对低的温度下沉积和结晶，从而允许在导体中使用铝或铜。

10. 发明申请

US20060249735A1 TFT mask ROM and method for making same 有权
公开(公告)号：US20060249735A1
公开(公告)日：2006-11-09
申请号：US11484757
申请日：2006-07-12
申请人： Andrew Walker , Christopher Petti
发明人： Andrew Walker , Christopher Petti
IPC分类号： H01L29/04 , H01L29/80 , H01L29/76
CPC分类号： H01L27/1128 , G11C17/12 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/105 , H01L27/11 , H01L27/1108 , H01L27/1116 , H01L27/112 , H01L27/1126 , H01L27/11286 , H01L27/11293 , H01L27/115 , H01L27/11517 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11568 , H01L27/11578 , H01L27/11803 , H01L27/1203 , H01L27/1214 , H01L29/66825
摘要： There is provided a monolithic three dimensional TFT mask ROM array. The array includes a plurality of device levels. Each of the plurality of device levels contains a first set of enabled TFTs and a second set of partially or totally disabled TFTs.

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