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1. 发明申请

US20070242511A1 NAND MEMORY ARRAY INCORPORATING CAPACITANCE BOOSTING OF CHANNEL REGIONS IN UNSELECTED MEMORY CELLS AND METHOD FOR OPERATION OF SAME 有权
标题翻译： NAND存储器阵列在不连续记忆细胞中的通道增加电容及其操作方法
公开(公告)号：US20070242511A1
公开(公告)日：2007-10-18
申请号：US11764793
申请日：2007-06-18
申请人： En-Hsing Chen , Andrew Walker , Roy Scheuerlein , Sucheta Nallamothu , Alper Ilkbahar , Luca Fasoli
发明人： En-Hsing Chen , Andrew Walker , Roy Scheuerlein , Sucheta Nallamothu , Alper Ilkbahar , Luca Fasoli
IPC分类号： G11C16/10
CPC分类号： G11C16/3418 , G11C11/5621 , G11C16/0483 , G11C16/10 , G11C16/3427 , H01L27/115 , H01L27/11568 , H01L27/1159
摘要： An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.
摘要翻译：示例性的NAND串存储器阵列提供半选择的存储器单元通道的电容性升压以减少半选择单元的程序干扰效应。为了减小升压电平的漏电流劣化的影响，采用较短持续时间的多个编程脉冲来限制这种漏电流可能降低未选择的NAND串中的电压的时间周期。此外，在每个NAND串的一端或两端的多个串联选择装置进一步确保了对于未选择的和选择的NAND串的这种选择装置的减少的泄漏。在某些示例性实施例中，存储器阵列包括具有电荷存储电介质的存储单元晶体管的串联连接的NAND串，并且包括形成在衬底上方的多于一个的存储单元平面。

2. 发明申请

US20050128807A1 Nand memory array incorporating multiple series selection devices and method for operation of same 审中-公开
标题翻译：包含多个系列选择装置的Nand存储器阵列及其操作方法
公开(公告)号：US20050128807A1
公开(公告)日：2005-06-16
申请号：US10729865
申请日：2003-12-05
申请人： En-Hsing Chen , Andrew Walker , Roy Scheuerlein , Sucheta Nallamothu , Alper Ilkbahar , Luca Fasoli , James Cleeves
发明人： En-Hsing Chen , Andrew Walker , Roy Scheuerlein , Sucheta Nallamothu , Alper Ilkbahar , Luca Fasoli , James Cleeves
IPC分类号： G11C8/08 , G11C16/04 , G11C16/08 , G11C16/34
CPC分类号： G11C16/0483 , G11C8/08 , G11C16/08 , G11C16/3418 , G11C16/3427
摘要： An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.
摘要翻译：示例性的NAND串存储器阵列提供半选择的存储器单元通道的电容性升压以减少半选择单元的程序干扰效应。为了减小升压电平的漏电流劣化的影响，采用较短持续时间的多个编程脉冲来限制这种漏电流可能降低未选择的NAND串中的电压的时间周期。此外，在每个NAND串的一端或两端的多个串联选择装置进一步确保了对于未选择的和选择的NAND串的这种选择装置的减少的泄漏。在某些示例性实施例中，存储器阵列包括具有电荷存储电介质的存储单元晶体管的串联连接的NAND串，并且包括形成在衬底上方的多于一个的存储单元平面。

3. 发明申请

US20050122780A1 NAND memory array incorporating multiple write pulse programming of individual memory cells and method for operation of same 有权
标题翻译： NAND存储器阵列结合了各个存储单元的多个写脉冲编程及其操作方法
公开(公告)号：US20050122780A1
公开(公告)日：2005-06-09
申请号：US10729844
申请日：2003-12-05
申请人： En-Hsing Chen , Andrew Walker , Roy Scheuerlein , Sucheta Nallamothu , Alper Ilkbahar , Luca Fasoli
发明人： En-Hsing Chen , Andrew Walker , Roy Scheuerlein , Sucheta Nallamothu , Alper Ilkbahar , Luca Fasoli
IPC分类号： G11C5/02 , G11C11/56 , G11C16/04 , G11C16/10
CPC分类号： G11C16/10 , G11C11/5671 , G11C16/0466 , G11C16/0483
摘要： An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.
摘要翻译：示例性的NAND串存储器阵列提供半选择的存储器单元通道的电容性升压以减少半选择单元的程序干扰效应。为了减小升压电平的漏电流劣化的影响，采用较短持续时间的多个编程脉冲来限制这种漏电流可能降低未选择的NAND串中的电压的时间周期。此外，在每个NAND串的一端或两端的多个串联选择装置进一步确保了对于未选择的和选择的NAND串的这种选择装置的减少的泄漏。在某些示例性实施例中，存储器阵列包括具有电荷存储电介质的存储单元晶体管的串联连接的NAND串，并且包括形成在衬底上方的多于一个的存储单元平面。

4. 发明授权

US07505321B2 Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same 有权
标题翻译：并联串联晶体管串的可编程存储器阵列结构及其制造和操作的方法
公开(公告)号：US07505321B2
公开(公告)日：2009-03-17
申请号：US10335078
申请日：2002-12-31
申请人： Roy E. Scheuerlein , Christopher Petti , Andrew J. Walker , En-Hsing Chen , Sucheta Nallamothu , Alper Ilkbahar , Luca Fasoli , Igor Koutnetsov
发明人： Roy E. Scheuerlein , Christopher Petti , Andrew J. Walker , En-Hsing Chen , Sucheta Nallamothu , Alper Ilkbahar , Luca Fasoli , Igor Koutnetsov
IPC分类号： G11C11/34 , G11C16/04 , G11C5/06 , G11C8/00
CPC分类号： H01L27/11568 , G11C11/5621 , G11C16/0483 , H01L27/115 , H01L27/1159
摘要： A three-dimensional flash memory array incorporates thin film transistors having a charge storage dielectric arranged in series-connected NAND strings to achieve a 4F2 memory cell layout. The memory array may be programmed and erased using only tunneling currents, and no leakage paths are formed through non-selected memory cells. Each NAND string includes two block select devices for respectively coupling one end of the NAND string to a global bit line, and the other end to a shared bias node. Pairs of NAND strings within a block share the same global bit line. The memory cells are preferably depletion mode SONOS devices, as are the block select devices. The memory cells may be programmed to a near depletion threshold voltage, and the block select devices are maintained in a programmed state having a near depletion mode threshold voltage. NAND strings on more than one layer may be connected to global bit lines on a single layer. By interleaving the NAND strings on each memory level and using two shared bias nodes per block, very little additional overhead is required for the switch devices at each end of the NAND strings. The NAND strings on different memory levels are preferably connected together by way of vertical stacked vias, each preferably connecting to more than one memory level. Each memory level may be produced with less than three masks per level.
摘要翻译：三维闪存阵列包括具有布置在串联连接的NAND串中的电荷存储电介质的薄膜晶体管，以实现4F2存储单元布局。可以仅使用隧穿电流对存储器阵列进行编程和擦除，并且不通过未选择的存储器单元形成泄漏路径。每个NAND串包括用于分别将NAND串的一端耦合到全局位线的两个块选择器件，另一端连接到共享偏置节点。块内的一对NAND串共享相同的全局位线。存储器单元优选地是耗尽型SONOS器件，块选择器件也是如此。存储器单元可以被编程为接近耗尽阈值电压，并且块选择器件保持在具有接近耗尽模式阈值电压的编程状态。多个层上的NAND串可以连接到单个层上的全局位线。通过在每个存储器级别交错NAND串并且每个块使用两个共享偏置节点，对于NAND串的每一端的开关器件需要非常少的附加开销。不同存储器级别的NAND串优选通过垂直堆叠的通孔连接在一起，每个优选地连接到多于一个的存储器级。每个存储器级别可以以每级别少于三个掩码来生成。

5. 发明授权

US07005350B2 Method for fabricating programmable memory array structures incorporating series-connected transistor strings 有权
标题翻译：用于制造并入串联晶体管串的可编程存储器阵列结构的方法
公开(公告)号：US07005350B2
公开(公告)日：2006-02-28
申请号：US10335089
申请日：2002-12-31
申请人： Andrew J. Walker , En-Hsing Chen , Sucheta Nallamothu , Roy E. Scheuerlein , Alper Ilkbahar , Luca Fasoli , Igor Koutnetsov , Christopher Petti
发明人： Andrew J. Walker , En-Hsing Chen , Sucheta Nallamothu , Roy E. Scheuerlein , Alper Ilkbahar , Luca Fasoli , Igor Koutnetsov , Christopher Petti
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , G11C16/0483 , H01L27/115 , H01L27/11502
摘要： A three-dimensional flash memory array incorporates thin film transistors having a charge storage dielectric arranged in series-connected NAND strings to achieve a 4F2 memory cell layout. The memory array may be programmed and erased using only tunneling currents, and no leakage paths are formed through non-selected memory cells. Each NAND string includes two block select devices for respectively coupling one end of the NAND string to a global bit line, and the other end to a shared bias node. Pairs of NAND strings within a block share the same global bit line. The memory cells are preferably depletion mode SONOS devices, as are the block select devices. The memory cells may be programmed to a near depletion threshold voltage, and the block select devices are maintained in a programmed state having a near depletion mode threshold voltage. NAND strings on more than one layer may be connected to global bit lines on a single layer. By interleaving the NAND strings on each memory level and using two shared bias nodes per block, very little additional overhead is required for the switch devices at each end of the NAND strings. The NAND strings on different memory levels are preferably connected together by way of vertical stacked vias, each preferably connecting to more than one memory level. Each memory level may be produced with less than three masks per level.
摘要翻译：三维闪存阵列包括具有布置在串联连接的NAND串中的电荷存储电介质的薄膜晶体管，以实现4F 2存储单元布局。可以仅使用隧穿电流对存储器阵列进行编程和擦除，并且不通过未选择的存储器单元形成泄漏路径。每个NAND串包括用于分别将NAND串的一端耦合到全局位线的两个块选择器件，另一端连接到共享偏置节点。块内的一对NAND串共享相同的全局位线。存储器单元优选地是耗尽型SONOS器件，块选择器件也是如此。存储器单元可以被编程为接近耗尽阈值电压，并且块选择器件保持在具有接近耗尽模式阈值电压的编程状态。多个层上的NAND串可以连接到单个层上的全局位线。通过在每个存储器级别交错NAND串并且每个块使用两个共享偏置节点，对于NAND串的每一端的开关器件需要非常少的附加开销。不同存储器级别的NAND串优选通过垂直堆叠的通孔连接在一起，每个优选地连接到多于一个的存储器级。每个存储器级别可以以每级别少于三个掩码来生成。

6. 发明申请

US20060067127A1 Method of programming a monolithic three-dimensional memory 审中-公开
标题翻译：编写单片三维存储器的方法
公开(公告)号：US20060067127A1
公开(公告)日：2006-03-30
申请号：US10955049
申请日：2004-09-30
申请人： Luca Fasoli , Roy Scheuerlein , Alper Ilkbahar , En-Hsing Chen , Tanmay Kumar
发明人： Luca Fasoli , Roy Scheuerlein , Alper Ilkbahar , En-Hsing Chen , Tanmay Kumar
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/12 , G11C16/16
摘要： A method of programming a monolithic three-dimensional (3-D) memory having a plurality of levels of memory cells above a silicon substrate is disclosed. The method includes initializing a program voltage and program time interval; selecting a memory cell to be programmed within the three-dimensional memory having the plurality of levels of memory cells; applying a pulse having the program voltage and the program time interval to the selected memory cell; performing a read after write operation with respect to the selected memory cell to determine a measured threshold voltage value; and comparing the measured threshold voltage value to a minimum program voltage. In response to the comparison between the measured threshold voltage value and the minimum program voltage, the method further includes selectively applying at least one subsequent program pulse to the selected memory cell.
摘要翻译：公开了一种在硅衬底上编程具有多层存储单元的单片三维（3-D）存储器的方法。该方法包括初始化程序电压和程序时间间隔; 选择要在具有多个级别的存储器单元的三维存储器内编程的存储器单元; 将具有编程电压和程序时间间隔的脉冲施加到所选存储单元; 在对所选择的存储单元进行写操作之后执行读取以确定测量的阈值电压值; 以及将所测量的阈值电压值与最小编程电压进行比较。响应于测量的阈值电压值和最小编程电压之间的比较，该方法还包括选择性地将至少一个后续编程脉冲施加到所选存储单元。

7. 发明授权

US07433233B2 NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same 有权
标题翻译： NAND存储器阵列结合未选择的存储单元中的沟道区域的电容升压及其操作方法
公开(公告)号：US07433233B2
公开(公告)日：2008-10-07
申请号：US11764793
申请日：2007-06-18
申请人： En-Hsing Chen , Andrew J. Walker , Roy E. Scheuerlein , Sucheta Nallamothu , Alper Ilkbahar , Luca G. Fasoli
发明人： En-Hsing Chen , Andrew J. Walker , Roy E. Scheuerlein , Sucheta Nallamothu , Alper Ilkbahar , Luca G. Fasoli
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/3418 , G11C11/5621 , G11C16/0483 , G11C16/10 , G11C16/3427 , H01L27/115 , H01L27/11568 , H01L27/1159
摘要： An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.
摘要翻译：示例性的NAND串存储器阵列提供半选择的存储器单元通道的电容性升压以减少半选择单元的程序干扰效应。为了减小升压电平的漏电流劣化的影响，采用较短持续时间的多个编程脉冲来限制这种漏电流可能降低未选择的NAND串中的电压的时间周期。此外，在每个NAND串的一端或两端的多个串联选择装置进一步确保了对于未选择的和选择的NAND串的这种选择装置的减少的泄漏。在某些示例性实施例中，存储器阵列包括具有电荷存储电介质的存储单元晶体管的串联连接的NAND串，并且包括形成在衬底上方的多于一个的存储单元平面。

8. 发明授权

US07233522B2 NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same 有权
标题翻译： NAND存储器阵列结合未选择的存储单元中的沟道区域的电容升压及其操作方法
公开(公告)号：US07233522B2
公开(公告)日：2007-06-19
申请号：US10729831
申请日：2003-12-05
申请人： En-Hsing Chen , Andrew J. Walker , Roy E. Scheuerlein , Sucheta Nallamothu , Alper Ilkbahar , Luca G. Fasoli
发明人： En-Hsing Chen , Andrew J. Walker , Roy E. Scheuerlein , Sucheta Nallamothu , Alper Ilkbahar , Luca G. Fasoli
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C11/5621 , G11C16/0483 , G11C16/10 , G11C16/3427 , H01L27/115 , H01L27/11568 , H01L27/1159
摘要： An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.
摘要翻译：示例性的NAND串存储器阵列提供半选择的存储器单元通道的电容性升压以减少半选择单元的程序干扰效应。为了减小升压电平的漏电流劣化的影响，采用较短持续时间的多个编程脉冲来限制这种漏电流可能降低未选择的NAND串中的电压的时间周期。此外，在每个NAND串的一端或两端的多个串联选择装置进一步确保了对于未选择的和选择的NAND串的这种选择装置的减少的泄漏。在某些示例性实施例中，存储器阵列包括具有电荷存储电介质的存储单元晶体管的串联连接的NAND串，并且包括形成在衬底上方的多于一个的存储单元平面。

9. 发明授权

US07023739B2 NAND memory array incorporating multiple write pulse programming of individual memory cells and method for operation of same 有权
标题翻译： NAND存储器阵列结合了各个存储单元的多个写脉冲编程及其操作方法
公开(公告)号：US07023739B2
公开(公告)日：2006-04-04
申请号：US10729844
申请日：2003-12-05
申请人： En-Hsing Chen , Andrew J. Walker , Roy E. Scheuerlein , Sucheta Nallamothu , Alper Ilkbahar , Luca G. Fasoli
发明人： En-Hsing Chen , Andrew J. Walker , Roy E. Scheuerlein , Sucheta Nallamothu , Alper Ilkbahar , Luca G. Fasoli
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/10 , G11C11/5671 , G11C16/0466 , G11C16/0483
摘要： An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.
摘要翻译：示例性的NAND串存储器阵列提供半选择的存储器单元通道的电容性升压以减少半选择单元的程序干扰效应。为了减小升压电平的漏电流劣化的影响，采用较短持续时间的多个编程脉冲来限制这种漏电流可能降低未选择的NAND串中的电压的时间周期。此外，在每个NAND串的一端或两端的多个串联选择装置进一步确保了对于未选择的和选择的NAND串的这种选择装置的减少的泄漏。在某些示例性实施例中，存储器阵列包括具有电荷存储电介质的存储单元晶体管的串联连接的NAND串，并且包括形成在衬底上方的多于一个的存储单元平面。

10. 发明申请

US20050079675A1 Semiconductor device with localized charge storage dielectric and method of making same 有权
公开(公告)号：US20050079675A1
公开(公告)日：2005-04-14
申请号：US10965763
申请日：2004-10-18
申请人： Alper Ilkbahar , Roy Scheuerlein , Andrew Walker , Luca Fasoli
发明人： Alper Ilkbahar , Roy Scheuerlein , Andrew Walker , Luca Fasoli
IPC分类号： G11C16/04 , H01L21/28 , H01L21/336 , H01L29/792 , H01L21/00 , H01L21/31 , H01L21/469 , H01L21/84
CPC分类号： H01L29/66833 , G11C16/0466 , G11C16/0491 , H01L21/28282 , H01L29/792
摘要： An array of transistors includes a plurality of transistors, a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction. Each transistor includes a source, a drain, a channel and a localized charge storage dielectric. A first transistor of the plurality of transistors and a second transistor of the plurality of transistors share a common source/drain. A first localized charge storage dielectric of the first transistor does not overlap the common source/drain and a second localized charge storage dielectric of the second transistor overlaps the common source/drain.

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