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1. 发明授权

US08278684B1 Voltage protection device 有权
标题翻译：电压保护装置
公开(公告)号：US08278684B1
公开(公告)日：2012-10-02
申请号：US11954514
申请日：2007-12-12
申请人： Andrew J. Walker , Helmut Puchner
发明人： Andrew J. Walker , Helmut Puchner
IPC分类号： H01L29/66
CPC分类号： H01L29/7436 , H01L27/0262 , H01L29/0603
摘要： A voltage protection device and method is provided to prevent accidental triggering of an silicon-controlled rectifier (SCR) unless the electrostatic discharge (ESD) is at a predefined threshold above the normal power supply operating voltage or below the ground supply operating voltage. The holding voltage upon the SCR is maintained above the threshold voltage to prevent accidental triggering. The present SCR avoids use of an additional field effect transistor (FET), and avoids relying upon the breakdown of the drain terminal of the FET, but instead programs the amount of holding voltage needed above the power supply voltage using mask-programmability, fuses, or other means for maintaining the holding voltage to a desired range above the power supply voltage. The programmed holding voltage is implemented using a barrier region between the PNP and the NPN of the PNPN junctions of the SCR. In addition to or as an alternative to the barrier region, hole sink junctions can be implemented close to the anode to reduce the substrate resistance in the vicinity of the anode and, therefore, extract holes from their normal target destination.
摘要翻译：提供了一种电压保护装置和方法，以防止硅可控整流器（SCR）的意外触发，除非静电放电（ESD）处于高于正常电源工作电压或低于接地电源工作电压的预定阈值。 SCR上的保持电压保持在阈值电压以上，以防止意外触发。当前的SCR避免使用附加的场效应晶体管（FET），并且避免依赖于FET的漏极端子的击穿，而是使用掩模可编程性，保险丝来编程所需的高于电源电压的保持电压量，或用于将保持电压维持在高于电源电压的期望范围的其它装置。编程的保持电压使用PNP与SCR的PNPN结的NPN之间的屏障区域来实现。除了作为屏障区域的替代方案之外，可以在阳极附近实现空穴接合点，以降低阳极附近的衬底电阻，并因此从其正常目标目的地提取孔。

2. 发明授权

US07777269B2 Dual-gate device 有权
公开(公告)号：US07777269B2
公开(公告)日：2010-08-17
申请号：US12142547
申请日：2008-06-19
申请人： Andrew J. Walker
发明人： Andrew J. Walker
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , G11C16/10 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/4234 , H01L29/42352
摘要： A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor layer has a thickness such that a sensitivity parameter relating an electrical interaction between the gate electrodes of the access device and the memory device is less than a predetermined value. The dual-gate memory cells can be used as building blocks for a non-volatile memory array, such as a memory array formed by NAND-strings. In such an array, during programming of a nearby memory device in a NAND string, in NAND-strings not to be programmed, if inversion regions are allowed to be formed in the semiconductor layer, or if the semiconductor layer is allowed to electrically float, electrical interaction exists between the access devices and the memory devices to inhibit programming of the memory devices.

3. 发明申请

US20090258462A1 METHOD FOR FORMING DOPED POLYSILICON VIA CONNECTING POLYSILICON LAYERS 有权
标题翻译：通过连接多晶硅层形成掺杂多晶硅的方法
公开(公告)号：US20090258462A1
公开(公告)日：2009-10-15
申请号：US12489214
申请日：2009-06-22
申请人： Michael W. Konevecki , Usha Raghuram , Maitreyee Mahajani , Sucheta Nallamothu , Andrew J. Walker , Tanmay Kumar
发明人： Michael W. Konevecki , Usha Raghuram , Maitreyee Mahajani , Sucheta Nallamothu , Andrew J. Walker , Tanmay Kumar
IPC分类号： H01L21/82
CPC分类号： H01L27/12 , H01L21/28282 , H01L21/84 , H01L23/535 , H01L27/0688 , H01L27/115 , H01L27/11521 , H01L27/11551 , H01L27/11568 , H01L27/11578 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.
摘要翻译：本发明提供了连接在不同高度形成的导电多晶硅层的多晶硅通孔。多晶硅通孔有利地用于电荷存储晶体管的单片三维存储器阵列中。根据本发明的多晶硅通孔可以用于例如将电荷存储晶体管存储单元的第一器件电平的沟道层连接到形成在第一器件电平之上的这样的单元的第二器件层的沟道层。类似地，根据本发明的通孔可用于将电荷存储晶体管存储单元的第一器件电平的字线连接到这种单元的第二器件层的沟道层。

4. 发明申请

US20090087973A1 RETENTION IMPROVEMENT IN DUAL-GATE MEMORY 审中-公开
标题翻译：双门记忆中的保持改进
公开(公告)号：US20090087973A1
公开(公告)日：2009-04-02
申请号：US12240848
申请日：2008-09-29
申请人： Andrew J. Walker
发明人： Andrew J. Walker
IPC分类号： H01L21/3205
CPC分类号： H01L27/12 , H01L27/11568
摘要： A manufacturing process improves retention capabilties of dual-gate non-volatile memory cells by limiting the effects of lateral charge movement. The process limits lateral extents of the charge storage medium that is an integral part of the memory device within the dual-gate device.
摘要翻译：通过限制横向电荷运动的影响，制造工艺提高了双栅非易失性存储单元的保留能力。该过程限制作为双栅极器件内的存储器件的组成部分的电荷存储介质的横向范围。

5. 发明申请

US20080315294A1 DUAL-GATE DEVICE AND METHOD 有权
标题翻译：双门装置和方法
公开(公告)号：US20080315294A1
公开(公告)日：2008-12-25
申请号：US12142547
申请日：2008-06-19
申请人： Andrew J. Walker
发明人： Andrew J. Walker
IPC分类号： H01L29/00
CPC分类号： H01L29/792 , G11C16/10 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/4234 , H01L29/42352
摘要： A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor layer has a thickness such that a sensitivity parameter relating an electrical interaction between the gate electrodes of the access device and the memory device is less than a predetermined value. The dual-gate memory cells can be used as building blocks for a non-volatile memory array, such as a memory array formed by NAND-strings. In such an array, during programming of a nearby memory device in a NAND string, in NAND-strings not to be programmed, if inversion regions are allowed to be formed in the semiconductor layer, or if the semiconductor layer is allowed to electrically float, electrical interaction exists between the access devices and the memory devices to inhibit programming of the memory devices.
摘要翻译：公开了一种具有双栅极存储单元的存储电路及其制造方法。双栅极存储单元各自包括存储器件和共享半导体层的存取器件，其各自的沟道区域设置在半导体层的不同表面上。半导体层的厚度使得与存取装置的栅电极和存储装置之间的电相互作用相关的灵敏度参数小于预定值。双栅极存储器单元可以用作非易失性存储器阵列的构造块，诸如由NAND串形成的存储器阵列。在这种阵列中，在NAND串中的附近的存储器件的编程期间，在不编程的NAND串中，如果允许在半导体层中形成反转区域，或者允许半导体层电浮动，存取装置和存储装置之间存在电相互作用以阻止存储装置的编程。

6. 发明申请

US20080283921A1 DUAL-GATE NMOS DEVICES WITH ANTIMONY SOURCE-DRAIN REGIONS AND METHODS FOR MANUFACTURING THEREOF 审中-公开
标题翻译：具有反源漏区的双栅极NMOS器件及其制造方法
公开(公告)号：US20080283921A1
公开(公告)日：2008-11-20
申请号：US11749078
申请日：2007-05-15
申请人： Andrew J. Walker
发明人： Andrew J. Walker
IPC分类号： H01L29/78
CPC分类号： H01L21/26513 , H01L29/4908 , H01L29/78645 , H01L29/78648
摘要： A dual-gate device includes an active layer between a first gate structure and a second gate structure. Each gate structure is isolated from the active layer by a dielectric layer and is located above a semiconductor or channel region in the active layer defined by spaced-apart diffusion regions formed by implanting antimony ions. The antimony-doped diffusion regions are particularly suitable in the dual-gate device because it can be implanted and activated at a temperature less than 900° C. and show little movement of the implanted antimony ions even after numerous thermal steps in the manufacturing process. As a result, dual-gate devices with well-controlled channel lengths may be achieved.
摘要翻译：双栅极器件包括在第一栅极结构和第二栅极结构之间的有源层。每个栅极结构通过介电层与有源层隔离，并且位于由通过注入锑离子形成的间隔扩散区限定的有源层中的半导体或沟道区的上方。掺杂锑的扩散区域特别适用于双栅极器件，因为它可以在低于900℃的温度下被注入和激活，并且即使在制造过程中经过许多热步骤之后也不会发生注入的锑离子的移动。因此，可以实现具有良好控制的通道长度的双栅极器件。

7. 发明授权

US07410845B2 Dual-gate device and method 有权
标题翻译：双栅极器件及方法
公开(公告)号：US07410845B2
公开(公告)日：2008-08-12
申请号：US11613102
申请日：2006-12-19
申请人： Andrew J. Walker
发明人： Andrew J. Walker
IPC分类号： H01L21/84 , H01L21/00 , H01L21/336
CPC分类号： H01L29/42344 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/4232 , H01L29/42328 , H01L29/42332 , H01L29/7881
摘要： A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor layer has a thickness, such that when a pass voltage is applied to the gate electrode of the access device, the access device and the memory device remains isolated, such that the charge stored in the memory device is unaffected by the pass voltage. The pass voltage is determined from a range of voltages, when applied to the access device, has no effect on the threshold voltage of the memory device. The dual-gate memory cells can be used as building blocks for a non-volatile memory array, such as a memory array formed by NAND-strings. In such an array, during programming of a nearby memory device in a NAND string, in NAND-strings not to be programmed, if inversion regions are allowed to be formed in the semiconductor layer, or if the semiconductor layer is allowed to electrically float, electrical interaction exists between the access devices and the memory devices to inhibit programming of the memory devices.
摘要翻译：公开了一种具有双栅极存储单元的存储电路及其制造方法。双栅极存储单元各自包括存储器件和共享半导体层的存取器件，其各自的沟道区域设置在半导体层的不同表面上。半导体层具有厚度，使得当通路电压被施加到存取装置的栅电极时，存取装置和存储装置保持隔离，使得存储在存储装置中的电荷不受通过电压的影响。当施加到接入装置时，从电压范围确定通过电压对存储器件的阈值电压没有影响。双栅极存储器单元可以用作非易失性存储器阵列的构造块，诸如由NAND串形成的存储器阵列。在这样的阵列中，在NAND串中的附近的存储器件的编程期间，在不被编程的NAND串中，如果允许在半导体层中形成反转区域，或者允许半导体层电浮动，存取装置和存储装置之间存在电相互作用以阻止存储装置的编程。

8. 发明申请

US20080083943A1 DUAL-GATE MEMORY DEVICE AND OPTIMIZATION OF ELECTRICAL INTERACTION BETWEEN FRONT AND BACK GATES TO ENABLE SCALING 审中-公开
标题翻译：双门存储器件和前门和后门之间的电气互动优化到使能量程
公开(公告)号：US20080083943A1
公开(公告)日：2008-04-10
申请号：US11749094
申请日：2007-05-15
申请人： Andrew J. Walker
发明人： Andrew J. Walker
IPC分类号： H01L29/788 , G11C11/34 , H01L21/336
CPC分类号： H01L27/11568 , G11C16/3418 , H01L27/115 , H01L27/11578 , H01L27/1203 , H01L29/42344 , H01L29/78645 , H01L29/78648
摘要： A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor layer has a thickness such that electrical interaction between the access device and the memory device is characterized by a sensitivity parameter having a value within a predetermined range for a sub-threshold voltage applied to a gate electrode of the access device. To achieve good scalability of the dual-gate memory cells, the semiconductor layer between the memory device gate and access device gate can be thinned. This results in a larger sensitivity parameter but this parameter is still small enough to avoid memory charge disturbs. The dual-gate memory cells can be used as building blocks for a non-volatile memory array, such as a memory array formed by NAND-strings. In such an array, during programming of a nearby memory device in a NAND string, in NAND-strings not to be programmed, if inversion regions are allowed to be formed in the semiconductor layer, or if the semiconductor layer is allowed to electrically float, electrical interaction exists between the access devices and the memory devices to inhibit programming of the memory devices.
摘要翻译：公开了一种具有双栅极存储单元的存储电路及其制造方法。双栅极存储单元各自包括存储器件和共享半导体层的存取器件，其各自的沟道区域设置在半导体层的不同表面上。半导体层的厚度使得访问装置和存储装置之间的电气相互作用的特征在于对于施加到存取装置的栅电极的次级阈值电压，具有在预定范围内的值的灵敏度参数。为了实现双栅极存储器单元的良好的可扩展性，可以减少存储器件栅极和存取器件栅极之间的半导体层。这导致较大的灵敏度参数，但是该参数仍然足够小以避免存储器充电干扰。双栅极存储器单元可以用作非易失性存储器阵列的构造块，诸如由NAND串形成的存储器阵列。在这样的阵列中，在NAND串中的附近的存储器件的编程期间，在不被编程的NAND串中，如果允许在半导体层中形成反转区域，或者允许半导体层电浮动，存取装置和存储装置之间存在电相互作用以阻止存储装置的编程。

9. 发明申请

US20070284621A1 Dual-gate semiconductor devices with enhanced scalability 有权
标题翻译：具有增强可扩展性的双栅极半导体器件
公开(公告)号：US20070284621A1
公开(公告)日：2007-12-13
申请号：US11441567
申请日：2006-05-25
申请人： Andrew J. Walker
发明人： Andrew J. Walker
IPC分类号： H01L29/76 , H01L29/745
CPC分类号： H01L29/7881 , H01L21/28273 , H01L29/42324 , H01L29/66825 , H01L29/78645 , H01L29/78648 , H01L2924/0002 , H01L2924/00
摘要： A scalable semiconductor device is formed using control gates formed on opposite sides of a semiconductor layer. A first control gate is formed electrically isolated from a first surface of the semiconductor layer by a first dielectric layer, such that, when a first voltage is applied on the first control gate, a first depletion region is formed in the semiconductor layer opposite the first control gate. A second control gate and a third control gate are also formed, each isolated from the semiconductor region by a second dielectric layer formed on a second surface of the semiconductor layer opposite the first surface. The second and the third control gates are offset from the first control gate such that, when a second voltage is applied to the second and third control gates, depletion regions are formed opposite the second and third control gates, respectively, such that each of the depletion regions opposite the second and third control gates overlaps the first depletion region to serve as source and drain regions, when filled with mobile carriers, of a field-effect transistor to the first depletion region, which serves as a channel region of the field-effect transistor.
摘要翻译：使用形成在半导体层的相对侧上的控制栅极形成可伸缩半导体器件。第一控制栅极通过第一介电层与半导体层的第一表面电隔离，使得当在第一控制栅极上施加第一电压时，在与第一栅极相反的半导体层中形成第一耗尽区控制门还形成第二控制栅极和第三控制栅极，每个通过形成在与第一表面相对的半导体层的第二表面上的第二介电层与半导体区域隔离。第二和第三控制栅极偏离第一控制栅极，使得当第二电压施加到第二和第三控制栅极时，耗尽区分别与第二和第三控制栅极相对形成，使得每个与第二和第三控制栅极相对的耗尽区域与第一耗尽区域重叠，用作当场效应晶体管充满移动载流子的源极和漏极区域到第一耗尽区域时，其用作场效应晶体管的沟道区域，效应晶体管。

10. 发明授权

US07250646B2 TFT mask ROM and method for making same 有权
标题翻译： TFT掩模ROM及其制造方法
公开(公告)号：US07250646B2
公开(公告)日：2007-07-31
申请号：US10965780
申请日：2004-10-18
申请人： Andrew J. Walker , Christopher Petti
发明人： Andrew J. Walker , Christopher Petti
IPC分类号： H01L29/772
CPC分类号： H01L27/1128 , G11C17/12 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/105 , H01L27/11 , H01L27/1108 , H01L27/1116 , H01L27/112 , H01L27/1126 , H01L27/11286 , H01L27/11293 , H01L27/115 , H01L27/11517 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11568 , H01L27/11578 , H01L27/11803 , H01L27/1203 , H01L27/1214 , H01L29/66825
摘要： There is provided a monolithic three dimensional TFT mask ROM array. The array includes a plurality of device levels. Each of the plurality of device levels contains a first set of enabled TFTs and a second set of partially or totally disabled TFTs.
摘要翻译：提供了单片三维TFT掩模ROM阵列。该阵列包括多个设备级别。多个器件级中的每一个包含第一组使能TFT和第二组部分或完全禁用的TFT。

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