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1. 发明授权

US5394007A Isolated well and method of making 失效
标题翻译：隔离井和制作方法
公开(公告)号：US5394007A
公开(公告)日：1995-02-28
申请号：US119636
申请日：1993-09-13
申请人： Robert H. Reuss , David J. Monk , Christopher P. Dragon
发明人： Robert H. Reuss , David J. Monk , Christopher P. Dragon
IPC分类号： H01L21/761 , H01L21/8249 , H01L27/06 , H01L27/02 , H01L27/04
CPC分类号： H01L21/8249 , H01L21/761 , H01L27/0623
摘要： A junction isolated P-well is formed for high performance BiCMOS. Two dopants of opposite conductivity types are implanted and co-diffused inside an annular N-type region to form a narrow N-type buried layer positioned between two P-type regions. N-type buried layer is formed having P-type doped regions above and below the N-type buried layer so that the N-type buried layer is narrow. The P-type region above the N-type buried layer provides for a retrograde profile of the P-well formed above it. Besides the P-well isolation, the P-type region below the N-type buried layer acts as a ground plane which collects noise, which helps to prevent it from being coupled to other devices of the BiCMOS circuit.
摘要翻译：形成了用于高性能BiCMOS的结隔离P阱。相反导电类型的两种掺杂剂被注入并共扩散在环形N型区域内以形成位于两个P型区域之间的窄N型掩埋层。 N型掩埋层在N型掩埋层的上方和下方形成有P型掺杂区域，使得N型掩埋层窄。 N型掩埋层上方的P型区域提供了形成在其上的P阱的逆行剖面。除了P阱隔离之外，N型掩埋层以下的P型区域用作收集噪声的接地平面，这有助于防止其耦合到BiCMOS电路的其他器件。

2. 发明授权

US5268312A Method of forming isolated wells in the fabrication of BiCMOS devices 失效
标题翻译：在BiCMOS器件制造中形成隔离阱的方法
公开(公告)号：US5268312A
公开(公告)日：1993-12-07
申请号：US964700
申请日：1992-10-22
申请人： Robert H. Reuss , David J. Monk , Christopher P. Dragon
发明人： Robert H. Reuss , David J. Monk , Christopher P. Dragon
IPC分类号： H01L21/761 , H01L21/8249 , H01L27/06 , H01L21/266
CPC分类号： H01L21/8249 , H01L21/761 , H01L27/0623
摘要： A junction isolated P-well is formed for high performance BiCMOS. Two dopants of opposite conductivity types are implanted and co-diffused inside an annular N-type region to form a narrow N-type buried layer positioned between two P-type regions. N-type buried layer is formed having P-type doped regions above and below the N-type buried layer so that the N-type buried layer is narrow. The P-type region above the N-type buried layer provides for a retrograde profile of the P-well formed above it. Besides the P-well isolation, the P-type region below the N-type buried layer acts as a ground plane which collects noise, which helps to prevent it from being coupled to other devices of the BiCMOS circuit.
摘要翻译：形成了用于高性能BiCMOS的结隔离P阱。相反导电类型的两种掺杂剂被注入并共扩散在环形N型区域内以形成位于两个P型区域之间的窄N型掩埋层。 N型掩埋层在N型掩埋层的上方和下方形成有P型掺杂区域，使得N型掩埋层窄。 N型掩埋层上方的P型区域提供了形成在其上的P阱的逆行剖面。除了P阱隔离之外，N型掩埋层以下的P型区域用作收集噪声的接地平面，这有助于防止其耦合到BiCMOS电路的其他器件。

3. 发明授权

US5302534A Forming a vertical PNP transistor 失效
标题翻译：形成垂直PNP晶体管
公开(公告)号：US5302534A
公开(公告)日：1994-04-12
申请号：US844311
申请日：1992-03-02
申请人： David J. Monk , Robert H. Reuss , Jenny M. Ford
发明人： David J. Monk , Robert H. Reuss , Jenny M. Ford
IPC分类号： H01L21/331 , H01L21/8249 , H01L21/265 , H01L29/70
CPC分类号： H01L29/66272 , H01L21/8249 , Y10S148/011
摘要： A transistor (10) is formed by utilizing an isolated well (18) within a thin epitaxial layer (14). A base mask (22) that has a base opening (23) is applied to expose a portion of the isolated well (18). A low resistance collector enhancement (24) is formed within the well (18) by doping a portion of the well (18) through the base opening (23). A base region (26) is formed overlying the collector enhancement (24) by doping the well (18) through the base opening (23). Forming the collector enhancement (24) through the base opening (23), facilitates providing the collector enhancement (24) with a small area thereby minimizing the transistor's (10) parasitic collector capacitance value, collector resistance, and transit time.
摘要翻译：通过利用薄外延层（14）内的隔离阱（18）形成晶体管（10）。具有基部开口（23）的底座（22）被施加以暴露所述隔离井（18）的一部分。通过将井（18）的一部分通过基座开口（23）掺杂，在阱（18）内形成低电阻集电极增强（24）。通过将孔（18）掺杂穿过基座开口（23），形成覆盖集电极增强层（24）的基极区（26）。通过基极开口（23）形成集电极增强（24），有利于使集电极增强（24）具有小的面积，从而最小化晶体管（10）的寄生集电极电容值，集电极电阻和通过时间。

4. 发明授权

US5618688A Method of forming a monolithic semiconductor integrated circuit having an N-channel JFET 失效
标题翻译：形成具有N沟道JFET的单片半导体集成电路的方法
公开(公告)号：US5618688A
公开(公告)日：1997-04-08
申请号：US200035
申请日：1994-02-22
申请人： Robert H. Reuss , Frederic B. Shapiro
发明人： Robert H. Reuss , Frederic B. Shapiro
IPC分类号： H01L21/8249 , H01L27/06 , H01L21/70
CPC分类号： H01L27/0623 , H01L21/8249
摘要： An N-channel JFET (60) and a method of forming the N-channel JFET (60) in a BiCMOS process. The N-channel JFET (60) is monolithically fabricated with an N-channel IGFET (70), a P-channel IGFET (75), and an NPN BJT (80) in an epitaxial layer (21). The N-channel JFET (60) is formed in an isolated N-channel JFET region (24), the P-channel IGFET (75) is formed in an isolated P-channel IGFET region (27), and the NPN BJT (80) is formed in an isolated BJT region (29). The N-channel IGFET (70) is fabricated in a P-type well (26) that is not isolated from other N-channel IGFET's in the epitaxial layer (21). Accordingly, the N-channel JFET (60), the N-channel IGFET (70), the P-channel IGFET (75), and an NPN BJT (80) are monolithically formed in the BiCMOS process.
摘要翻译： N沟道JFET（60）以及在BiCMOS工艺中形成N沟道JFET（60）的方法。 N沟道JFET（60）在外延层（21）中用N沟道IGFET（70），P沟道IGFET（75）和NPN BJT（80）单片制造。 N沟道JFET（60）形成在隔离的N沟道JFET区域（24）中，P沟道IGFET（75）形成在隔离的P沟道IGFET区域（27）中，NPN BJT（80））形成在隔离的BJT区域（29）中。 N沟道IGFET（70）制造在P型阱（26）中，其不与外延层（21）中的其它N沟道IGFET隔离。因此，在BiCMOS工艺中，单片地形成N沟道JFET（60），N沟道IGFET（70），P沟道IGFET（75）和NPN BJT（80）。

5. 发明授权

US6137213A Field emission device having a vacuum bridge focusing structure and method 失效
标题翻译：具有真空桥聚焦结构和方法的场发射装置
公开(公告)号：US6137213A
公开(公告)日：2000-10-24
申请号：US176150
申请日：1998-10-21
申请人： Curtis D. Moyer , Peter A. Smith , Robert H. Reuss , Troy A. Trottier , Steven A. Voight , Diane A. Carrillo , Kevin J. Nordquist , Jaynal A. Molla , David W. Jacobs , Kathleen A. Tobin
发明人： Curtis D. Moyer , Peter A. Smith , Robert H. Reuss , Troy A. Trottier , Steven A. Voight , Diane A. Carrillo , Kevin J. Nordquist , Jaynal A. Molla , David W. Jacobs , Kathleen A. Tobin
IPC分类号： H01J1/304 , H01J29/46 , H01J29/94 , H01J31/12 , H01J1/02
CPC分类号： H01J29/467 , H01J31/127
摘要： A field emission device (100, 150) includes a cathode plate (102, 180) having electron emitters (116), an anode plate (104, 170) having a phosphor (107, 207, 307, 407) activated by electrons (119) emitted by electron emitters (116), and a vacuum bridge focusing structure (118, 158, 218, 318) for focusing electrons (119) emitted by electron emitters (116). Vacuum bridge focusing structure (118, 158, 218, 318) has landings (121, 122, 221, 322), which are attached to cathode plate (102, 180), and further has bridges (120, 220, 320), which extend above and beyond landings (121, 122, 221, 322, 421) to provide a self-supporting structure that is spaced apart from cathode plate (102, 180).
摘要翻译：场致发射器件（100,150）包括具有电子发射器（116）的阴极板（102,180），具有由电子激活的荧光体（107,207,307,407）的阳极板（104,170））和由电子发射器（116）发射的用于聚焦电子（119）的真空电桥聚焦结构（118,158,218,318）。真空桥聚焦结构（118,158,218,318）具有连接到阴极板（102,180）上的平台（121,122,221,322），并且还具有桥梁（120,220,320），其中（121,122,221,322,421）之上和之外延伸以提供与阴极板（102,180）间隔开的自支撑结构。

6. 发明授权

US5433150A Traveling crane 失效
标题翻译：旅行起重机
公开(公告)号：US5433150A
公开(公告)日：1995-07-18
申请号：US187666
申请日：1994-01-26
申请人： Herbert D. Long, Jr. , Robert H. Reuss
发明人： Herbert D. Long, Jr. , Robert H. Reuss
IPC分类号： B66C9/16 , B66C5/00
CPC分类号： B66C9/16
摘要： A gantry crane travelable along a pair of rails and having an overhead girder transverse to the direction of travel, first and second legs connected to the girder, a load carrying trolley movable along the girder to a first position adjacent the first leg and to a second position adjacent the second leg, first and second spaced apart motor drives mounted on one of the legs in engagement with one of the rails for moving the crane, and third and fourth spaced apart motor drives mounted on the other leg in engagement with the other rail for moving the crane. When the trolley is at the first position, the first and second drives are highly loaded and the third and fourth drives are lightly loaded. Thereby, the lightly loaded drives attempt to drive the second leg such that it leads the first leg and skews the crane. When the trolley is at the second position, the third and fourth drives are highly loaded and the first and second motor drives are lightly loaded. Consequently, the lightly loaded drives attempt to drive the first leg such that it leads the second leg and skews the crane. A power source is connected to the first and third drives and a power source is connected to the second and fourth drives. The power sources are responsive to the presence of the trolley at either its first or second position to provide a large portion of their electrical power to the highly loaded motor drives to prevent skew.
摘要翻译：沿着一对轨道行进并具有横向于行进方向的顶部梁的龙门起重机，连接到所述梁的第一和第二腿，沿着所述梁移动到第一位置的负载运载小车到与所述第一腿相邻的第一位置，与第二腿相邻的位置，第一和第二间隔开的电动机驱动器，其安装在一个腿上，与用于移动起重机的轨道之一接合，以及安装在另一个腿上的第三和第四间隔开的电动机驱动器与另一个轨道用于移动起重机。当手推车处于第一位置时，第一和第二驱动器是高负载的，第三和第四驱动器被轻轻地加载。因此，轻载驱动器试图驱动第二条腿，使得它引导第一条腿并使起重机偏斜。当手推车处于第二位置时，第三和第四驱动器是高负载的，并且第一和第二电动机驱动器被轻轻地加载。因此，轻载驱动器试图驱动第一条腿，使得它引导第二条腿并使起重机偏斜。电源连接到第一和第三驱动器，并且电源连接到第二和第四驱动器。电源响应于手推车在其第一或第二位置的存在，以便向高负载的电动机驱动器提供其大部分电力以防止偏斜。

7. 发明授权

US06633119B1 Field emission device having metal hydride hydrogen source 失效
标题翻译：具有金属氢化物氢源的场致发射器件
公开(公告)号：US06633119B1
公开(公告)日：2003-10-14
申请号：US09572529
申请日：2000-05-17
申请人： Babu R. Chalamala , Robert H. Reuss
发明人： Babu R. Chalamala , Robert H. Reuss
IPC分类号： H01J162
CPC分类号： H01J29/94 , H01J2329/00
摘要： A field emission display (100, 200) includes a cathode plate (102, 302), an anode plate (104, 204, 304), and a hydrogen source (146, 148, 129, 150, 246, 346, 270), which is preferably disposed on cathode plate (102, 302) or anode plate (104, 204, 304). Hydrogen source (146, 148, 129, 150, 246, 346, 270) is distributed over the active area of field emission display (100, 200) and is made from a metal hydride, which is selected from the group consisting of titanium hydride, vanadium hydride, zirconium hydride, hafnium hydride, niobium hydride, and tantalum hydride. The metal hydride can be activated to provide an isotope of hydrogen in situ.
摘要翻译：场致发射显示器（ 100,200 ）包括阴极板（ 102,302 ），），和氢源（ 146,148,129,150,246,346,270 ＆lt; PDAT＆gt;＆lt; PDAT＆gt; 104,204,304＆lt; ），其优选地设置在阴极板（ 102,302 PDAT>）或阳极板（ 104,204,304 ）。氢源（ 146,148,129,150,246,346,270 ）分布在场发射显示的有效区域（ 100,200 由金属氢化物制成，该金属氢化物选自氢化钛，氢化钒，氢化锆，氢化铪，氢化铌和氢化钽。可以活化金属氢化物以提供原位的氢同位素

8. 发明授权

US4663831A Method of forming transistors with poly-sidewall contacts utilizing deposition of polycrystalline and insulating layers combined with selective etching and oxidation of said layers 失效
标题翻译：利用多晶层和绝缘层的沉积与所述层的选择性蚀刻和氧化结合形成具有多侧壁接触的晶体管的方法
公开(公告)号：US4663831A
公开(公告)日：1987-05-12
申请号：US785640
申请日：1985-10-08
申请人： Mark S. Birrittella , Hang M. Liaw , Robert H. Reuss
发明人： Mark S. Birrittella , Hang M. Liaw , Robert H. Reuss
IPC分类号： H01L21/8222 , H01L21/285 , H01L21/331 , H01L27/082 , H01L29/73 , H01L21/20 , H01L21/76
CPC分类号： H01L21/28531 , H01L29/66287 , H01L29/732 , Y10S148/011 , Y10S148/02 , Y10S148/026 , Y10S148/05 , Y10S148/117 , Y10S148/164
摘要： Improved bipolar transistors having minimum base-collector and collector-substrate junction area are formed by using multiple polycrystalline (e.g. doped poly silicon) layers to make lateral contact to a pillar shaped single crystal device region. The lateral poly silicon contacts are isolated from each other and the substrate and extend to the upper surface of the device for external connections. The structure is made by depositing two dielectric-poly layer sandwiches, etching and oxidizing part of the poly silicon layers to provide isolated overlapping poly silicon regions, etching a first hole through both poly silicon regions to the substrate, etching a second hole to the lower poly silicon layer, and filling the first and second holes with single and poly-crystalline silicon, respectfully. A sidewall oxide is formed at the periphery of the top of the single crystal pillar for defining the emitter location without additional masking.
摘要翻译：通过使用多个多晶（例如掺杂多晶硅）层来形成与柱状单晶器件区域的横向接触，形成具有最小基极集电极和集电极 - 衬底结面积的改进的双极晶体管。侧面多晶硅接触件彼此隔离并且衬底并延伸到设备的上表面用于外部连接。该结构通过沉积两个电介质多层三明治，蚀刻和氧化多个硅层的一部分而制成，以提供隔离的重叠多晶硅区域，将通过两个多晶硅区域的第一孔蚀刻到衬底，将第二个孔蚀刻到较低层多晶硅层，并且用单晶和多晶硅填充第一和第二孔。在单晶柱顶部的周围形成侧壁氧化物，用于限定发射器位置而不需要附加掩模。

9. 发明授权

US4631570A Integrated circuit having buried oxide isolation and low resistivity substrate for power supply interconnection 失效
标题翻译：具有埋置氧化物隔离的集成电路和用于电源互连的低电阻衬底
公开(公告)号：US4631570A
公开(公告)日：1986-12-23
申请号：US628019
申请日：1984-07-03
申请人： Mark S. Birrittella , Robert H. Reuss , Walter C. Seelbach
发明人： Mark S. Birrittella , Robert H. Reuss , Walter C. Seelbach
IPC分类号： H01L27/04 , H01L21/762 , H01L21/822 , H01L21/8222 , H01L23/528 , H01L27/06 , H01L27/082 , H01L27/12 , H01L27/02
CPC分类号： H01L21/76243 , H01L23/5286 , H01L27/0825 , H01L2924/0002 , Y10S148/083 , Y10S148/085 , Y10S257/906
摘要： An integrated circuit power supply interconnection technique is disclosed having a highly doped, low resistivity substrate for distribution of the integrated circuit's most positive supply voltage. The substrate functions as the most positive voltage point and accomodates devices that are normally connected directly to this most positive supply voltage. A dielectric buried layer overlies a portion of the substrate and isolates the substrate supply voltage from devices that are not connected directly to the most positive supply voltage.
摘要翻译：公开了一种集成电路电源互连技术，其具有用于分配集成电路最正电源电压的高掺杂的低电阻率衬底。衬底作为最正的电压点，并且适应通常直接连接到最正电源电压的器件。电介质掩埋层覆盖在衬底的一部分上，并将衬底电源电压与不直接连接到最正电源电压的器件隔离。

10. 发明授权

US06626720B1 Method of manufacturing vacuum gap dielectric field emission triode and apparatus 失效
标题翻译：制造真空间隙介质场发射三极管及其装置的方法
公开(公告)号：US06626720B1
公开(公告)日：2003-09-30
申请号：US09656912
申请日：2000-09-07
申请人： Emmett M. Howard , Curtis D. Moyer , Joseph Justin Bonanno , Robert H. Reuss
发明人： Emmett M. Howard , Curtis D. Moyer , Joseph Justin Bonanno , Robert H. Reuss
IPC分类号： H01J902
CPC分类号： B82Y10/00 , H01J3/022 , H01J9/025 , H01J2201/30469
摘要： A vacuum gap dielectric field emission triode and a method of fabrication include a conductive layer positioned on a supporting substrate and an emitter positioned on the conductive layer. A gate metal layer electrically separated from the conductive layer defines a metal bridge gate surrounding the emitter and separated from the emitter by a substantially fixed distance. The gate metal layer defines a gate opening through the metal bridge gate overlying the emitter. An anode is positioned in spaced relationship to the gate metal layer and the triode is sealed in a substantial vacuum so that the emitter is separated from the metal bridge by the substantial vacuum and the metal bridge is separated from the anode by the substantial vacuum.
摘要翻译：真空间隙介质场发射三极管和制造方法包括位于支撑衬底上的导电层和位于导电层上的发射极。与导电层电分离的栅极金属层限定了围绕发射极并与发射极分离大致固定距离的金属桥栅。栅极金属层限定通过覆盖发射极的金属桥接栅极的栅极开口。阳极以与栅极金属层隔开的关系定位，并且三极管被密封在实质的真空中，使得发射极通过实质的真空从金属桥分离，并且金属桥与实际真空下的阳极分离。

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