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1. 发明授权

US6127875A Complimentary double pumping voltage boost converter 有权
标题翻译：免费双重升压升压转换器
公开(公告)号：US6127875A
公开(公告)日：2000-10-03
申请号：US130343
申请日：1998-08-13
申请人： Steven Peter Allen , Ahmad H. Atriss , Gerald Lee Walcott , Walter C. Seelbach
发明人： Steven Peter Allen , Ahmad H. Atriss , Gerald Lee Walcott , Walter C. Seelbach
IPC分类号： H02M3/07 , H03L5/00
CPC分类号： H02M3/073
摘要： A voltage boosting circuit which derives an output voltage than is substantially twice the magnitude of a supply voltage applied thereto. The voltage boosting circuit consists of complementary acting boost circuits each having a pair of switches (42A, 52A; 42B, 52B) connected between an input of the voltage boosting circuit, at which is applied the supply voltage, and an output at which the output voltage is produced. Boost capacitors (48A, 48B) are connected between the respective switches of the complementary boost circuits and the switches of the these circuits are opened and closed out of phase with respect to each other in response to clocking signals being applied thereto such that a boosted output voltage is produced during each half cycle of the clocking signals.
摘要翻译：导出输出电压的升压电路基本上是施加到其上的电源电压的大小的两倍。升压电路包括互补作用升压电路，每个互补作用升压电路各自具有一对开关（42A，52A; 42B，52B），所述开关连接在施加电源电压的升压电路的输入端和输出端之间，产生电压。升压电容器（48A，48B）连接在互补升压电路的相应开关之间，并且这些电路的开关响应于施加到其上的时钟信号相对于彼此而异相地打开和闭合，使得升压输出在时钟信号的每个半周期产生电压。

2. 发明授权

US4779230A CMOS static ram cell provided with an additional bipolar drive transistor 失效
标题翻译： CMOS静态压电池提供一个额外的双极驱动晶体管
公开(公告)号：US4779230A
公开(公告)日：1988-10-18
申请号：US947124
申请日：1986-12-29
申请人： Kevin L. McLaughlin , Walter C. Seelbach
发明人： Kevin L. McLaughlin , Walter C. Seelbach
IPC分类号： G11C11/41 , G11C7/00
CPC分类号： G11C11/41
摘要： A BIMOS memory cell is formed by providing a CMOS static RAM cell with an additional NPN bipolar transistor to provide additional drive current during the read cycle to improve the read time of the memory cell.
摘要翻译：通过为CMOS静态RAM单元提供附加的NPN双极晶体管来形成BIMOS存储单元，以在读周期期间提供额外的驱动电流，以改善存储单元的读取时间。

3. 发明授权

US4635087A Monolithic bipolar SCR memory cell 失效
标题翻译：单片双极SCR存储单元
公开(公告)号：US4635087A
公开(公告)日：1987-01-06
申请号：US687530
申请日：1984-12-28
申请人： Mark S. Birrittella , Walter C. Seelbach
发明人： Mark S. Birrittella , Walter C. Seelbach
IPC分类号： G11C11/39 , G11C11/411 , H01L27/082 , H01L27/102 , H01L29/74 , G11C11/34 , H01L27/02 , H01L29/72
CPC分类号： H01L27/1025 , G11C11/39 , G11C11/4116 , H01L27/0826
摘要： Bipolar memory arrays having lower quiescent leakage and higher switching speed are constructed by using coupled SCRs formed from vertical PNP and NPN devices. Buried collectors for the PNP and NPN devices are provided within the same isolation tub. A P type plug is used to connect the P collector of the PNP to the P base of the NPN in a region where the P base and P collector overlap. A single N epi-region serves as the base of the PNP and the collector of the NPN. The P plug is located within this N epi-region but part of the N epi-region adjacent to or around the P plug is left so that internal connection of the PNP base and NPN collector is not cut off by the P plug. The structure is particularly suited for use in large memory arrays. The method of fabrication is also described.
摘要翻译：通过使用由垂直PNP和NPN器件形成的耦合SCR构成具有较低静态泄漏和较高开关速度的双极存储器阵列。 PNP和NPN设备的埋藏式收集器提供在同一隔离桶内。 P型插头用于在P基极和P集电极重叠的区域中将PNP的P集电极连接到NPN的P基极。单个N外延区域用作PNP的基极和NPN的收集器。 P插头位于该N外延区域内，但是与P插头相邻或附近的N外延区域的一部分保留，使得PNP基极和NPN集电极的内部连接不被P插头切断。该结构特别适用于大型存储器阵列。还描述了制造方法。

4. 发明授权

US4948991A Load controlled ECL transient driver 失效
标题翻译：负载控制ECL瞬态驱动器
公开(公告)号：US4948991A
公开(公告)日：1990-08-14
申请号：US266613
申请日：1988-11-03
申请人： Douglas W. Schucker , David B. Weaver , Pat Hickman , Walter C. Seelbach
发明人： Douglas W. Schucker , David B. Weaver , Pat Hickman , Walter C. Seelbach
IPC分类号： H03K19/01 , H03K19/013 , H03K19/086
CPC分类号： H03K19/086 , H03K19/0136
摘要： An ECL transient driver discharges a capacitive load at the output of an emitter follower with a pulse whose amplitude and duration is determined by the charge on the load. A pull-up transistor is coupled to an output terminal for selectively supplying a voltage thereto in response to a first signal from a logic circuit. A pull-down transistor is coupled to the output terminal for selectively sinking a current therefrom in response to a second signal. A comparator circuit is coupled to the pull-down transistor, the logic circuit, and the output terminal, for selectively providing the second signal in response to the first signal and an output voltage on the output terminal.

5. 发明授权

US4675554A NPN transient driver circuit 失效
标题翻译： NPN瞬态驱动电路
公开(公告)号：US4675554A
公开(公告)日：1987-06-23
申请号：US815846
申请日：1986-01-03
申请人： Daniel N. Koury, Jr. , Walter C. Seelbach
发明人： Daniel N. Koury, Jr. , Walter C. Seelbach
IPC分类号： H03K19/013 , H03K19/086 , H03K17/16 , H03K17/60 , H03K19/02
CPC分类号： H03K19/086 , H03K19/0136
摘要： A transient driver circuit for use with a logic circuit having an emitter-follower output stage that sources current to a load connected to an output thereof in response to an applied logic signal being at a first logic level. The transient driver circuit includes a first NPN transistor the collector-emitter path of which is coupled between the output of the logic circuit and the negative power supply rail, a second NPN transistor having its collector-emitter path couple between a positive power supply rail and the collector of the first NPN transistor and its base adapted to receive the logic signal and feedback circuitry that is responsive to a rise in the collector voltage of the second NPN transistor occurring as the logic signal switches to a second logic level for supplying current drive to the base of the first NPN transistor thereby turning it on to sink a large transient current at the output of the logic circuit.
摘要翻译：一种用于具有发射极跟随器输出级的逻辑电路的瞬态驱动器电路，其响应于所施加的逻辑信号处于第一逻辑电平而将电流供给连接到其输出的负载。瞬态驱动器电路包括第一NPN晶体管，其集电极 - 发射极路径耦合在逻辑电路的输出端和负电源轨道之间，第二NPN晶体管的集电极 - 发射极路径耦合在正电源轨和第一NPN晶体管的集电极及其基极适于接收响应于第二NPN晶体管的集电极电压升高而产生的逻辑信号和反馈电路，逻辑信号切换到第二逻辑电平以供应电流驱动第一NPN晶体管的基极由此导通，以在逻辑电路的输出端吸收大的瞬态电流。

6. 发明授权

US4570240A AC Transient driver for memory cells 失效
标题翻译： AC瞬态驱动器用于存储单元
公开(公告)号：US4570240A
公开(公告)日：1986-02-11
申请号：US566837
申请日：1983-12-29
申请人： Walter C. Seelbach , Robert R. Marley
发明人： Walter C. Seelbach , Robert R. Marley
IPC分类号： G11C11/414 , G11C11/415 , H03K17/60 , G11C7/00 , G11C8/00 , G11C11/00
CPC分类号： G11C11/415
摘要： A memory circuit is provided wherein the speed of the downward transition of the memory cell is increased. A plurality of memory cells are coupled between a select line and a current drain line. A first means is coupled to the select line for providing current to the plurality of memory cells and is responsive to a select signal having first and second states. A first PNP transistor has an emitter coupled to the current drain line for drawing any charge from the plurality of memory cells when the select signal transitions downward. A second means is coupled to the base of the first PNP transistor and is responsive to the select signal for setting the current level in said first PNP transistor. A second embodiment additionally includes a second PNP transistor having an emitter coupled to the select line and a collector coupled to said second supply voltage terminal for removing charge stored on the select line.
摘要翻译：提供了存储器电路，其中存储单元的向下转换的速度增加。多个存储单元耦合在选择线和电流漏极线之间。第一装置耦合到选择线，用于向多个存储单元提供电流，并响应于具有第一和第二状态的选择信号。当选择信号向下转变时，第一PNP晶体管具有耦合到电流漏极线的发射极，用于从多个存储器单元抽取任何电荷。第二装置耦合到第一PNP晶体管的基极，并且响应于选择信号来设置所述第一PNP晶体管中的电流电平。第二实施例另外包括具有耦合到选择线的发射极的第二PNP晶体管和耦合到所述第二电源电压端子的集电极，用于去除存储在选择线上的电荷。

7. 发明授权

US4423339A Majority logic gate 失效
标题翻译：多数逻辑门
公开(公告)号：US4423339A
公开(公告)日：1983-12-27
申请号：US237310
申请日：1981-02-23
申请人： Walter C. Seelbach , Boyd K. Hansen
发明人： Walter C. Seelbach , Boyd K. Hansen
IPC分类号： H03K19/23 , H03K5/08 , H03K19/092 , H03K19/094
CPC分类号： H03K19/23
摘要： A majority logic gate is comprised of a plurality of depletion mode switching devices and includes Schottky diodes for both level shifting and clamping the high logic level output voltage to ground. A plurality of MESFET input devices each have their gate electrode coupled to one input of the majority logic gate. Each MESFET input device has a source coupled to ground and a drain coupled to a current load device. The voltage level at the drain at each of the input devices changes from a logical "0" to a logical "1" state depending upon the number of inputs which are at a logical "1" level. The drain voltage is then level shifted down. The high logic level output voltage is clamped to ground by means of two Schottky diodes the first of which has a cathode coupled to ground and an anode coupled to the anode of the second diode, the cathode of the second diode being coupled to the output of the circuit.
摘要翻译：多数逻辑门由多个耗尽型开关器件组成，并包括用于电平移位并将高逻辑电平输出电压钳位到地的肖特基二极管。多个MESFET输入装置各自具有耦合到多数逻辑门的一个输入的栅电极。每个MESFET输入装置具有耦合到地的源极和耦合到当前负载装置的漏极。每个输入装置的漏极处的电压电平根据逻辑“1”电平的输入数从逻辑“0”变为逻辑“1”状态。然后漏极电压向下移位。高逻辑电平输出电压通过两个肖特基二极管钳位到地，第一个肖特基二极管具有耦合到地的阴极和耦合到第二二极管的阳极的阳极，第二二极管的阴极耦合到电路。

8. 发明授权

US4223238A Integrated circuit substrate charge pump 失效
标题翻译：集成电路基板电荷泵
公开(公告)号：US4223238A
公开(公告)日：1980-09-16
申请号：US934642
申请日：1978-08-17
申请人： Ward D. Parkinson , Walter C. Seelbach
发明人： Ward D. Parkinson , Walter C. Seelbach
IPC分类号： G05F3/20 , H03K1/02 , H03K1/12 , H03K3/26 , H03K3/64
CPC分类号： G05F3/205
摘要： An integrated circuit is disclosed which includes a charge pump adapted for biasing the substrate of a monolithic integrated circuit containing bipolar transistors. An oscillator operating under the control of a control input provides pulsed output signals for driving a diode-capacitor voltage multiplier network which generates a substrate bias voltage. A feedback network including a zener diode senses the substrate voltage, and switching action of the zener diode operates to selectively enable and disable the oscillator for regulating the substrate bias voltage.
摘要翻译：公开了一种集成电路，其包括适于偏置包含双极晶体管的单片集成电路的衬底的电荷泵。在控制输入的控制下工作的振荡器提供脉冲输出信号，用于驱动产生衬底偏置电压的二极管 - 电容器电压倍增器网络。包括齐纳二极管的反馈网络感测衬底电压，并且齐纳二极管的开关动作用于选择性地使能和禁止用于调节衬底偏置电压的振荡器。

9. 发明授权

US5440249A Voltage level translator circuit with cascoded output transistors 失效
标题翻译：具有级联输出晶体管的电压电平转换器电路
公开(公告)号：US5440249A
公开(公告)日：1995-08-08
申请号：US237570
申请日：1994-05-03
申请人： Douglas W. Schucker , Walter C. Seelbach
发明人： Douglas W. Schucker , Walter C. Seelbach
IPC分类号： H03K19/003 , H03K19/0185
CPC分类号： H03K3/356113 , H03K19/00315 , H03K19/018521
摘要： A voltage level translator circuit converts an input signal referenced between first and second operating potentials to an output signal referenced between second and third operating potentials. The input signal is level shifted through cascoded transistors and latched by series inverters to drive upper cascoded transistors in the output stage. The input signal is delayed before driving lower cascoded transistors in the output stage. The output stage transistors are cascoded in a similar manner as the level shifting section. The logic state of the input signal determines whether the upper cascoded transistors or the lower cascoded transistors in the output stage are activated to set the logic state of the output signal of the voltage level translator circuit. Additional cascoded transistors may be stacked to extend the range of voltage translation. The voltage level translator circuit is applicable to sub-micron technology.
摘要翻译：电压电平转换器电路将在第一和第二操作电位之间参考的输入信号转换为在第二和第三操作电位之间参考的输出信号。输入信号通过级联转换晶体管并由串联逆变器锁存，以驱动输出级的上级串联晶体管。在输出级驱动较低级联的晶体管之前，输入信号被延迟。输出级晶体管以与电平移位部分类似的方式被级联。输入信号的逻辑状态确定输出级中的上级联型晶体管或下级联型晶体管是否被激活，以设置电压电平转换器电路的输出信号的逻辑状态。可以堆叠附加的级联三极管以延长电压转换的范围。电压转换器电路适用于亚微米技术。

10. 发明授权

US5229967A BICMOS sense circuit for sensing data during a read cycle of a memory 失效
标题翻译： BICMOS感测电路，用于在存储器的读取周期期间感测数据
公开(公告)号：US5229967A
公开(公告)日：1993-07-20
申请号：US577375
申请日：1990-09-04
申请人： Scott G. Nogle , Robert P. Dixon , Walter C. Seelbach
发明人： Scott G. Nogle , Robert P. Dixon , Walter C. Seelbach
IPC分类号： G11C7/06 , G11C11/419
CPC分类号： G11C7/062 , G11C11/419
摘要： A bipolar complementary metal oxide semiconductor (BICMOS) sense circuit for sensing data on read data lines during a read cycle of a memory comprises a load portion and a sense amplifier portion. In one form, the load portion couples true and complement read data lines to a first voltage in response to a start of a read cycle. When the true and complement read data lines exceed a predetermined voltage, the sense amplifier is enabled. The load portion becomes inactive when the voltage on the read data lines reaches approximately the first voltage. Then a selected memory cell provides a differential voltage on a bit line pair, which is coupled to the read data lines, indicating the contents of the selected memory cell. The sense amplifier provides a differential current onto a corresponding read global data line pair in response to the differential voltage. At the termination of the read cycle, the load portion becomes active again and couples the read data lines to a second voltage to disable the sense amplifier. The predetermined voltage is between the first voltage and the second voltage. The circuit increases the speed of the sensing function over a CMOS design, while keeping power consumption to a minimum. In another form, the sense circuit generates a read sense voltage that is substantially independent of non-tracking process variations between P-channel and N-channel field-effect transistors.
摘要翻译：用于在存储器的读取周期期间读取数据线上的数据的双极互补金属氧化物半导体（BICMOS）感测电路包括负载部分和读出放大器部分。在一种形式中，负载部分响应于读周期的开始将真数和补码读数据线耦合到第一电压。当真实和补码读取数据线超过预定电压时，读出放大器使能。当读取数据线上的电压达到大约第一电压时，负载部分变为无效。然后，选择的存储单元在位线对上提供差分电压，位线对耦合到读取数据线，指示所选存储单元的内容。读出放大器响应于差分电压而将差分电流提供给对应的读取全局数据线对。在读周期结束时，负载部分再次变为有效，并将读数据线耦合到第二电压以禁用读出放大器。预定电压在第一电压和第二电压之间。该电路在CMOS设计中增加了感测功能的速度，同时将功耗降至最低。在另一种形式中，感测电路产生读取感测电压，其基本上与P沟道和N沟道场效应晶体管之间的非跟踪处理变化无关。

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