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1. 发明授权

US5302534A Forming a vertical PNP transistor 失效
标题翻译：形成垂直PNP晶体管
公开(公告)号：US5302534A
公开(公告)日：1994-04-12
申请号：US844311
申请日：1992-03-02
申请人： David J. Monk , Robert H. Reuss , Jenny M. Ford
发明人： David J. Monk , Robert H. Reuss , Jenny M. Ford
IPC分类号： H01L21/331 , H01L21/8249 , H01L21/265 , H01L29/70
CPC分类号： H01L29/66272 , H01L21/8249 , Y10S148/011
摘要： A transistor (10) is formed by utilizing an isolated well (18) within a thin epitaxial layer (14). A base mask (22) that has a base opening (23) is applied to expose a portion of the isolated well (18). A low resistance collector enhancement (24) is formed within the well (18) by doping a portion of the well (18) through the base opening (23). A base region (26) is formed overlying the collector enhancement (24) by doping the well (18) through the base opening (23). Forming the collector enhancement (24) through the base opening (23), facilitates providing the collector enhancement (24) with a small area thereby minimizing the transistor's (10) parasitic collector capacitance value, collector resistance, and transit time.
摘要翻译：通过利用薄外延层（14）内的隔离阱（18）形成晶体管（10）。具有基部开口（23）的底座（22）被施加以暴露所述隔离井（18）的一部分。通过将井（18）的一部分通过基座开口（23）掺杂，在阱（18）内形成低电阻集电极增强（24）。通过将孔（18）掺杂穿过基座开口（23），形成覆盖集电极增强层（24）的基极区（26）。通过基极开口（23）形成集电极增强（24），有利于使集电极增强（24）具有小的面积，从而最小化晶体管（10）的寄生集电极电容值，集电极电阻和通过时间。

2. 发明授权

US06492232B1 Method of manufacturing vertical semiconductor device 失效
标题翻译：垂直半导体器件制造方法
公开(公告)号：US06492232B1
公开(公告)日：2002-12-10
申请号：US09563796
申请日：2000-05-02
申请人： Zhirong Tang , Heemyong Park , Jenny M. Ford
发明人： Zhirong Tang , Heemyong Park , Jenny M. Ford
IPC分类号： H01L21336
CPC分类号： H01L29/66666 , H01L21/823885 , H01L29/1045 , H01L29/7827
摘要： An n-channel device (10) and a p-channel device (11) are formed from a single epitaxial silicon layer (60,61). During the deposition of the single epitaxial silicon layer (60,61), dopants are added to the epitaxial reaction chamber and subsequently changed to define a drain region (24,33), a channel region (27,34), and a source region (30,35). The dopant concentration is modified during the formation of the channel region (27,34) to create a doping profile (50). The doping profile (50) has a first profile (51) that is constant and a second profile (52) that changes.
摘要翻译：由单个外延硅层（60,61）形成n沟道器件（10）和p沟道器件（11）。在沉积单个外延硅层（60,61）期间，将掺杂物添加到外延反应室中，随后改变为限定漏极区（24,33），沟道区（27,34）和源极区（30,35）。掺杂剂浓度在沟道区（27,34）的形成过程中被修改以产生掺杂分布（50）。掺杂分布（50）具有恒定的第一分布（51）和改变的第二分布（52）。

3. 发明授权

US4902639A Process for making BiCMOS integrated circuit having a shallow trench bipolar transistor with vertical base contacts 失效
标题翻译：具有具有垂直基极触点的浅沟槽双极晶体管的BiCMOS集成电路的工艺
公开(公告)号：US4902639A
公开(公告)日：1990-02-20
申请号：US388885
申请日：1989-08-03
申请人： Jenny M. Ford
发明人： Jenny M. Ford
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8249 , H01L27/06 , H01L29/732
CPC分类号： H01L21/8249
摘要： An improved bipolar transistor of a BiCMOS integrated circuit is fabricated by utilizing a shallow trench structure. The shallow trench defines an active base and a self-aligned emitter. The base resistance of the transistor is reduced because a vertical, rather than lateral, link base, which connects an extrinsic base to the active base, is formed. In addition, the overall area is reduced, which provides for a lower collector to base capacitance.

4. 发明授权

US5872374A Vertical semiconductor device 失效
标题翻译：垂直半导体器件
公开(公告)号：US5872374A
公开(公告)日：1999-02-16
申请号：US625016
申请日：1996-03-29
申请人： Zhirong Tang , Heemyong Park , Jenny M. Ford
发明人： Zhirong Tang , Heemyong Park , Jenny M. Ford
IPC分类号： H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/10 , H01L29/78 , H01L29/76
CPC分类号： H01L29/66666 , H01L21/823885 , H01L27/0928 , H01L29/1037 , H01L29/1045 , H01L29/7827
摘要： An n-channel device (10) and a p-channel device (11) are formed from a single epitaxial silicon layer (60,61). During the deposition of the single epitaxial silicon layer (60,61), dopants are added to the epitaxial reaction chamber and subsequently changed to define a drain region (24,33), a channel region (27,34), and a source region (30,35). The dopant concentration is modified during the formation of the channel region (27,34) to create a doping profile (50). The doping profile (50) has a first profile (51) that is constant and a second profile (52) that changes.
摘要翻译：由单个外延硅层（60,61）形成n沟道器件（10）和p沟道器件（11）。在沉积单个外延硅层（60,61）期间，将掺杂物添加到外延反应室中，随后改变为限定漏极区（24,33），沟道区（27,34）和源极区（30,35）。掺杂剂浓度在沟道区（27,34）的形成过程中被修改以产生掺杂分布（50）。掺杂分布（50）具有恒定的第一分布（51）和改变的第二分布（52）。

5. 发明授权

US4782373A Self-aligned semiconductor device with non-diffusable contacts 失效
标题翻译：具有非扩散接触的自对准半导体器件
公开(公告)号：US4782373A
公开(公告)日：1988-11-01
申请号：US101694
申请日：1987-09-25
申请人： Clarence A. Lund , Jenny M. Ford
发明人： Clarence A. Lund , Jenny M. Ford
IPC分类号： H01L21/02 , H01L21/28 , H01L21/8244 , H01L27/11 , H01L29/78
CPC分类号： H01L28/20 , H01L21/28 , H01L27/11 , H01L27/1112
摘要： An active portion of a cell of a static RAM semiconductor device comprising a MOSFET and a variable resistor load device having non-diffused contacts which are self-aligned is described. A polycrystalline gate is used as a mask for the implantation of a source and a drain into a semiconductor substrate. Following the formation of a conformal dielectric layer and a conformal polycrystalline layer PtSi contacts are formed. These contacts are also aligned by the gate and do not diffuse and therefore may be spaced closely together. As the MOSFET of the device is turned "on" and "off" the resistance of the load device increases and decreases proportionately.
摘要翻译：描述了包括MOSFET和具有自对准的非扩散接触的可变电阻器负载装置的静态RAM半导体器件的单元的有源部分。多晶栅极用作将源极和漏极注入到半导体衬底中的掩模。在形成保形电介质层和共形多晶层PtSi接触之后形成。这些触点也由栅极对准，并且不会扩散，因此可以紧密地间隔开。随着器件的MOSFET“开”和“关”，负载装置的电阻按比例增加和减少。

6. 发明授权

US6127230A Vertical semiconductor device and method of manufacturing the same 失效
标题翻译：垂直半导体器件及其制造方法
公开(公告)号：US6127230A
公开(公告)日：2000-10-03
申请号：US94870
申请日：1998-06-15
申请人： Zhirong Tang , Heemyong Park , Jenny M. Ford
发明人： Zhirong Tang , Heemyong Park , Jenny M. Ford
IPC分类号： H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/10 , H01L29/78
CPC分类号： H01L29/66666 , H01L21/823885 , H01L27/0928 , H01L29/1037 , H01L29/1045 , H01L29/7827
摘要： An n-channel device (10) and a p-channel device (11) are formed from a single epitaxial silicon layer (60,61). During the deposition of the single epitaxial silicon layer (60,61), dopants are added to the epitaxial reaction chamber and subsequently changed to define a drain region (24,33), a channel region (27,34), and a source region (30,35). The dopant concentration is modified during the formation of the channel region (27,34) to create a doping profile (50). The doping profile (50) has a first profile (51) that is constant and a second profile (52) that changes.
摘要翻译：由单个外延硅层（60,61）形成n沟道器件（10）和p沟道器件（11）。在沉积单个外延硅层（60,61）期间，将掺杂物添加到外延反应室中，随后改变为限定漏极区（24,33），沟道区（27,34）和源极区（30,35）。掺杂剂浓度在沟道区（27,34）的形成过程中被修改以产生掺杂分布（50）。掺杂分布（50）具有恒定的第一分布（51）和改变的第二分布（52）。

7. 发明授权

US5721438A Heterojunction semiconductor device and method of manufacture 失效
标题翻译：异质结半导体器件及其制造方法
公开(公告)号：US5721438A
公开(公告)日：1998-02-24
申请号：US593306
申请日：1996-01-31
申请人： Zhirong Tang , Jenny M. Ford , John W. Steele
发明人： Zhirong Tang , Jenny M. Ford , John W. Steele
IPC分类号： H01L29/737 , H01L31/0328 , H01L31/0336
CPC分类号： H01L29/7378
摘要： A heterojunction bipolar transistor (HBT) (30) is formed to have a germanium composition profile (46) in a base region (32) that improves the tolerance of the HBT device (30) to manufacturing variations and reduces the sensitivity to emitter/base biases. A first region (40) of essentially constant germanium composition is formed at the interface of an emitter region (34) and the base region (32). The germanium composition profile (46) also has a second region (41) in which the germanium composition is increased linearly to provide an acceleration field by reducing the band gap in this second region (41). The acceleration field reduces the transit time of carriers and increases the frequency response of the HBT device (30).
摘要翻译：异质结双极晶体管（HBT）（30）形成为在基极区域（32）中具有锗组成分布（46），其改善了HBT器件（30）对制造变化的公差并降低了对发射极/基极的灵敏度偏见在发射极区域（34）和基极区域（32）的界面处形成基本上恒定的锗组成的第一区域（40）。锗组成轮廓（46）还具有第二区域（41），其中锗组合物线性增加以通过减小该第二区域（41）中的带隙来提供加速度场。加速度场减小了载波的通过时间，并增加了HBT设备的频率响应（30）。

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