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1. 发明公开

CN101207113A 半导体结构及其制造方法有权转让
公开(公告)号：CN101207113A
公开(公告)日：2008-06-25
申请号：CN200710108849.0
申请日：2007-06-05
申请人：台湾积体电路制造股份有限公司
发明人：余振华 , 邱文智 , 吴文进 , 涂宏荣 , 杨固峰
IPC分类号： H01L25/00 , H01L25/065 , H01L21/50
CPC分类号： H01L21/8221 , H01L21/76898 , H01L24/16 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L2224/05001 , H01L2224/05009 , H01L2224/05124 , H01L2224/05139 , H01L2224/05147 , H01L2224/05157 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05186 , H01L2224/05568 , H01L2224/05573 , H01L2224/05609 , H01L2224/05616 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05684 , H01L2224/13099 , H01L2225/06513 , H01L2225/06541 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/19041 , Y10S148/164 , H01L2924/00014 , H01L2924/0105 , H01L2924/01079 , H01L2924/013
摘要：本发明提供一种半导体结构及其制造方法，该半导体结构包括第一芯片、第二芯片及保护层。第一芯片包括第一衬底及位于第一衬底上方的第一接合垫。第二芯片具有第一表面和相对于第一表面的第二表面，且堆叠于第一芯片上。保护层包括垂直部分和水平部分，其中垂直部分位于第二芯片的侧壁上，水平部分延伸至第一芯片上方。本发明能够防止水气和化学物质对于半导体结构的污染，从而改善芯片间结合的可靠度。

2. 发明授权

CN101207113B 半导体结构及其制造方法有权转让
公开(公告)号：CN101207113B
公开(公告)日：2010-12-08
申请号：CN200710108849.0
申请日：2007-06-05
申请人：台湾积体电路制造股份有限公司
发明人：余振华 , 邱文智 , 吴文进 , 涂宏荣 , 杨固峰
IPC分类号： H01L25/00 , H01L25/065 , H01L21/50
CPC分类号： H01L21/8221 , H01L21/76898 , H01L24/16 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L2224/05001 , H01L2224/05009 , H01L2224/05124 , H01L2224/05139 , H01L2224/05147 , H01L2224/05157 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05186 , H01L2224/05568 , H01L2224/05573 , H01L2224/05609 , H01L2224/05616 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05684 , H01L2224/13099 , H01L2225/06513 , H01L2225/06541 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/19041 , Y10S148/164 , H01L2924/00014 , H01L2924/0105 , H01L2924/01079 , H01L2924/013
摘要：本发明提供一种半导体结构及其制造方法，该半导体结构包括第一芯片、第二芯片及保护层。第一芯片包括第一衬底及位于第一衬底上方的第一接合垫。第二芯片具有第一表面和相对于第一表面的第二表面，且堆叠于第一芯片上。保护层包括垂直部分和水平部分，其中垂直部分位于第二芯片的侧壁上，水平部分延伸至第一芯片上方。本发明能够防止水气和化学物质对于半导体结构的污染，从而改善芯片间结合的可靠度。

3. 发明申请

WO1981000489A1 SEMICONDUCTOR EMBEDDED LAYER TECHNOLOGY 审中-公开
标题翻译：半导体嵌入层技术
公开(公告)号：WO1981000489A1
公开(公告)日：1981-02-19
申请号：PCT/US1980000997
申请日：1980-08-07
申请人： MASSACHUSETTS INST TECHN
发明人： MASSACHUSETTS INST TECHN , BOZLER C , LINDLEY W , ALLEY G , MURPHY R
IPC分类号： H01L29/48
CPC分类号： H01L29/66424 , H01L21/02395 , H01L21/02532 , H01L21/02546 , H01L21/02639 , H01L21/743 , H01L23/4824 , H01L23/52 , H01L23/535 , H01L28/40 , H01L29/7722 , H01L2924/0002 , H01L2924/3011 , Y10S148/164 , H01L2924/00
摘要： A permeable base transistor (30) including a metal base layer (34) embedded in a semiconductor crystal (32) to separate collector (38) and emitter (40) regions and form a Schottky barrier with each. The metal base layer has at least one opening (37) through which the crystal semiconductor (32) joins the collector (38) and emitter (40) regions. Ohmic contacts (42, 44) are made to the emitter (40) and collector (38) regions. The width of all openings (37) in the base layer (34) is of the order of the zero bias depletion width corresponding to the carrier concentration in the opening. The thickness of the metal layer (34) is in the order of 10% if this zero bias depletion width. As a result, a potential barrier in each opening limits current flow over the lower portion of the bias range. With increasing forward base bias the potential in the openings, which is lower than along the metal of the base layer (34), is lowered sufficiently to permit substantial increase in the barrier limited current flow from the collector (38) to emitter (40). A method of fabricating this transistor as well as methods for forming integrated circuit structures are also disclosed. Metal and other layers may be selectively embedded in semiconductor crystal. Embedded metal layers may serve as interconnections between devices. Devices may be in a stacked configuration.

4. 发明申请

WO1988001436A1 PROCESS FOR FABRICATING STACKED MOS STRUCTURES 审中-公开
标题翻译：制作堆叠MOS结构的方法
公开(公告)号：WO1988001436A1
公开(公告)日：1988-02-25
申请号：PCT/US1987001892
申请日：1987-08-06
申请人： NCR CORPORATION
发明人： NCR CORPORATION , SZLUK, Nicholas, John , MILLER, Gayle, Wilburn
IPC分类号： H01L21/82
CPC分类号： H01L27/0688 , H01L21/8221 , Y10S148/164 , Y10S438/951
摘要： A process for fabricating a self-aligned three-dimensionally integrated circuit structure having two channel regions responsive to a common gate electrode (7) includes forming a relatively thick lift-off region (11) over and in alignment with the gate electrode (7). A thick oxide layer (16) is then deposited over the structure so as to form stressed oxide (18, 19) extending from the lift-off layer sidewalls. A selective etch of the stressed oxide (18, 19) follows. The relatively thick oxide (21) covering the lift-off layer (11) is then removed with the etch of the lift-off layer (11), the lift-off etch acting through the exposed lift-off layer sidewalls. The formation of an upper field effect transistor gate oxide (24) and a conformal deposition of polysilicon (26) retains the contour of the recess formed by the lift-off. The gate aligned recess is then filled with a dopant masking material (30) by deposition and etching, which dopant masking material (30) thereafter defines during implant or diffusion an upper field effect transistor channel region (59) self-aligned with the common gate electrode (7).

5. 发明申请

WO1985005495A1 AN INTERLAYER CONTACT FOR USE IN A STATIC RAM CELL 审中-公开
标题翻译：一个INTERLAYER联系人用于静态RAM单元
公开(公告)号：WO1985005495A1
公开(公告)日：1985-12-05
申请号：PCT/US1985000493
申请日：1985-03-25
申请人： MOTOROLA, INC.
发明人： MOTOROLA, INC. , WANG, Karl, L.
IPC分类号： H01L21/82
CPC分类号： H01L21/043 , H01L21/76889 , Y10S148/019 , Y10S148/147 , Y10S148/164 , Y10S257/903
摘要： A CMOS static RAM (10), which has P channel transistors (12, 14) formed in a second polysilicon layer (39, 40), N channel transistors (11, 13, 15, 16) formed in the substrate (48), and gates of both the N channel (11, 13, 15, 16) and P channel transistors (12, 14) formed in a first polysilicon layer (29, 30, 31, 32), requires that ohmic contact be made between semiconductor material of different conductivity type. The first polysilicon layer (29, 30, 31, 32) is N-type, and the second polysilicon layer (39, 40) is P-type. Ohmic contact therebetween is achieved by providing a silicide layer (35, 36) which is between these two layers and in physical contact with both. Ohmic contact between N-type regions (32) in the substrate (48) and the second polysilicon layer (39, 40) is similarly achieved by sandwiching silicide (34, 37) therebetween.

6. 发明申请

WO1995009438A1 THREE-DIMENSIONAL PROCESSOR USING TRANSFERRED THIN FILM CIRCUITS 审中-公开
标题翻译：使用转印薄膜电路的三维处理器
公开(公告)号：WO1995009438A1
公开(公告)日：1995-04-06
申请号：PCT/US1994011074
申请日：1994-09-29
申请人： KOPIN CORPORATION
发明人： KOPIN CORPORATION , ZAVRACKY, Paul, M. , ZAVRACKY, Matthew , VU, Duy-Phach , DINGLE, Brenda
IPC分类号： H01L25/18
CPC分类号： H01L25/50 , H01L23/49833 , H01L24/24 , H01L24/82 , H01L25/0657 , H01L25/18 , H01L2224/16145 , H01L2224/24225 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01033 , H01L2924/01039 , H01L2924/01047 , H01L2924/01061 , H01L2924/01072 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/10253 , H01L2924/10329 , H01L2924/12041 , H01L2924/12042 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , Y10S148/164 , H01L2924/00
摘要： A multi-layered structure is fabricated in which a microprocessor is configured in different layers and interconnected vertically through insulating layers which separate each circuit layer of the structure. Each circuit layer can be fabricated in a separate wafer or thin film material and then transferred onto the layered structure and interconnected.
摘要翻译：制造多层结构，其中微处理器被配置在不同的层中，并且通过隔离结构的每个电路层的绝缘层垂直互连。每个电路层可以制造在单独的晶片或薄膜材料中，然后转移到分层结构上并互连。

7. 发明申请

WO1994017548A1 METHOD FOR FORMING DEEP CONDUCTIVE FEEDTHROUGHS AND AN INTERCONNECT LAYER THAT INCLUDES FEEDTHROUGHS FORMED IN ACCORDANCE WITH THE METHOD 审中-公开
标题翻译：用于形成深层诱导性食物的方法和包括根据该方法形成的食物的互连层
公开(公告)号：WO1994017548A1
公开(公告)日：1994-08-04
申请号：PCT/US1994000371
申请日：1994-01-10
申请人： HUGHES AIRCRAFT COMPANY
发明人： HUGHES AIRCRAFT COMPANY , PINTER, Jerald, F.
IPC分类号： H01L21/48
CPC分类号： H01L21/76251 , H01L21/76898 , Y10S148/135 , Y10S148/164 , Y10S438/928 , Y10S438/973
摘要： An interconnect layer (40) for interposing between two active circuit layers of a multi-chip module (50). The interconnect layer includes a layer of silicon (14) having first surface and second surfaces. A first layer of dielectric material (16) is disposed over the first surface and a second layer of dielectric material (12) disposed over the second surface. The interconnect layer includes at least one electrically conductive feedthrough (42) that is formed within an opening made through the layer of silicon. The opening has sidewalls (22) that are coated with a dielectric material (24) and an electrically conductive material for providing a topside contact (26). A second contact (28) is formed from the backside of the silicon layer after removing the substrate (10). In accordance with the invention, the sidewalls have a slope associated therewith such that an area of the opening is larger at the first surface of the silicon layer than at the second surface of the silicon layer, thereby improving the contact metal step coverage. The silicon layer is comprised of silicon and has a thickness in the range of approximately 10 micrometers to approximately 50 micrometers. The opening is etched through the silicon layer with KOH to provide an inwardly sloping sidewall profile having an angle that is approximately equal to 54.7 degrees.
摘要翻译：一种用于插入多芯片模块（50）的两个有源电路层之间的互连层（40）。互连层包括具有第一表面和第二表面的硅层（14）。电介质材料（16）的第一层设置在第一表面上方，第二层介电材料（12）设置在第二表面之上。互连层包括形成在通过硅层制成的开口内的至少一个导电馈通（42）。开口具有涂覆有电介质材料（24）的侧壁（22）和用于提供顶侧触点（26）的导电材料。在去除衬底（10）之后，从硅层的背面形成第二接触（28）。根据本发明，侧壁具有与其相关联的斜面，使得在硅层的第一表面处的开口面积大于在硅层的第二表面处的面积，从而改善接触金属台阶覆盖。硅层由<100>硅组成，其厚度在约10微米至约50微米的范围内。用KOH将开口蚀刻通过<100>硅层，以提供具有大致等于54.7度的角度的向内倾斜的侧壁轮廓。

8. 发明公开

EP0463330A3 Iterative self-aligned contact metallization process 失效
标题翻译：迭代自对准接触金属化过程
公开(公告)号：EP0463330A3
公开(公告)日：1992-09-23
申请号：EP91107384.9
申请日：1991-05-07
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Coleman, Donald J., Jr.
IPC分类号： H01L21/90
CPC分类号： H01L21/76877 , H01L21/76802 , Y10S148/14 , Y10S148/164
摘要： A method is provided for forming multiple layers of interconnections adjacent a planar surface. A first insulator layer is formed adjacent the selected planar surface. A first conductor layer is formed adjacent the first insulator layer. A second insulator is formed adjacent the first conductor layer. A first cavity and a second cavity are formed, each having sidewalls extending through said second insulator layer and said first conductor layer. The first cavity is formed wider than the second cavity. A third insulator layer is conformally deposited adjacent the second insulator layer, such that sidewall insulators are deposited on sidewalls of the first cavity and such that the second cavity is substantially filled with insulator. An etch is performed through the first cavity to expose a portion of the planar surface. A second conductor layer is conformally deposited adjacent third insulator layer such that second conductor layer extends through the first cavity to contact the planar surface.

9. 发明公开

EP0317083A3 Single wafer moated signal processor 失效
标题翻译：单波轮运动信号处理器
公开(公告)号：EP0317083A3
公开(公告)日：1990-04-18
申请号：EP88309837.8
申请日：1988-10-20
申请人： GRUMMAN AEROSPACE CORPORATION
发明人： Solomon, Allen L.
IPC分类号： H01L25/04 , H01L29/06
CPC分类号： H01L25/0657 , H01L21/76264 , H01L21/76275 , H01L21/76283 , H01L2225/06551 , H01L2225/06565 , H01L2924/0002 , Y10S148/035 , Y10S148/164 , Y10S438/977 , H01L2924/00
摘要： The present invention is directed to the construction of an integrated circuit chip, and to the method of making such a chip from a plate or wafer. In accordance with the present invention a chip is formed to have conductive edge portions disposed on an insulator surface, which portions optionally may further be expanded into a pad (22). The insulating material electrically isolates the conductive edge portions from the semiconductive body (23) of the chip. The invention may be implemented in redundant fashion to effect a multiplicity of electrical connections to a set of bulk semiconductor integrated circuits formed on the wafer. Each exposed conductive portion on a chip edge and its optional surrounding conductive pad may be reliably surrounded by insulator so that electrical shorts to non-insulating regions are not experienced. By this edge surface structure integrated circuit elements may be stacked in an array (13), electrically connected at the edge surfaces (19) thereof, without hazard that any electrical regions of the integrated circuit elements may be contacted, save intentionally through a conductive lead (18) or film connected to the pads (22).

10. 发明公开

EP0276292A1 PROCESS FOR FABRICATING STACKED MOS STRUCTURES 失效
标题翻译：用于生产堆叠式MOS结构。
公开(公告)号：EP0276292A1
公开(公告)日：1988-08-03
申请号：EP87905391.0
申请日：1987-08-06
申请人： NCR CORPORATION
发明人： SZLUK, Nicholas, John , MILLER, Gayle, Wilburn
IPC分类号： H01L27 , H01L21 , H01L29
CPC分类号： H01L27/0688 , H01L21/8221 , Y10S148/164 , Y10S438/951
摘要： Un procédé de fabrication d'une structure d'un circuit intégré tridimensionnel auto-aligné ayant deux régions de canaux sensibles à une électrode de porte commune (7) consiste à former une région de décollage relativement épaisse (11) sur l'électrode de porte (7) et en alignement avec cette dernière. Une couche d'oxyde épaisse (16) est ensuite déposée sur la structure de manière à former un oxyde contraint (18, 19) s'étendant depuis les parois latérales de la couche de décollage. Une attaque sélective de l'oxyde contraint (18, 19) est ensuite effectuée. L'oxyde relativement épais (21) recouvrant la couche de décollage (11) est ensuite enlevé avec le décapage de la couche de décollage (11), le décapage s'effectuant au travers des parois latérales exposées de la couche de décollage. La formation d'un oxyde de porte d'un transistor à effet de champ supérieur (24) et d'un dépôt harmonique de polysilicium (26) retient le contour de l'évidement formé par le décollage. L'évidement aligné avec la porte est ensuite rempli d'un matériau de masquage dopant (30) par déposition et attaque, lequel matériau de masquage dopant (30) définit ensuite pendant l'implantation ou la diffusion une région de canaux de transistor à effet de champ supérieure (59) auto-alignée avec l'électrode de porte commune (7).

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