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1. 发明授权

US06229465B1 Built in self test method and structure for analog to digital converter 失效
标题翻译：内置模数转换器的自检方法和结构
公开(公告)号：US06229465B1
公开(公告)日：2001-05-08
申请号：US09303288
申请日：1999-04-30
申请人： Raymond J. Bulaga , Brooks A. Cummings , Douglas R. Firth , John L. Harris , Christina L. Newman , Donald L. Wheater
发明人： Raymond J. Bulaga , Brooks A. Cummings , Douglas R. Firth , John L. Harris , Christina L. Newman , Donald L. Wheater
IPC分类号： H03M110
CPC分类号： H03M1/108 , H03M1/46
摘要： A method and structure for testing an A to D converter containing a plurality of discrete components is provided. The testing methodology includes dividing the circuit into a number of segments of the discrete components (for testing purposes only) with each segment having the same number of discrete components or an unequal but known number of discrete components. The value of the components individually and collectively of each segment is tested and compared with the value of the corresponding components of at least one other segment, and an output signal is generated of the compared value of the segments being tested. Preferably, the components are in a ladder configuration and are either resistors or capacitors. The testing of the components takes place by impressing constant voltage reference signal to at least a portion of one of the segments, sampling and holding this value and then providing a similar reference signal to complementary components of the other of said segments being compared, and comparing the output signal from each of the segments.
摘要翻译：提供了一种用于测试包含多个分立组件的A到D转换器的方法和结构。测试方法包括将电路划分成分立组件的多个段（仅用于测试目的），每个段具有相同数目的离散组件或不等的已知数量的分立组件。对每个段的单独和统一的组件的值进行测试，并将其与至少一个其他段的对应组件的值进行比较，并且生成被测试段的比较值的输出信号。优选地，组件处于梯形结构中，并且是电阻器或电容器。组件的测试是通过将恒定的参考信号施加到至少一个段中的一部分，采样并保持该值，然后向被比较的所述段中的另一个的互补分量提供相似的参考信号，并比较来自每个段的输出信号。

2. 发明授权

US06333706B1 Built-in self-test for analog to digital converter 失效
标题翻译：内置模数转换器自检
公开(公告)号：US06333706B1
公开(公告)日：2001-12-25
申请号：US09365424
申请日：1999-08-02
申请人： Brooks A. Cummings , Douglas R. Firth , Donald L. Wheater
发明人： Brooks A. Cummings , Douglas R. Firth , Donald L. Wheater
IPC分类号： H03M110
CPC分类号： H03M1/108 , H03M1/12
摘要： An on-chip analog to digital converter (ADC) test circuit comprises a waveform generator for developing a known arbitrary waveform. A switch selectively connects the waveform generator to the ADC in a test mode or an internal analog input to the ADC in an operate mode. In the test mode the ADC develops a known sequence of digital codes. A signature register is connected to an output of the ADC for receiving and compressing the sequence of digital codes during the test mode. The register develops a single compressed signature representative of the entire ADC digital output sequence. The compression method may be used to test ADC monotonicity, linearity, and that there are no missing codes.
摘要翻译：片上模数转换器（ADC）测试电路包括用于开发已知任意波形的波形发生器。在工作模式下，开关选择性地将波形发生器连接到ADC，或者在ADC的内部模拟输入端连接ADC。在测试模式下，ADC开发了已知的数字代码序列。签名寄存器连接到ADC的输出端，用于在测试模式期间接收和压缩数字代码序列。该寄存器开发出整个ADC数字输出序列的单个压缩签名。压缩方法可用于测试ADC单调性，线性度，并且没有缺少代码。

3. 发明授权

US06618682B2 Method for test optimization using historical and actual fabrication test data 有权
公开(公告)号：US06618682B2
公开(公告)日：2003-09-09
申请号：US09838996
申请日：2001-04-20
申请人： Raymond J. Bulaga , Anne E. Gattiker , John L. Harris , Phillip J. Nigh , Leo A. Noel , William J. Thibault , Jody J. Van Horn , Donald L. Wheater
发明人： Raymond J. Bulaga , Anne E. Gattiker , John L. Harris , Phillip J. Nigh , Leo A. Noel , William J. Thibault , Jody J. Van Horn , Donald L. Wheater
IPC分类号： G01N3700
CPC分类号： H01L22/20
摘要： A method and system are provided that minimize wafer or package level test time without adversely impacting yields in downstream manufacturing processes or degrading outgoing quality levels. The method provides optimization by determining, a priority, the most effective set of tests for a given lot or wafer. The invention implements a method using a processor-based system involving the integration of multiple sources of data that include: historical and realtime, product specific and lot specific, from wafer fabrication data (i.e., process measurements, defect inspections, and parametric testing), product qualification test results, physical failure analysis results and manufacturing functional test results. These various forms of data are used to determine an optimal set of tests to run using a test application sequence, on a given product to optimize test time with minimum risk to yield or product quality.

4. 发明授权

US06549150B1 Integrated test structure and method for verification of microelectronic devices 失效
标题翻译：用于微电子器件验证的集成测试结构和方法
公开(公告)号：US06549150B1
公开(公告)日：2003-04-15
申请号：US09682536
申请日：2001-09-17
申请人： Raymond J. Bulaga , John K. Masi , Patrick W. Miller , Mark S. Styduhar , Donald L. Wheater
发明人： Raymond J. Bulaga , John K. Masi , Patrick W. Miller , Mark S. Styduhar , Donald L. Wheater
IPC分类号： H03M110
CPC分类号： H03M1/108 , H03M1/66
摘要： An integrated test structure adapted to facilitate manufacturing verification of microelectronic devices such as Digital to Analog Converters (DAC) is disclosed. The test circuitry and the Circuit Under Test (CUT) are placed on an IC along with an arbitrary amount of digital logic, which drives the input of the CUT. These inputs are translated into an analog output. During a manufacturing test, this output is measured in order to determine that the IC has been manufactured correctly. The analog input of the circuit is coupled to the analog output of the DAC. The digital output of the test circuitry is coupled to the digital logic on the IC. This configuration comprises a Built In Self Test (BIST) structure. The invention allows BIST by eliminating the need to measure the analog output of the DAC external to the IC, and enables testing the CUT by using standard digital BIST techniques.
摘要翻译：公开了一种适于促进诸如数模转换器（DAC）的微电子器件的制造验证的集成测试结构。测试电路和被测电路（CUT）放置在IC上以及任意数量的数字逻辑，驱动CUT的输入。这些输入被转换为模拟输出。在制造测试期间，测量该输出以确定IC已被正确地制造。电路的模拟输入耦合到DAC的模拟输出。测试电路的数字输出耦合到IC上的数字逻辑。该配置包括内置自检（BIST）结构。本发明通过消除对IC外部DAC的模拟输出的需求而允许BIST，并且能够使用标准数字BIST技术来测试CUT。

5. 发明申请

US20080082883A1 SYSTEM FOR AND METHOD OF PERFORMING HIGH SPEED MEMORY DIAGNOSTICS VIA BUILT-IN-SELF-TEST 有权
标题翻译：通过内置自检来执行高速记忆诊断的系统和方法
公开(公告)号：US20080082883A1
公开(公告)日：2008-04-03
申请号：US11531035
申请日：2006-09-12
申请人： Kevin W Gorman , Emory D. Keller , Michael R. Ouellette , Donald L. Wheater
发明人： Kevin W Gorman , Emory D. Keller , Michael R. Ouellette , Donald L. Wheater
IPC分类号： G01R31/28
CPC分类号： G11C29/44 , G11C2029/3202
摘要： A system for and method of performing high speed memory diagnostics via built-in-self-test (BIST) is disclosed. In particular, a test system includes a tester for testing an integrated circuit that includes a BIST circuit and a test control circuit. The BIST circuit further includes a BIST engine and fail logic for testing an imbedded memory array. The test control circuit includes three binary up/down counters, a variable delay, and a comparator circuit. A method of performing high speed memory diagnostics via BIST includes, but is not limited to, presetting the counters of the test control circuit, presetting the variable delay to a value that is equal to the latency of the fail logic, setting the BIST cycle counter to decrement mode, presetting the variable delay to zero, re-executing the test algorithm and performing a second test operation of capturing the fail data, and performing a third test operation of transmitting the fail data to the tester.
摘要翻译：公开了一种通过内置自检（BIST）执行高速存储器诊断的系统和方法。特别地，测试系统包括用于测试包括BIST电路和测试控制电路的集成电路的测试器。 BIST电路还包括用于测试嵌入式存储器阵列的BIST引擎和故障逻辑。测试控制电路包括三个二进制向上/向下计数器，可变延迟和比较器电路。通过BIST执行高速存储器诊断的方法包括但不限于预设测试控制电路的计数器，将可变延迟预设为等于故障逻辑的等待时间的值，设置BIST周期计数器将可变延迟预置为零，重新执行测试算法并执行捕获故障数据的第二测试操作，以及执行将失败数据发送给测试者的第三测试操作。

6. 发明授权

US07073100B2 Method for testing embedded DRAM arrays 失效
标题翻译：嵌入式DRAM阵列测试方法
公开(公告)号：US07073100B2
公开(公告)日：2006-07-04
申请号：US10065694
申请日：2002-11-11
申请人： Laura S. Chadwick , William R. Corbin , Jeffrey H. Dreibelbis , Erik A. Nelson , Thomas E. Obremski , Toshiharu Saitoh , Donald L. Wheater
发明人： Laura S. Chadwick , William R. Corbin , Jeffrey H. Dreibelbis , Erik A. Nelson , Thomas E. Obremski , Toshiharu Saitoh , Donald L. Wheater
IPC分类号： G11C29/00
CPC分类号： G11C29/12015 , G11C11/401 , G11C29/26 , G11C2207/104
摘要： A method and system for testing an embedded DRAM that includes DRAM blocks. The method including: generating a test data pattern in a processor based BIST system, for each DRAM block, performing a write of the test data pattern into the DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from the DRAM block; where for each DRAM block, the write of the test data pattern into the DRAM block is performed before the pause, and the read of the resulting data pattern from each DRAM block is performed after the pause; where at least a portion of the pause of two or more of the DRAM blocks overlap in time; and for each DRAM block comparing the test data pattern to the resulting data pattern.
摘要翻译：一种用于测试包括DRAM块的嵌入式DRAM的方法和系统。该方法包括：在基于处理器的BIST系统中为每个DRAM块生成测试数据模式，执行将测试数据模式写入DRAM块，执行预定时间段的暂停，以及执行读取来自DRAM块的结果数据模式; 对于每个DRAM块，在暂停之前执行将测试数据模式写入DRAM块，并且在暂停之后执行来自每个DRAM块的结果数据模式的读取; 其中两个或更多个DRAM块的暂停的至少一部分在时间上重叠; 并且对于每个DRAM块，将测试数据模式与所得到的数据模式进行比较。

7. 发明授权

US06426904B2 Structures for wafer level test and burn-in 失效
标题翻译：晶圆级测试和老化的结构
公开(公告)号：US06426904B2
公开(公告)日：2002-07-30
申请号：US09803500
申请日：2001-03-09
申请人： John E. Barth , Claude L. Bertin , Jeffrey H. Dreibelbis , Wayne F. Ellis , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , William R. Tonti , Donald L. Wheater
发明人： John E. Barth , Claude L. Bertin , Jeffrey H. Dreibelbis , Wayne F. Ellis , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , William R. Tonti , Donald L. Wheater
IPC分类号： G11C2900
CPC分类号： G01R31/2855 , G01R31/2806 , G01R31/2831 , G01R31/31905 , H01L2224/05624 , H01L2224/13 , H01L2224/45144 , H01L2224/45147 , H01L2924/00014
摘要： Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in. Connections to the wafer and between test engines and chips are provided along a membrane attached to the wafer. Membrane connectors can be formed or opened after the membrane is connected to the wafer so shorted chips can be disconnected. Preferably the membrane remains on the wafer after test, burn-in and dicing to provide a chip scale package. Thus, the very high cost of TCE matched materials, such as glass ceramic contactors, for wafer burn-in is avoided while providing benefit beyond test and burn-in for packaging.
摘要翻译：晶圆测试和老化是通过位于被测晶片上的状态机或可编程测试引擎完成的。每个测试引擎需要少于10个连接，并且每个测试引擎可以连接到多个芯片，例如晶片上的行或一列芯片。因此，仍然提供必须连接用于测试的晶片的焊盘数量，同时还提供大量的并行测试。测试引擎还允许并行的片上分配冗余，以便在老化完成后可以修复故障的芯片。此外，可编程测试引擎可以对其代码进行更改，因此可以修改测试程序以在晶圆制造之后考虑新的信息。在老化期间使用测试引擎向DRAM阵列提供高频写入信号，为阵列提供更高的有效电压，从而降低了老化所需的时间。沿着连接到晶片的膜提供与晶片和测试引擎与芯片之间的连接。膜连接器可以在膜连接到晶片之后形成或打开，因此短路芯片可以断开。优选地，膜在测试之后保留在晶片上，老化和切割以提供芯片级封装。因此，避免了TCE匹配材料（例如玻璃陶瓷接触器）用于晶片老化的非常高的成本，同时提供超出测试和包装封装的优点。

8. 发明授权

US06426641B1 Single pin performance screen ring oscillator with frequency division 失效
标题翻译：单针性能屏幕振荡器分频
公开(公告)号：US06426641B1
公开(公告)日：2002-07-30
申请号：US09177139
申请日：1998-10-21
申请人： Steven P. Koch , Donald L. Wheater , Larry Wissel
发明人： Steven P. Koch , Donald L. Wheater , Larry Wissel
IPC分类号： G01R3128
CPC分类号： G01R31/2882
摘要： An oscillator circuit on a chip with a single I/O node whose output generally corresponds to a performance level of the IC chip. The single I/O node provides an easy access and testing point for evaluating chip performance. The I/O node is used for coupling to the oscillator circuit, and for activating and monitoring its oscillating output signal. The single I/O node may be accessed at the wafer level, after packaging, or in the field.
摘要翻译：具有单个I / O节点的芯片上的振荡器电路，其输出通常对应于IC芯片的性能水平。单个I / O节点提供了一个易于访问和测试点来评估芯片性能。 I / O节点用于耦合到振荡器电路，并用于激活和监视其振荡输出信号。单个I / O节点可以在晶片级，封装之后或现场访问。

9. 发明授权

US08729549B2 Test structure and methodology for three-dimensional semiconductor structures 有权
标题翻译：三维半导体结构的测试结构和方法
公开(公告)号：US08729549B2
公开(公告)日：2014-05-20
申请号：US13533191
申请日：2012-06-26
申请人： Kerry Bernstein , Jerome L. Cann , Christopher M. Durham , Paul D. Kartschoke , Peter J. Klim , Donald L. Wheater
发明人： Kerry Bernstein , Jerome L. Cann , Christopher M. Durham , Paul D. Kartschoke , Peter J. Klim , Donald L. Wheater
IPC分类号： H01L23/58
CPC分类号： H01L22/32 , H01L21/4846 , H01L21/6835 , H01L21/76898 , H01L23/49827 , H01L24/11 , H01L24/13 , H01L25/0657 , H01L25/50 , H01L2221/6835 , H01L2224/13005 , H01L2224/16 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079
摘要： A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.
摘要翻译：在外围测试结构衬底内形成通孔的多个外围测试结构衬底（PTSS）。周边测试结构层和至少一个功能层通过通孔形成在多个PTSS的一侧上。多个PTSS通孔中的另一侧在外围测试结构层和至少一个功能层的制造过程中暴露出来，以提供用于在整个制造顺序中测试各个层的功能性的接入点。可以在完成所有至少一个功能层的所有制造之后执行C4键合。不需要3D组装载体或C4载体衬底，因为外围测试结构衬底具有足够的机械强度以支撑外围测试结构层和至少一个功能层。

10. 发明申请

US20120221910A1 MICROCONTROLLER FOR LOGIC BUILT-IN SELF TEST (LBIST) 有权
标题翻译：用于逻辑内置自检的微控制器（LBIST）
公开(公告)号：US20120221910A1
公开(公告)日：2012-08-30
申请号：US13469604
申请日：2012-05-11
申请人： Gary D. GRISE , David E. LACKEY , Steven F. OAKLAND , Donald L. Wheater
发明人： Gary D. GRISE , David E. LACKEY , Steven F. OAKLAND , Donald L. Wheater
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31724 , G01R31/31727
摘要： Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store a uniquely defined set of input and output signals to enable a logic BIST, and a plurality of latches adapted to store a plurality of values corresponding to a behavioral profile of a test clock.
摘要翻译：内置自检（BIST）微控制器集成电路，适用于逻辑验证。微控制器包括表示微控制器的分层描述的多个硬件描述语言文件，所述多个硬件描述语言文件包括电路设计元素库，多个库设计电路元件，适于存储唯一定义的输入和输出集合用于启用逻辑BIST的信号，以及适于存储对应于测试时钟的行为轮廓的多个值的多个锁存器。

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