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1. 发明授权

US06233184B1 Structures for wafer level test and burn-in 失效
标题翻译：晶圆级测试和老化的结构
公开(公告)号：US06233184B1
公开(公告)日：2001-05-15
申请号：US09191954
申请日：1998-11-13
申请人： John E. Barth , Claude L. Bertin , Jeffrey H. Dreibelbis , Wayne F. Ellis , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , William R. Tonti , Donald L. Wheater
发明人： John E. Barth , Claude L. Bertin , Jeffrey H. Dreibelbis , Wayne F. Ellis , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , William R. Tonti , Donald L. Wheater
IPC分类号： G11C2900
CPC分类号： G01R31/2855 , G01R31/2806 , G01R31/2831 , G01R31/31905 , H01L2224/05624 , H01L2224/13 , H01L2224/45144 , H01L2224/45147 , H01L2924/00014
摘要： Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in. Connections to the wafer and between test engines and chips are provided along a membrane attached to the wafer. Membrane connectors can be formed or opened after the membrane is connected to the wafer so shorted chips can be disconnected. Preferably the membrane remains on the wafer after test, burn-in and dicing to provide a chip scale package. Thus, the very high cost of TCE matched materials, such as glass ceramic contactors, for wafer burn-in is avoided while providing benefit beyond test and burn-in for packaging.
摘要翻译：晶圆测试和老化是通过位于被测晶片上的状态机或可编程测试引擎完成的。每个测试引擎需要少于10个连接，并且每个测试引擎可以连接到多个芯片，例如晶片上的行或一列芯片。因此，仍然提供必须连接用于测试的晶片的焊盘数量，同时还提供大量的并行测试。测试引擎还允许并行的片上分配冗余，以便在老化完成后可以修复故障的芯片。此外，可编程测试引擎可以对其代码进行更改，因此可以修改测试程序以在晶圆制造之后考虑新的信息。在老化期间使用测试引擎向DRAM阵列提供高频写入信号，为阵列提供更高的有效电压，从而降低老化所需的时间。沿着连接到晶片的膜提供与晶片和测试引擎与芯片之间的连接。膜连接器可以在膜连接到晶片之后形成或打开，因此短路芯片可以断开。优选地，膜在测试之后保留在晶片上，老化和切割以提供芯片级封装。因此，避免了TCE匹配材料（例如玻璃陶瓷接触器）用于晶片老化的非常高的成本，同时提供超出测试和包装封装的优点。

2. 发明授权

US06426904B2 Structures for wafer level test and burn-in 失效
标题翻译：晶圆级测试和老化的结构
公开(公告)号：US06426904B2
公开(公告)日：2002-07-30
申请号：US09803500
申请日：2001-03-09
申请人： John E. Barth , Claude L. Bertin , Jeffrey H. Dreibelbis , Wayne F. Ellis , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , William R. Tonti , Donald L. Wheater
发明人： John E. Barth , Claude L. Bertin , Jeffrey H. Dreibelbis , Wayne F. Ellis , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , William R. Tonti , Donald L. Wheater
IPC分类号： G11C2900
CPC分类号： G01R31/2855 , G01R31/2806 , G01R31/2831 , G01R31/31905 , H01L2224/05624 , H01L2224/13 , H01L2224/45144 , H01L2224/45147 , H01L2924/00014
摘要： Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in. Connections to the wafer and between test engines and chips are provided along a membrane attached to the wafer. Membrane connectors can be formed or opened after the membrane is connected to the wafer so shorted chips can be disconnected. Preferably the membrane remains on the wafer after test, burn-in and dicing to provide a chip scale package. Thus, the very high cost of TCE matched materials, such as glass ceramic contactors, for wafer burn-in is avoided while providing benefit beyond test and burn-in for packaging.
摘要翻译：晶圆测试和老化是通过位于被测晶片上的状态机或可编程测试引擎完成的。每个测试引擎需要少于10个连接，并且每个测试引擎可以连接到多个芯片，例如晶片上的行或一列芯片。因此，仍然提供必须连接用于测试的晶片的焊盘数量，同时还提供大量的并行测试。测试引擎还允许并行的片上分配冗余，以便在老化完成后可以修复故障的芯片。此外，可编程测试引擎可以对其代码进行更改，因此可以修改测试程序以在晶圆制造之后考虑新的信息。在老化期间使用测试引擎向DRAM阵列提供高频写入信号，为阵列提供更高的有效电压，从而降低了老化所需的时间。沿着连接到晶片的膜提供与晶片和测试引擎与芯片之间的连接。膜连接器可以在膜连接到晶片之后形成或打开，因此短路芯片可以断开。优选地，膜在测试之后保留在晶片上，老化和切割以提供芯片级封装。因此，避免了TCE匹配材料（例如玻璃陶瓷接触器）用于晶片老化的非常高的成本，同时提供超出测试和包装封装的优点。

3. 发明授权

US06255899B1 Method and apparatus for increasing interchip communications rates 失效
标题翻译：提高芯片间通信速率的方法和装置
公开(公告)号：US06255899B1
公开(公告)日：2001-07-03
申请号：US09388164
申请日：1999-09-01
申请人： Claude L. Bertin , Anthony R. Bonaccio , Erik L. Hedberg , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , Edward J. Nowak , William R. Tonti
发明人： Claude L. Bertin , Anthony R. Bonaccio , Erik L. Hedberg , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , Edward J. Nowak , William R. Tonti
IPC分类号： H01L2500
CPC分类号： H01L25/0657 , H01L24/73 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/16235 , H01L2224/17181 , H01L2224/32225 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2225/06517 , H01L2225/0652 , H01L2225/06555 , H01L2225/06589 , H01L2924/00014 , H01L2924/09701 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15192 , H01L2924/16152 , H01L2924/19041 , H01L2924/19105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00012 , H01L2924/00 , H01L2224/05599
摘要： An assembly is provided that includes an interposer having first and second substantially flat, opposed surfaces, and at least one speed critical signal line extending directly through the interposer from the first surface to the second surface. A first IC is coupled to the first surface of the interposer and has a first external connection mechanism coupled to the at least one speed critical signal line. A second IC is coupled to the second surface of the interposer and has a first external connection mechanism coupled to the at least one speed critical signal line. Preferably at least one non-speed critical signal line is provided within the interposer and is coupled to a second external connection mechanism of the first IC and/or the second IC for delivering non-speed critical signals thereto or for receiving such signals therefrom. A chip carrier having a cavity formed therein also may be provided wherein the second surface of the interposer is coupled to the chip carrier and the second IC is disposed within the cavity. One or more carrier signal lines may be provided within the chip carrier and coupled between the interposer and the second IC. The first and/or the second IC also may comprise control logic adapted to select a number of drivers within either IC that drive a particular signal line.
摘要翻译：提供了一种组件，其包括具有第一和第二基本上平坦的相对表面的插入件以及至少一个直线从第一表面延伸到第二表面的速度临界信号线。第一IC耦合到插入器的第一表面，并且具有耦合到至少一个速度临界信号线的第一外部连接机构。第二IC耦合到插入器的第二表面，并且具有耦合到至少一个速度临界信号线的第一外部连接机构。优选地，在插入器内提供至少一个非速度临界信号线，并且耦合到第一IC和/或第二IC的第二外部连接机构，用于向其递送非速度关键信号或用于从其接收这样的信号。还可以提供其中形成有空腔的芯片载体，其中插入器的第二表面耦合到芯片载体，并且第二IC设置在空腔内。可以在芯片载体内提供一个或多个载波信号线，并且耦合在插入器和第二IC之间。第一和/或第二IC还可以包括适于选择驱动特定信号线的IC内的多个驱动器的控制逻辑。

4. 发明授权

US5563086A Integrated memory cube, structure and fabrication 失效
标题翻译：集成存储立方体，结构和制造
公开(公告)号：US5563086A
公开(公告)日：1996-10-08
申请号：US406284
申请日：1995-03-17
申请人： Claude L. Bertin , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , Gordon A. Kelley, Jr.
发明人： Claude L. Bertin , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , Gordon A. Kelley, Jr.
IPC分类号： G11C5/00 , H01L25/065 , H01L21/70
CPC分类号： H01L25/0657 , G11C5/06 , H01L2224/48091 , H01L2225/0651 , H01L2225/06551 , H01L2225/06555 , H01L2225/06572 , H01L2225/06596 , H01L2924/10253
摘要： An integrated memory cube structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the functional appearance of a single, higher level memory chip. A memory/logic cube is formed having N memory chips and at least one logic chip, with each memory chip of the cube having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N.times.M memory devices appears at the cube's I/O pins. A corresponding fabrication technique includes an approach for facilitating metallization patterning on the side surface of the memory subunit.
摘要翻译：一种集成的存储立方体结构和制造方法，其中堆叠的半导体存储器芯片由控制逻辑芯片集成，使得更强大的存储器架构被定义为单个更高级存储器芯片的功能外观。形成具有N个存储器芯片和至少一个逻辑芯片的存储器/逻辑立方体，其中立方体的每个存储器芯片具有M个存储器件。控制逻辑芯片协调与N个存储器芯片的外部通信，使得具有NxM存储器件的单个存储器芯片架构出现在立方体的I / O引脚处。相应的制造技术包括用于在存储器子单元的侧表面上促进金属化图案化的方法。

5. 发明授权

US5561622A Integrated memory cube structure 失效
标题翻译：集成内存立方体结构
公开(公告)号：US5561622A
公开(公告)日：1996-10-01
申请号：US120993
申请日：1993-09-13
申请人： Claude L. Bertin , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , Gordon A. Kelley, Jr.
发明人： Claude L. Bertin , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , Gordon A. Kelley, Jr.
IPC分类号： G11C5/00 , H01L25/065 , G11C5/06 , H01L23/02
CPC分类号： H01L25/0657 , G11C5/06 , H01L2224/48091 , H01L2225/0651 , H01L2225/06551 , H01L2225/06555 , H01L2225/06572 , H01L2225/06596 , H01L2924/10253
摘要： An integrated memory cube structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the functional appearance of a single, higher level memory chip. A memory/logic cube is formed having N memory chips and at least one logic chip, with each memory chip of the cube having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N.times.M memory devices appears at the cube's I/O pins. A corresponding fabrication technique includes an approach for facilitating metallization patterning on the side surface of the memory subunit.
摘要翻译：一种集成的存储立方体结构和制造方法，其中堆叠的半导体存储器芯片由控制逻辑芯片集成，使得更强大的存储器架构被定义为单个更高级存储器芯片的功能外观。形成具有N个存储器芯片和至少一个逻辑芯片的存储器/逻辑立方体，其中立方体的每个存储器芯片具有M个存储器件。控制逻辑芯片协调与N个存储器芯片的外部通信，使得具有NxM存储器件的单个存储器芯片架构出现在立方体的I / O引脚处。相应的制造技术包括用于在存储器子单元的侧表面上促进金属化图案化的方法。

6. 发明授权

US06177729B1 Rolling ball connector 失效
标题翻译：滚球连接器
公开(公告)号：US06177729B1
公开(公告)日：2001-01-23
申请号：US09303290
申请日：1999-04-03
申请人： Joseph A. Benenati , Claude L. Bertin , William T. Chen , Thomas E. Dinan , Wayne F. Ellis , Wayne J. Howell , John U. Knickerbocker , Mark V. Pierson , William R. Tonti , Jerzy M. Zalesinski
发明人： Joseph A. Benenati , Claude L. Bertin , William T. Chen , Thomas E. Dinan , Wayne F. Ellis , Wayne J. Howell , John U. Knickerbocker , Mark V. Pierson , William R. Tonti , Jerzy M. Zalesinski
IPC分类号： H01L2348
CPC分类号： H01L24/16 , G01R1/0483 , H01L24/11 , H01L24/12 , H01L24/17 , H01L24/83 , H01L2224/05147 , H01L2224/05155 , H01L2224/05568 , H01L2224/05573 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/11003 , H01L2224/11334 , H01L2224/13099 , H01L2224/13111 , H01L2224/1319 , H01L2224/17051 , H01L2224/2919 , H01L2224/8319 , H01L2224/838 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/10253 , H01L2924/14 , H01L2924/15787 , H01L2924/3025 , H01L2924/351 , H05K1/111 , H05K3/321 , H05K2201/0133 , H05K2201/0212 , H05K2201/0221 , H05K2201/0233 , H05K2201/10234 , H05K2201/10734 , H05K2201/10992 , H05K2203/0307 , Y10T428/12472 , H01L2924/00 , H01L2924/3512 , H01L2924/00014
摘要： An integrated circuit assembly has pads of a chip electrically connected to pads of a substrate with rolling metal balls. A pliable material bonds the balls in movable contact with pads of the chip and substrate. Because the balls are relatively free to move, thermal expansion differences that would ordinarily cause enormous stresses in the attached joints of the prior art, simply cause rolling of the balls of the present invention, avoiding thermal stress altogether. Reliability of the connections is substantially improved as compared with C4 solder bumps, and chips can be safely directly mounted to such substrates as PC boards, despite substantial thermal mismatch.
摘要翻译：集成电路组件具有与滚动金属球电连接到衬底的焊盘的芯片焊盘。柔韧的材料将球与芯片和衬底的焊盘可动地接触。由于球相对自由移动，因此在现有技术的连接接头中通常会引起巨大应力的热膨胀差异简单地导致本发明的滚珠滚动，从而完全避免热应力。与C4焊料凸块相比，连接的可靠性大大提高，尽管存在大量的热失配，芯片可以安全地直接安装到诸如PC板的基板上。

7. 发明授权

US07132841B1 Carrier for test, burn-in, and first level packaging 失效
标题翻译：用于测试，老化和一级包装的载体
公开(公告)号：US07132841B1
公开(公告)日：2006-11-07
申请号：US09588617
申请日：2000-06-06
申请人： Claude L. Bertin , Wayne F. Ellis , Mark W. Kellogg , William R. Tonti , Jerzy M. Zalesinski , James M. Leas , Wayne J. Howell
发明人： Claude L. Bertin , Wayne F. Ellis , Mark W. Kellogg , William R. Tonti , Jerzy M. Zalesinski , James M. Leas , Wayne J. Howell
IPC分类号： G01R31/26 , G01R31/28
CPC分类号： G01R31/2867 , G11C5/04 , G11C29/06 , G11C29/1201 , G11C29/48 , G11C29/56016 , G11C29/785 , G11C2029/2602 , G11C2029/5602 , H01L22/22 , H01L22/32 , H01L2924/0002 , H01L2924/00
摘要： A plurality of semiconductor devices are provided on a carrier for testing or burning-in. The carrier is then cut up to provide single chip-on-carrier components or multi-chip-on-carrier components. The carrier is used as a first level package for each chip. Thus, the carrier serves a dual purpose for test and burn-in and for packaging. A lead reduction mechanism, such as a built-in self-test engine, can be provided on each chip or on the carrier and is connected to contacts of the carrier for the testing and burn-in steps. The final package after cutting includes at least one known good die and may include an array of chips on the carrier, such as a SIMM or a DIMM. The final package can also be a stack of chips each mounted on a separate carrier. The carriers of the stack are connected to each other through a substrate mounted along a side face of the stack that is electrically connected to a line of pads along an edge of each carrier. The carrier is formed of a flex material. It can also be formed of printed circuit board material. A window in the flex permits invoking redundancy on each chip after burn-in is complete, significantly improving yield as compared with present schemes that do not permit repair after burn-in.
摘要翻译：在载体上提供多个半导体器件用于测试或烧录。然后将载体切割以提供单个芯片上载波部件或多芯片载波部件。载体用作每个芯片的第一级封装。因此，载体用于测试和烧录和包装的双重目的。可以在每个芯片或载体上提供诸如内置自检引擎的引线减少机构，并且连接到载体的触点用于测试和老化步骤。切割后的最终包装包括至少一个已知的良好的模具，并且可以包括载体上的芯片阵列，例如SIMM或DIMM。最终的包装也可以是一堆芯片，每个芯片都安装在单独的载体上。堆叠的载体通过沿着堆叠的侧面安装的基板彼此连接，该基板沿着每个载体的边缘电连接到焊盘一排。载体由柔性材料形成。它也可以由印刷电路板材料形成。柔性窗口允许在烧坏完成后在每个芯片上调用冗余度，与不允许在老化后修复的现有方案相比，显着提高产量。

8. 发明授权

US07394268B2 Carrier for test, burn-in, and first level packaging 失效
标题翻译：用于测试，老化和一级包装的载体
公开(公告)号：US07394268B2
公开(公告)日：2008-07-01
申请号：US11531140
申请日：2006-09-12
申请人： Claude L. Bertin , Wayne F. Ellis , Mark W. Kellogg , William R. Tonti , Jerzy M. Zalesinski , James M. Leas , Wayne J. Howell
发明人： Claude L. Bertin , Wayne F. Ellis , Mark W. Kellogg , William R. Tonti , Jerzy M. Zalesinski , James M. Leas , Wayne J. Howell
IPC分类号： G01R31/02
CPC分类号： G01R31/2867 , G11C5/04 , G11C29/06 , G11C29/1201 , G11C29/48 , G11C29/56016 , G11C29/785 , G11C2029/2602 , G11C2029/5602 , H01L22/22 , H01L22/32 , H01L2924/0002 , H01L2924/00
摘要： A plurality of semiconductor devices are provided on a carrier for testing or burning-in. The carrier is then cut up to provide single chip-on-carrier components or multi-chip-on-carrier components. The carrier is used as a first level package for each chip. Thus, the carrier serves a dual purpose for test and burn-in and for packaging. A lead reduction mechanism, such as a built-in self-test engine, can be provided on each chip or on the carrier and is connected to contacts of the carrier for the testing and burn-in steps. The final package after cutting includes at least one known good die and may include an array of chips on the carrier, such as a SIMM or a DIMM. The final package can also be a stack of chips each mounted on a separate carrier. The carriers of the stack are connected to each other through a substrate mounted along a side face of the stack that is electrically connected to a line of pads along an edge of each carrier.
摘要翻译：在载体上提供多个半导体器件用于测试或烧录。然后将载体切割以提供单个芯片上载波部件或多芯片载波部件。载体用作每个芯片的第一级封装。因此，载体用于测试和烧录和包装的双重目的。可以在每个芯片或载体上提供诸如内置自检引擎的引线减少机构，并且连接到载体的触点用于测试和老化步骤。切割后的最终包装包括至少一个已知的良好的模具，并且可以包括载体上的芯片阵列，例如SIMM或DIMM。最终的包装也可以是一堆芯片，每个芯片都安装在单独的载体上。堆叠的载体通过沿着堆叠的侧面安装的基板彼此连接，该基板沿着每个载体的边缘电连接到焊盘一排。

9. 发明授权

US06358627B2 Rolling ball connector 有权
标题翻译：滚球连接器
公开(公告)号：US06358627B2
公开(公告)日：2002-03-19
申请号：US09768112
申请日：2001-01-23
申请人： Joseph A. Benenati , Claude L. Bertin , William T. Chen , Thomas E. Dinan , Wayne F. Ellis , Wayne J. Howell , John U. Knickerbocker , Mark V. Pierson , William R. Tonti , Jerzy M. Zalesinski
发明人： Joseph A. Benenati , Claude L. Bertin , William T. Chen , Thomas E. Dinan , Wayne F. Ellis , Wayne J. Howell , John U. Knickerbocker , Mark V. Pierson , William R. Tonti , Jerzy M. Zalesinski
IPC分类号： H01L2144
CPC分类号： H01L24/16 , G01R1/0483 , H01L24/11 , H01L24/12 , H01L24/17 , H01L24/83 , H01L2224/05147 , H01L2224/05155 , H01L2224/05568 , H01L2224/05573 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/11003 , H01L2224/11334 , H01L2224/13099 , H01L2224/13111 , H01L2224/1319 , H01L2224/17051 , H01L2224/2919 , H01L2224/8319 , H01L2224/838 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/10253 , H01L2924/14 , H01L2924/15787 , H01L2924/3025 , H01L2924/351 , H05K1/111 , H05K3/321 , H05K2201/0133 , H05K2201/0212 , H05K2201/0221 , H05K2201/0233 , H05K2201/10234 , H05K2201/10734 , H05K2201/10992 , H05K2203/0307 , Y10T428/12472 , H01L2924/00 , H01L2924/3512 , H01L2924/00014
摘要： An integrated circuit assembly has pads of a chip electrically connected to pads of a substrate with rolling metal balls. A pliable material bonds the balls in movable contact with pads of the chip and substrate. Because the balls are relatively free to move, thermal expansion differences that would ordinarily cause enormous stresses in the attached joints of the prior art, simply cause rolling of the balls of the present invention, avoiding thermal stress altogether. Reliability of the connections is substantially improved as compared with C4 solder bumps, and chips can be safely directly mounted to such substrates as PC boards, despite substantial thermal mismatch.
摘要翻译：集成电路组件具有与滚动金属球电连接到衬底的焊盘的芯片焊盘。柔韧的材料将球与芯片和衬底的焊盘可动地接触。由于球相对自由移动，因此在现有技术的连接接头中通常会引起巨大应力的热膨胀差异简单地导致本发明的滚珠滚动，从而完全避免热应力。与C4焊料凸块相比，连接的可靠性大大提高，尽管存在大量的热失配，芯片可以安全地直接安装到诸如PC板的基板上。

10. 发明授权

US06369671B1 Voltage controlled transmission line with real-time adaptive control 有权
标题翻译：电压控制传输线具有实时自适应控制
公开(公告)号：US06369671B1
公开(公告)日：2002-04-09
申请号：US09281412
申请日：1999-03-30
申请人： Claude L. Bertin , Anthony R. Bonaccio , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , Edward J. Nowak , William R. Tonti
发明人： Claude L. Bertin , Anthony R. Bonaccio , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , Edward J. Nowak , William R. Tonti
IPC分类号： H01P1185
CPC分类号： G11C7/12
摘要： A semiconductor structure having a substrate, an insulator above a portion of the substrate, a conductor above the insulator; and at least two contact regions in the substrate on opposite sides of the portion of the substrate, wherein a voltage between the contact regions modulates a capacitance of the conductor.
摘要翻译：一种具有衬底的半导体结构，在衬底的一部分上方的绝缘体，绝缘体上方的导体; 以及在所述衬底的所述部分的相对侧上的所述衬底中的至少两个接触区域，其中所述接触区域之间的电压调制所述导体的电容。

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